system.cc revision 8852:c744483edfcf
11689SN/A/* 212106SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2007 The Hewlett-Packard Development Company 39913Ssteve.reinhardt@amd.com * All rights reserved. 47854SAli.Saidi@ARM.com * 57854SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67854SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77854SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87854SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97854SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107854SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117854SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127854SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137854SAli.Saidi@ARM.com * 147854SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 152329SN/A * modification, are permitted provided that the following conditions are 161689SN/A * met: redistributions of source code must retain the above copyright 171689SN/A * notice, this list of conditions and the following disclaimer; 181689SN/A * redistributions in binary form must reproduce the above copyright 191689SN/A * notice, this list of conditions and the following disclaimer in the 201689SN/A * documentation and/or other materials provided with the distribution; 211689SN/A * neither the name of the copyright holders nor the names of its 221689SN/A * contributors may be used to endorse or promote products derived from 231689SN/A * this software without specific prior written permission. 241689SN/A * 251689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 261689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 271689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 281689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 291689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 301689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 311689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 321689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 331689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 341689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 351689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 361689SN/A * 371689SN/A * Authors: Gabe Black 381689SN/A */ 391689SN/A 402665Ssaidi@eecs.umich.edu#include "arch/x86/bios/intelmp.hh" 412665Ssaidi@eecs.umich.edu#include "arch/x86/bios/smbios.hh" 422935Sksewell@umich.edu#include "arch/x86/regs/misc.hh" 431689SN/A#include "arch/x86/isa_traits.hh" 441689SN/A#include "arch/x86/system.hh" 459944Smatt.horsnell@ARM.com#include "arch/vtophys.hh" 469944Smatt.horsnell@ARM.com#include "base/loader/object_file.hh" 479944Smatt.horsnell@ARM.com#include "base/loader/symtab.hh" 481060SN/A#include "base/intmath.hh" 491060SN/A#include "base/trace.hh" 503773Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 516329Sgblack@eecs.umich.edu#include "mem/port_proxy.hh" 526658Snate@binkert.org#include "params/X86System.hh" 531717SN/A#include "sim/byteswap.hh" 549913Ssteve.reinhardt@amd.com 558232Snate@binkert.orgusing namespace LittleEndianGuest; 568232Snate@binkert.orgusing namespace X86ISA; 579527SMatt.Horsnell@arm.com 585529Snate@binkert.orgX86System::X86System(Params *p) : 591060SN/A System(p), smbiosTable(p->smbios_table), 606221Snate@binkert.org mpFloatingPointer(p->intel_mp_pointer), 616221Snate@binkert.org mpConfigTable(p->intel_mp_table), 621061SN/A rsdp(p->acpi_description_table_pointer) 635529Snate@binkert.org{ 644329Sktlim@umich.edu} 654329Sktlim@umich.edu 662292SN/Astatic void 672292SN/AinstallSegDesc(ThreadContext *tc, SegmentRegIndex seg, 682292SN/A SegDescriptor desc, bool longmode) 692292SN/A{ 7012109SRekai.GonzalezAlberquilla@arm.com uint64_t base = desc.baseLow + (desc.baseHigh << 24); 711060SN/A bool honorBase = !longmode || seg == SEGMENT_REG_FS || 7210172Sdam.sunwoo@arm.com seg == SEGMENT_REG_GS || 7310172Sdam.sunwoo@arm.com seg == SEGMENT_REG_TSL || 7410172Sdam.sunwoo@arm.com seg == SYS_SEGMENT_REG_TR; 7510172Sdam.sunwoo@arm.com uint64_t limit = desc.limitLow | (desc.limitHigh << 16); 7610172Sdam.sunwoo@arm.com 772292SN/A SegAttr attr = 0; 7810328Smitch.hayenga@arm.com 7913453Srekai.gonzalezalberquilla@arm.com attr.dpl = desc.dpl; 8013453Srekai.gonzalezalberquilla@arm.com attr.unusable = 0; 8113453Srekai.gonzalezalberquilla@arm.com attr.defaultSize = desc.d; 8213453Srekai.gonzalezalberquilla@arm.com attr.longMode = desc.l; 8313453Srekai.gonzalezalberquilla@arm.com attr.avl = desc.avl; 8413453Srekai.gonzalezalberquilla@arm.com attr.granularity = desc.g; 8513453Srekai.gonzalezalberquilla@arm.com attr.present = desc.p; 8613453Srekai.gonzalezalberquilla@arm.com attr.system = desc.s; 8713453Srekai.gonzalezalberquilla@arm.com attr.type = desc.type; 8813453Srekai.gonzalezalberquilla@arm.com if (desc.s) { 8913453Srekai.gonzalezalberquilla@arm.com if (desc.type.codeOrData) { 9013453Srekai.gonzalezalberquilla@arm.com // Code segment 912292SN/A attr.expandDown = 0; 922292SN/A attr.readable = desc.type.r; 932292SN/A attr.writable = 0; 942292SN/A } else { 952292SN/A // Data segment 962292SN/A attr.expandDown = desc.type.e; 972292SN/A attr.readable = 1; 981060SN/A attr.writable = desc.type.w; 991060SN/A } 1001061SN/A } else { 1011060SN/A attr.readable = 1; 1022292SN/A attr.writable = 1; 1031062SN/A attr.expandDown = 0; 1041062SN/A } 1058240Snate@binkert.org 1061062SN/A tc->setMiscReg(MISCREG_SEG_BASE(seg), base); 1071062SN/A tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), honorBase ? base : 0); 1081062SN/A tc->setMiscReg(MISCREG_SEG_LIMIT(seg), limit); 1098240Snate@binkert.org tc->setMiscReg(MISCREG_SEG_ATTR(seg), (MiscReg)attr); 1101062SN/A} 1111062SN/A 1121062SN/Avoid 1138240Snate@binkert.orgX86System::initState() 1141062SN/A{ 1151062SN/A System::initState(); 1162301SN/A 1178240Snate@binkert.org if (kernel->getArch() == ObjectFile::I386) 1182301SN/A fatal("Loading a 32 bit x86 kernel is not supported.\n"); 1192301SN/A 1202292SN/A ThreadContext *tc = threadContexts[0]; 1218240Snate@binkert.org // This is the boot strap processor (BSP). Initialize it to look like 1222292SN/A // the boot loader has just turned control over to the 64 bit OS. We 1232292SN/A // won't actually set up real mode or legacy protected mode descriptor 1241062SN/A // tables because we aren't executing any code that would require 1258240Snate@binkert.org // them. We do, however toggle the control bits in the correct order 1261062SN/A // while allowing consistency checks and the underlying mechansims 1271062SN/A // just to be safe. 1281062SN/A 1298240Snate@binkert.org const int NumPDTs = 4; 1301062SN/A 1311062SN/A const Addr PageMapLevel4 = 0x70000; 1321062SN/A const Addr PageDirPtrTable = 0x71000; 1338240Snate@binkert.org const Addr PageDirTable[NumPDTs] = 1341062SN/A {0x72000, 0x73000, 0x74000, 0x75000}; 1351062SN/A const Addr GDTBase = 0x76000; 1361062SN/A 1378240Snate@binkert.org const int PML4Bits = 9; 1382292SN/A const int PDPTBits = 9; 1391062SN/A const int PDTBits = 9; 1401062SN/A 1418240Snate@binkert.org /* 1422292SN/A * Set up the gdt. 1431062SN/A */ 14410239Sbinhpham@cs.rutgers.edu uint8_t numGDTEntries = 0; 14510239Sbinhpham@cs.rutgers.edu // Place holder at selector 0 14610239Sbinhpham@cs.rutgers.edu uint64_t nullDescriptor = 0; 14710239Sbinhpham@cs.rutgers.edu physProxy.writeBlob(GDTBase + numGDTEntries * 8, 14810239Sbinhpham@cs.rutgers.edu (uint8_t *)(&nullDescriptor), 8); 14910239Sbinhpham@cs.rutgers.edu numGDTEntries++; 15010239Sbinhpham@cs.rutgers.edu 15110239Sbinhpham@cs.rutgers.edu //64 bit code segment 1521062SN/A SegDescriptor csDesc = 0; 1538240Snate@binkert.org csDesc.type.codeOrData = 1; 1541062SN/A csDesc.type.c = 0; // Not conforming 1551062SN/A csDesc.type.r = 1; // Readable 1561062SN/A csDesc.dpl = 0; // Privelege level 0 1578240Snate@binkert.org csDesc.p = 1; // Present 1581062SN/A csDesc.l = 1; // 64 bit 1591062SN/A csDesc.d = 0; // default operand size 1601062SN/A csDesc.g = 1; // Page granularity 1618240Snate@binkert.org csDesc.s = 1; // Not a system segment 1621062SN/A csDesc.limitHigh = 0xF; 1631062SN/A csDesc.limitLow = 0xFF; 1641062SN/A //Because we're dealing with a pointer and I don't think it's 1658240Snate@binkert.org //guaranteed that there isn't anything in a nonvirtual class between 1661062SN/A //it's beginning in memory and it's actual data, we'll use an 1671062SN/A //intermediary. 1681062SN/A uint64_t csDescVal = csDesc; 1698240Snate@binkert.org physProxy.writeBlob(GDTBase + numGDTEntries * 8, 1701062SN/A (uint8_t *)(&csDescVal), 8); 1711062SN/A 1722301SN/A numGDTEntries++; 1738240Snate@binkert.org 1742301SN/A SegSelector cs = 0; 1752301SN/A cs.si = numGDTEntries - 1; 1762301SN/A 1772301SN/A tc->setMiscReg(MISCREG_CS, (MiscReg)cs); 1788240Snate@binkert.org 1792301SN/A //32 bit data segment 1802301SN/A SegDescriptor dsDesc = 0; 1812301SN/A dsDesc.type.codeOrData = 0; 1822307SN/A dsDesc.type.e = 0; // Not expand down 1838240Snate@binkert.org dsDesc.type.w = 1; // Writable 1842307SN/A dsDesc.dpl = 0; // Privelege level 0 1852307SN/A dsDesc.p = 1; // Present 1862307SN/A dsDesc.d = 1; // default operand size 1877897Shestness@cs.utexas.edu dsDesc.g = 1; // Page granularity 1888240Snate@binkert.org dsDesc.s = 1; // Not a system segment 1897897Shestness@cs.utexas.edu dsDesc.limitHigh = 0xF; 1907897Shestness@cs.utexas.edu dsDesc.limitLow = 0xFF; 1917897Shestness@cs.utexas.edu uint64_t dsDescVal = dsDesc; 1928240Snate@binkert.org physProxy.writeBlob(GDTBase + numGDTEntries * 8, 1937897Shestness@cs.utexas.edu (uint8_t *)(&dsDescVal), 8); 1947897Shestness@cs.utexas.edu 19512109SRekai.GonzalezAlberquilla@arm.com numGDTEntries++; 19612109SRekai.GonzalezAlberquilla@arm.com 19712109SRekai.GonzalezAlberquilla@arm.com SegSelector ds = 0; 19812109SRekai.GonzalezAlberquilla@arm.com ds.si = numGDTEntries - 1; 19913610Sgiacomo.gabrielli@arm.com 20013610Sgiacomo.gabrielli@arm.com tc->setMiscReg(MISCREG_DS, (MiscReg)ds); 20113610Sgiacomo.gabrielli@arm.com tc->setMiscReg(MISCREG_ES, (MiscReg)ds); 20213610Sgiacomo.gabrielli@arm.com tc->setMiscReg(MISCREG_FS, (MiscReg)ds); 2031062SN/A tc->setMiscReg(MISCREG_GS, (MiscReg)ds); 2041062SN/A tc->setMiscReg(MISCREG_SS, (MiscReg)ds); 2051062SN/A 2061062SN/A tc->setMiscReg(MISCREG_TSL, 0); 20711246Sradhika.jagtap@ARM.com tc->setMiscReg(MISCREG_TSG_BASE, GDTBase); 20811246Sradhika.jagtap@ARM.com tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1); 20911246Sradhika.jagtap@ARM.com 21011246Sradhika.jagtap@ARM.com SegDescriptor tssDesc = 0; 21111246Sradhika.jagtap@ARM.com tssDesc.type = 0xB; 21211246Sradhika.jagtap@ARM.com tssDesc.dpl = 0; // Privelege level 0 21311246Sradhika.jagtap@ARM.com tssDesc.p = 1; // Present 21411246Sradhika.jagtap@ARM.com tssDesc.d = 1; // default operand size 21511246Sradhika.jagtap@ARM.com tssDesc.g = 1; // Page granularity 2162292SN/A tssDesc.s = 1; // Not a system segment 2171060SN/A tssDesc.limitHigh = 0xF; 2181060SN/A tssDesc.limitLow = 0xFF; 2191060SN/A uint64_t tssDescVal = tssDesc; 2201060SN/A physProxy.writeBlob(GDTBase + numGDTEntries * 8, 2211060SN/A (uint8_t *)(&tssDescVal), 8); 2221060SN/A 2231060SN/A numGDTEntries++; 2241060SN/A 2251060SN/A SegSelector tss = 0; 2261060SN/A tss.si = numGDTEntries - 1; 2271060SN/A 2281060SN/A tc->setMiscReg(MISCREG_TR, (MiscReg)tss); 2291060SN/A installSegDesc(tc, SYS_SEGMENT_REG_TR, tssDesc, true); 2301061SN/A 2311060SN/A /* 2322292SN/A * Identity map the first 4GB of memory. In order to map this region 2331060SN/A * of memory in long mode, there needs to be one actual page map level 2341060SN/A * 4 entry which points to one page directory pointer table which 2351060SN/A * points to 4 different page directory tables which are full of two 2361060SN/A * megabyte pages. All of the other entries in valid tables are set 2371060SN/A * to indicate that they don't pertain to anything valid and will 2381060SN/A * cause a fault if used. 2391060SN/A */ 2401061SN/A 2411060SN/A // Put valid values in all of the various table entries which indicate 2422292SN/A // that those entries don't point to further tables or pages. Then 2431060SN/A // set the values of those entries which are needed. 2441060SN/A 2451060SN/A // Page Map Level 4 2461060SN/A 2471060SN/A // read/write, user, not present 2481060SN/A uint64_t pml4e = X86ISA::htog(0x6); 2491060SN/A for (int offset = 0; offset < (1 << PML4Bits) * 8; offset += 8) { 2501061SN/A physProxy.writeBlob(PageMapLevel4 + offset, (uint8_t *)(&pml4e), 8); 2511060SN/A } 2529427SAndreas.Sandberg@ARM.com // Point to the only PDPT 2531060SN/A pml4e = X86ISA::htog(0x7 | PageDirPtrTable); 2549444SAndreas.Sandberg@ARM.com physProxy.writeBlob(PageMapLevel4, (uint8_t *)(&pml4e), 8); 2559444SAndreas.Sandberg@ARM.com 2569444SAndreas.Sandberg@ARM.com // Page Directory Pointer Table 2579444SAndreas.Sandberg@ARM.com 2589444SAndreas.Sandberg@ARM.com // read/write, user, not present 25913641Sqtt2@cornell.edu uint64_t pdpe = X86ISA::htog(0x6); 26013641Sqtt2@cornell.edu for (int offset = 0; offset < (1 << PDPTBits) * 8; offset += 8) { 26113641Sqtt2@cornell.edu physProxy.writeBlob(PageDirPtrTable + offset, 26213641Sqtt2@cornell.edu (uint8_t *)(&pdpe), 8); 26313641Sqtt2@cornell.edu } 26413641Sqtt2@cornell.edu // Point to the PDTs 26513641Sqtt2@cornell.edu for (int table = 0; table < NumPDTs; table++) { 26613641Sqtt2@cornell.edu pdpe = X86ISA::htog(0x7 | PageDirTable[table]); 26713641Sqtt2@cornell.edu physProxy.writeBlob(PageDirPtrTable + table * 8, 26813641Sqtt2@cornell.edu (uint8_t *)(&pdpe), 8); 26913641Sqtt2@cornell.edu } 27013641Sqtt2@cornell.edu 27113641Sqtt2@cornell.edu // Page Directory Tables 27213641Sqtt2@cornell.edu 27313641Sqtt2@cornell.edu Addr base = 0; 27413641Sqtt2@cornell.edu const Addr pageSize = 2 << 20; 27513641Sqtt2@cornell.edu for (int table = 0; table < NumPDTs; table++) { 27613641Sqtt2@cornell.edu for (int offset = 0; offset < (1 << PDTBits) * 8; offset += 8) { 27713641Sqtt2@cornell.edu // read/write, user, present, 4MB 27813641Sqtt2@cornell.edu uint64_t pdte = X86ISA::htog(0x87 | base); 27913641Sqtt2@cornell.edu physProxy.writeBlob(PageDirTable[table] + offset, 28013641Sqtt2@cornell.edu (uint8_t *)(&pdte), 8); 2819444SAndreas.Sandberg@ARM.com base += pageSize; 2829444SAndreas.Sandberg@ARM.com } 2839444SAndreas.Sandberg@ARM.com } 2849444SAndreas.Sandberg@ARM.com 2859444SAndreas.Sandberg@ARM.com /* 2869444SAndreas.Sandberg@ARM.com * Transition from real mode all the way up to Long mode 2879444SAndreas.Sandberg@ARM.com */ 2882329SN/A CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); 2896221Snate@binkert.org //Turn off paging. 2909444SAndreas.Sandberg@ARM.com cr0.pg = 0; 2919444SAndreas.Sandberg@ARM.com tc->setMiscReg(MISCREG_CR0, cr0); 2922292SN/A //Turn on protected mode. 29310239Sbinhpham@cs.rutgers.edu cr0.pe = 1; 29410239Sbinhpham@cs.rutgers.edu tc->setMiscReg(MISCREG_CR0, cr0); 2952292SN/A 2962292SN/A CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4); 2979444SAndreas.Sandberg@ARM.com //Turn on pae. 2989444SAndreas.Sandberg@ARM.com cr4.pae = 1; 2999444SAndreas.Sandberg@ARM.com tc->setMiscReg(MISCREG_CR4, cr4); 3009444SAndreas.Sandberg@ARM.com 3019444SAndreas.Sandberg@ARM.com //Point to the page tables. 30210239Sbinhpham@cs.rutgers.edu tc->setMiscReg(MISCREG_CR3, PageMapLevel4); 30310239Sbinhpham@cs.rutgers.edu 3049444SAndreas.Sandberg@ARM.com Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER); 3059444SAndreas.Sandberg@ARM.com //Enable long mode. 3062292SN/A efer.lme = 1; 3071060SN/A tc->setMiscReg(MISCREG_EFER, efer); 3081060SN/A 3092292SN/A //Start using longmode segments. 3102292SN/A installSegDesc(tc, SEGMENT_REG_CS, csDesc, true); 3116221Snate@binkert.org installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true); 3122292SN/A installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true); 3132292SN/A installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true); 3142292SN/A installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true); 3152292SN/A installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true); 3162292SN/A 3171061SN/A //Activate long mode. 3181060SN/A cr0.pg = 1; 3192292SN/A tc->setMiscReg(MISCREG_CR0, cr0); 3201060SN/A 3216221Snate@binkert.org tc->pcState(tc->getSystemPtr()->kernelEntry); 3226221Snate@binkert.org 3231060SN/A // We should now be in long mode. Yay! 3241060SN/A 3251061SN/A Addr ebdaPos = 0xF0000; 3261060SN/A Addr fixed, table; 3272292SN/A 3281060SN/A //Write out the SMBios/DMI table 3292292SN/A writeOutSMBiosTable(ebdaPos, fixed, table); 3302292SN/A ebdaPos += (fixed + table); 3311060SN/A ebdaPos = roundUp(ebdaPos, 16); 3322292SN/A 3332292SN/A //Write out the Intel MP Specification configuration table 3342292SN/A writeOutMPTable(ebdaPos, fixed, table); 3352292SN/A ebdaPos += (fixed + table); 3362292SN/A} 3371060SN/A 3381060SN/Avoid 3391061SN/AX86System::writeOutSMBiosTable(Addr header, 3402863Sktlim@umich.edu Addr &headerSize, Addr &structSize, Addr table) 3419444SAndreas.Sandberg@ARM.com{ 3421060SN/A // If the table location isn't specified, just put it after the header. 3439444SAndreas.Sandberg@ARM.com // The header size as of the 2.5 SMBios specification is 0x1F bytes 3449444SAndreas.Sandberg@ARM.com if (!table) 3459444SAndreas.Sandberg@ARM.com table = header + 0x1F; 3469444SAndreas.Sandberg@ARM.com smbiosTable->setTableAddr(table); 34711650Srekai.gonzalezalberquilla@arm.com 34811650Srekai.gonzalezalberquilla@arm.com smbiosTable->writeOut(physProxy, header, headerSize, structSize); 3499444SAndreas.Sandberg@ARM.com 3509444SAndreas.Sandberg@ARM.com // Do some bounds checking to make sure we at least didn't step on 3512863Sktlim@umich.edu // ourselves. 3522316SN/A assert(header > table || header + headerSize <= table); 3531060SN/A assert(table > header || table + structSize <= header); 3542316SN/A} 3552316SN/A 3562307SN/Avoid 3571060SN/AX86System::writeOutMPTable(Addr fp, 3589444SAndreas.Sandberg@ARM.com Addr &fpSize, Addr &tableSize, Addr table) 3599444SAndreas.Sandberg@ARM.com{ 3601060SN/A // If the table location isn't specified and it exists, just put 3619444SAndreas.Sandberg@ARM.com // it after the floating pointer. The fp size as of the 1.4 Intel MP 3629444SAndreas.Sandberg@ARM.com // specification is 0x10 bytes. 3639444SAndreas.Sandberg@ARM.com if (mpConfigTable) { 3649444SAndreas.Sandberg@ARM.com if (!table) 3656221Snate@binkert.org table = fp + 0x10; 3669444SAndreas.Sandberg@ARM.com mpFloatingPointer->setTableAddr(table); 3679444SAndreas.Sandberg@ARM.com } 3689444SAndreas.Sandberg@ARM.com 3699444SAndreas.Sandberg@ARM.com fpSize = mpFloatingPointer->writeOut(physProxy, fp); 3702307SN/A if (mpConfigTable) 3712307SN/A tableSize = mpConfigTable->writeOut(physProxy, table); 3722307SN/A else 3732307SN/A tableSize = 0; 3742307SN/A 3756221Snate@binkert.org // Do some bounds checking to make sure we at least didn't step on 3761858SN/A // ourselves and the fp structure was the size we thought it was. 37713831SAndrea.Mondelli@ucf.edu assert(fp > table || fp + fpSize <= table); 37813831SAndrea.Mondelli@ucf.edu assert(table > fp || table + tableSize <= fp); 3791858SN/A assert(fpSize == 0x10); 3802292SN/A} 3812292SN/A 3822292SN/A 3832292SN/AX86System::~X86System() 3843788Sgblack@eecs.umich.edu{ 3852292SN/A delete smbiosTable; 3862698Sktlim@umich.edu} 3873788Sgblack@eecs.umich.edu 3882301SN/Avoid 3893788Sgblack@eecs.umich.eduX86System::serialize(std::ostream &os) 3903788Sgblack@eecs.umich.edu{ 39113831SAndrea.Mondelli@ucf.edu System::serialize(os); 39213831SAndrea.Mondelli@ucf.edu} 39313831SAndrea.Mondelli@ucf.edu 3943788Sgblack@eecs.umich.edu 3953788Sgblack@eecs.umich.eduvoid 3963788Sgblack@eecs.umich.eduX86System::unserialize(Checkpoint *cp, const std::string §ion) 3973788Sgblack@eecs.umich.edu{ 3983788Sgblack@eecs.umich.edu System::unserialize(cp,section); 3993788Sgblack@eecs.umich.edu} 4003788Sgblack@eecs.umich.edu 4013788Sgblack@eecs.umich.eduX86System * 4022292SN/AX86SystemParams::create() 4032292SN/A{ 4042292SN/A return new X86System(this); 4052292SN/A} 4062292SN/A