system.cc revision 7447:3fc243687abb
1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 */ 39 40#include "arch/x86/bios/smbios.hh" 41#include "arch/x86/bios/intelmp.hh" 42#include "arch/x86/miscregs.hh" 43#include "arch/x86/system.hh" 44#include "arch/vtophys.hh" 45#include "base/intmath.hh" 46#include "base/loader/object_file.hh" 47#include "base/loader/symtab.hh" 48#include "base/trace.hh" 49#include "cpu/thread_context.hh" 50#include "mem/physical.hh" 51#include "params/X86System.hh" 52#include "sim/byteswap.hh" 53 54 55using namespace LittleEndianGuest; 56using namespace X86ISA; 57 58X86System::X86System(Params *p) : 59 System(p), smbiosTable(p->smbios_table), 60 mpFloatingPointer(p->intel_mp_pointer), 61 mpConfigTable(p->intel_mp_table), 62 rsdp(p->acpi_description_table_pointer) 63{} 64 65static void 66installSegDesc(ThreadContext *tc, SegmentRegIndex seg, 67 SegDescriptor desc, bool longmode) 68{ 69 uint64_t base = desc.baseLow + (desc.baseHigh << 24); 70 bool honorBase = !longmode || seg == SEGMENT_REG_FS || 71 seg == SEGMENT_REG_GS || 72 seg == SEGMENT_REG_TSL || 73 seg == SYS_SEGMENT_REG_TR; 74 uint64_t limit = desc.limitLow | (desc.limitHigh << 16); 75 76 SegAttr attr = 0; 77 78 attr.dpl = desc.dpl; 79 attr.unusable = 0; 80 attr.defaultSize = desc.d; 81 attr.longMode = desc.l; 82 attr.avl = desc.avl; 83 attr.granularity = desc.g; 84 attr.present = desc.p; 85 attr.system = desc.s; 86 attr.type = desc.type; 87 if (desc.s) { 88 if (desc.type.codeOrData) { 89 // Code segment 90 attr.expandDown = 0; 91 attr.readable = desc.type.r; 92 attr.writable = 0; 93 } else { 94 // Data segment 95 attr.expandDown = desc.type.e; 96 attr.readable = 1; 97 attr.writable = desc.type.w; 98 } 99 } else { 100 attr.readable = 1; 101 attr.writable = 1; 102 attr.expandDown = 0; 103 } 104 105 tc->setMiscReg(MISCREG_SEG_BASE(seg), base); 106 tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), honorBase ? base : 0); 107 tc->setMiscReg(MISCREG_SEG_LIMIT(seg), limit); 108 tc->setMiscReg(MISCREG_SEG_ATTR(seg), (MiscReg)attr); 109} 110 111void 112X86System::startup() 113{ 114 System::startup(); 115 ThreadContext *tc = threadContexts[0]; 116 // This is the boot strap processor (BSP). Initialize it to look like 117 // the boot loader has just turned control over to the 64 bit OS. We 118 // won't actually set up real mode or legacy protected mode descriptor 119 // tables because we aren't executing any code that would require 120 // them. We do, however toggle the control bits in the correct order 121 // while allowing consistency checks and the underlying mechansims 122 // just to be safe. 123 124 const int NumPDTs = 4; 125 126 const Addr PageMapLevel4 = 0x70000; 127 const Addr PageDirPtrTable = 0x71000; 128 const Addr PageDirTable[NumPDTs] = 129 {0x72000, 0x73000, 0x74000, 0x75000}; 130 const Addr GDTBase = 0x76000; 131 132 const int PML4Bits = 9; 133 const int PDPTBits = 9; 134 const int PDTBits = 9; 135 136 // Get a port to write the page tables and descriptor tables. 137 FunctionalPort * physPort = tc->getPhysPort(); 138 139 /* 140 * Set up the gdt. 141 */ 142 uint8_t numGDTEntries = 0; 143 // Place holder at selector 0 144 uint64_t nullDescriptor = 0; 145 physPort->writeBlob(GDTBase + numGDTEntries * 8, 146 (uint8_t *)(&nullDescriptor), 8); 147 numGDTEntries++; 148 149 //64 bit code segment 150 SegDescriptor csDesc = 0; 151 csDesc.type.codeOrData = 1; 152 csDesc.type.c = 0; // Not conforming 153 csDesc.type.r = 1; // Readable 154 csDesc.dpl = 0; // Privelege level 0 155 csDesc.p = 1; // Present 156 csDesc.l = 1; // 64 bit 157 csDesc.d = 0; // default operand size 158 csDesc.g = 1; // Page granularity 159 csDesc.s = 1; // Not a system segment 160 csDesc.limitHigh = 0xF; 161 csDesc.limitLow = 0xFF; 162 //Because we're dealing with a pointer and I don't think it's 163 //guaranteed that there isn't anything in a nonvirtual class between 164 //it's beginning in memory and it's actual data, we'll use an 165 //intermediary. 166 uint64_t csDescVal = csDesc; 167 physPort->writeBlob(GDTBase + numGDTEntries * 8, 168 (uint8_t *)(&csDescVal), 8); 169 170 numGDTEntries++; 171 172 SegSelector cs = 0; 173 cs.si = numGDTEntries - 1; 174 175 tc->setMiscReg(MISCREG_CS, (MiscReg)cs); 176 177 //32 bit data segment 178 SegDescriptor dsDesc = 0; 179 dsDesc.type.codeOrData = 0; 180 dsDesc.type.e = 0; // Not expand down 181 dsDesc.type.w = 1; // Writable 182 dsDesc.dpl = 0; // Privelege level 0 183 dsDesc.p = 1; // Present 184 dsDesc.d = 1; // default operand size 185 dsDesc.g = 1; // Page granularity 186 dsDesc.s = 1; // Not a system segment 187 dsDesc.limitHigh = 0xF; 188 dsDesc.limitLow = 0xFF; 189 uint64_t dsDescVal = dsDesc; 190 physPort->writeBlob(GDTBase + numGDTEntries * 8, 191 (uint8_t *)(&dsDescVal), 8); 192 193 numGDTEntries++; 194 195 SegSelector ds = 0; 196 ds.si = numGDTEntries - 1; 197 198 tc->setMiscReg(MISCREG_DS, (MiscReg)ds); 199 tc->setMiscReg(MISCREG_ES, (MiscReg)ds); 200 tc->setMiscReg(MISCREG_FS, (MiscReg)ds); 201 tc->setMiscReg(MISCREG_GS, (MiscReg)ds); 202 tc->setMiscReg(MISCREG_SS, (MiscReg)ds); 203 204 tc->setMiscReg(MISCREG_TSL, 0); 205 tc->setMiscReg(MISCREG_TSG_BASE, GDTBase); 206 tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1); 207 208 SegDescriptor tssDesc = 0; 209 tssDesc.type = 0xB; 210 tssDesc.dpl = 0; // Privelege level 0 211 tssDesc.p = 1; // Present 212 tssDesc.d = 1; // default operand size 213 tssDesc.g = 1; // Page granularity 214 tssDesc.s = 1; // Not a system segment 215 tssDesc.limitHigh = 0xF; 216 tssDesc.limitLow = 0xFF; 217 uint64_t tssDescVal = tssDesc; 218 physPort->writeBlob(GDTBase + numGDTEntries * 8, 219 (uint8_t *)(&tssDescVal), 8); 220 221 numGDTEntries++; 222 223 SegSelector tss = 0; 224 tss.si = numGDTEntries - 1; 225 226 tc->setMiscReg(MISCREG_TR, (MiscReg)tss); 227 installSegDesc(tc, SYS_SEGMENT_REG_TR, tssDesc, true); 228 229 /* 230 * Identity map the first 4GB of memory. In order to map this region 231 * of memory in long mode, there needs to be one actual page map level 232 * 4 entry which points to one page directory pointer table which 233 * points to 4 different page directory tables which are full of two 234 * megabyte pages. All of the other entries in valid tables are set 235 * to indicate that they don't pertain to anything valid and will 236 * cause a fault if used. 237 */ 238 239 // Put valid values in all of the various table entries which indicate 240 // that those entries don't point to further tables or pages. Then 241 // set the values of those entries which are needed. 242 243 // Page Map Level 4 244 245 // read/write, user, not present 246 uint64_t pml4e = X86ISA::htog(0x6); 247 for (int offset = 0; offset < (1 << PML4Bits) * 8; offset += 8) { 248 physPort->writeBlob(PageMapLevel4 + offset, (uint8_t *)(&pml4e), 8); 249 } 250 // Point to the only PDPT 251 pml4e = X86ISA::htog(0x7 | PageDirPtrTable); 252 physPort->writeBlob(PageMapLevel4, (uint8_t *)(&pml4e), 8); 253 254 // Page Directory Pointer Table 255 256 // read/write, user, not present 257 uint64_t pdpe = X86ISA::htog(0x6); 258 for (int offset = 0; offset < (1 << PDPTBits) * 8; offset += 8) { 259 physPort->writeBlob(PageDirPtrTable + offset, 260 (uint8_t *)(&pdpe), 8); 261 } 262 // Point to the PDTs 263 for (int table = 0; table < NumPDTs; table++) { 264 pdpe = X86ISA::htog(0x7 | PageDirTable[table]); 265 physPort->writeBlob(PageDirPtrTable + table * 8, 266 (uint8_t *)(&pdpe), 8); 267 } 268 269 // Page Directory Tables 270 271 Addr base = 0; 272 const Addr pageSize = 2 << 20; 273 for (int table = 0; table < NumPDTs; table++) { 274 for (int offset = 0; offset < (1 << PDTBits) * 8; offset += 8) { 275 // read/write, user, present, 4MB 276 uint64_t pdte = X86ISA::htog(0x87 | base); 277 physPort->writeBlob(PageDirTable[table] + offset, 278 (uint8_t *)(&pdte), 8); 279 base += pageSize; 280 } 281 } 282 283 /* 284 * Transition from real mode all the way up to Long mode 285 */ 286 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); 287 //Turn off paging. 288 cr0.pg = 0; 289 tc->setMiscReg(MISCREG_CR0, cr0); 290 //Turn on protected mode. 291 cr0.pe = 1; 292 tc->setMiscReg(MISCREG_CR0, cr0); 293 294 CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4); 295 //Turn on pae. 296 cr4.pae = 1; 297 tc->setMiscReg(MISCREG_CR4, cr4); 298 299 //Point to the page tables. 300 tc->setMiscReg(MISCREG_CR3, PageMapLevel4); 301 302 Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER); 303 //Enable long mode. 304 efer.lme = 1; 305 tc->setMiscReg(MISCREG_EFER, efer); 306 307 //Start using longmode segments. 308 installSegDesc(tc, SEGMENT_REG_CS, csDesc, true); 309 installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true); 310 installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true); 311 installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true); 312 installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true); 313 installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true); 314 315 //Activate long mode. 316 cr0.pg = 1; 317 tc->setMiscReg(MISCREG_CR0, cr0); 318 319 tc->setPC(tc->getSystemPtr()->kernelEntry); 320 tc->setNextPC(tc->readPC()); 321 322 // We should now be in long mode. Yay! 323 324 Addr ebdaPos = 0xF0000; 325 Addr fixed, table; 326 327 //Write out the SMBios/DMI table 328 writeOutSMBiosTable(ebdaPos, fixed, table); 329 ebdaPos += (fixed + table); 330 ebdaPos = roundUp(ebdaPos, 16); 331 332 //Write out the Intel MP Specification configuration table 333 writeOutMPTable(ebdaPos, fixed, table); 334 ebdaPos += (fixed + table); 335} 336 337void 338X86System::writeOutSMBiosTable(Addr header, 339 Addr &headerSize, Addr &structSize, Addr table) 340{ 341 // Get a port to write the table and header to memory. 342 FunctionalPort * physPort = threadContexts[0]->getPhysPort(); 343 344 // If the table location isn't specified, just put it after the header. 345 // The header size as of the 2.5 SMBios specification is 0x1F bytes 346 if (!table) 347 table = header + 0x1F; 348 smbiosTable->setTableAddr(table); 349 350 smbiosTable->writeOut(physPort, header, headerSize, structSize); 351 352 // Do some bounds checking to make sure we at least didn't step on 353 // ourselves. 354 assert(header > table || header + headerSize <= table); 355 assert(table > header || table + structSize <= header); 356} 357 358void 359X86System::writeOutMPTable(Addr fp, 360 Addr &fpSize, Addr &tableSize, Addr table) 361{ 362 // Get a port to write the table and header to memory. 363 FunctionalPort * physPort = threadContexts[0]->getPhysPort(); 364 365 // If the table location isn't specified and it exists, just put 366 // it after the floating pointer. The fp size as of the 1.4 Intel MP 367 // specification is 0x10 bytes. 368 if (mpConfigTable) { 369 if (!table) 370 table = fp + 0x10; 371 mpFloatingPointer->setTableAddr(table); 372 } 373 374 fpSize = mpFloatingPointer->writeOut(physPort, fp); 375 if (mpConfigTable) 376 tableSize = mpConfigTable->writeOut(physPort, table); 377 else 378 tableSize = 0; 379 380 // Do some bounds checking to make sure we at least didn't step on 381 // ourselves and the fp structure was the size we thought it was. 382 assert(fp > table || fp + fpSize <= table); 383 assert(table > fp || table + tableSize <= fp); 384 assert(fpSize == 0x10); 385} 386 387 388X86System::~X86System() 389{ 390 delete smbiosTable; 391} 392 393void 394X86System::serialize(std::ostream &os) 395{ 396 System::serialize(os); 397} 398 399 400void 401X86System::unserialize(Checkpoint *cp, const std::string §ion) 402{ 403 System::unserialize(cp,section); 404} 405 406X86System * 407X86SystemParams::create() 408{ 409 return new X86System(this); 410} 411