system.cc revision 12483
1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * Copyright (c) 2018 TU Dresden 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions are 17 * met: redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer; 19 * redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution; 22 * neither the name of the copyright holders nor the names of its 23 * contributors may be used to endorse or promote products derived from 24 * this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 27 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 29 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 30 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 31 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 32 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 * 38 * Authors: Gabe Black 39 * Maximilian Stein 40 */ 41 42#include "arch/x86/system.hh" 43 44#include "arch/x86/bios/intelmp.hh" 45#include "arch/x86/bios/smbios.hh" 46#include "arch/x86/isa_traits.hh" 47#include "base/loader/object_file.hh" 48#include "cpu/thread_context.hh" 49#include "params/X86System.hh" 50 51using namespace LittleEndianGuest; 52using namespace X86ISA; 53 54X86System::X86System(Params *p) : 55 System(p), smbiosTable(p->smbios_table), 56 mpFloatingPointer(p->intel_mp_pointer), 57 mpConfigTable(p->intel_mp_table), 58 rsdp(p->acpi_description_table_pointer) 59{ 60} 61 62void 63X86ISA::installSegDesc(ThreadContext *tc, SegmentRegIndex seg, 64 SegDescriptor desc, bool longmode) 65{ 66 uint64_t base = desc.baseLow + (desc.baseHigh << 24); 67 bool honorBase = !longmode || seg == SEGMENT_REG_FS || 68 seg == SEGMENT_REG_GS || 69 seg == SEGMENT_REG_TSL || 70 seg == SYS_SEGMENT_REG_TR; 71 uint64_t limit = desc.limitLow | (desc.limitHigh << 16); 72 if (desc.g) 73 limit = (limit << 12) | mask(12); 74 75 SegAttr attr = 0; 76 77 attr.dpl = desc.dpl; 78 attr.unusable = 0; 79 attr.defaultSize = desc.d; 80 attr.longMode = desc.l; 81 attr.avl = desc.avl; 82 attr.granularity = desc.g; 83 attr.present = desc.p; 84 attr.system = desc.s; 85 attr.type = desc.type; 86 if (desc.s) { 87 if (desc.type.codeOrData) { 88 // Code segment 89 attr.expandDown = 0; 90 attr.readable = desc.type.r; 91 attr.writable = 0; 92 } else { 93 // Data segment 94 attr.expandDown = desc.type.e; 95 attr.readable = 1; 96 attr.writable = desc.type.w; 97 } 98 } else { 99 attr.readable = 1; 100 attr.writable = 1; 101 attr.expandDown = 0; 102 } 103 104 tc->setMiscReg(MISCREG_SEG_BASE(seg), base); 105 tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), honorBase ? base : 0); 106 tc->setMiscReg(MISCREG_SEG_LIMIT(seg), limit); 107 tc->setMiscReg(MISCREG_SEG_ATTR(seg), (MiscReg)attr); 108} 109 110void 111X86System::initState() 112{ 113 System::initState(); 114 115 if (!kernel) 116 fatal("No kernel to load.\n"); 117 118 if (kernel->getArch() == ObjectFile::I386) 119 fatal("Loading a 32 bit x86 kernel is not supported.\n"); 120 121 ThreadContext *tc = threadContexts[0]; 122 // This is the boot strap processor (BSP). Initialize it to look like 123 // the boot loader has just turned control over to the 64 bit OS. We 124 // won't actually set up real mode or legacy protected mode descriptor 125 // tables because we aren't executing any code that would require 126 // them. We do, however toggle the control bits in the correct order 127 // while allowing consistency checks and the underlying mechansims 128 // just to be safe. 129 130 const int NumPDTs = 4; 131 132 const Addr PageMapLevel4 = 0x70000; 133 const Addr PageDirPtrTable = 0x71000; 134 const Addr PageDirTable[NumPDTs] = 135 {0x72000, 0x73000, 0x74000, 0x75000}; 136 const Addr GDTBase = 0x76000; 137 138 const int PML4Bits = 9; 139 const int PDPTBits = 9; 140 const int PDTBits = 9; 141 142 /* 143 * Set up the gdt. 144 */ 145 uint8_t numGDTEntries = 0; 146 // Place holder at selector 0 147 uint64_t nullDescriptor = 0; 148 physProxy.writeBlob(GDTBase + numGDTEntries * 8, 149 (uint8_t *)(&nullDescriptor), 8); 150 numGDTEntries++; 151 152 SegDescriptor initDesc = 0; 153 initDesc.type.codeOrData = 0; // code or data type 154 initDesc.type.c = 0; // conforming 155 initDesc.type.r = 1; // readable 156 initDesc.dpl = 0; // privilege 157 initDesc.p = 1; // present 158 initDesc.l = 1; // longmode - 64 bit 159 initDesc.d = 0; // operand size 160 initDesc.g = 1; // granularity 161 initDesc.s = 1; // system segment 162 initDesc.limitHigh = 0xF; 163 initDesc.limitLow = 0xFFFF; 164 initDesc.baseHigh = 0x0; 165 initDesc.baseLow = 0x0; 166 167 //64 bit code segment 168 SegDescriptor csDesc = initDesc; 169 csDesc.type.codeOrData = 1; 170 csDesc.dpl = 0; 171 //Because we're dealing with a pointer and I don't think it's 172 //guaranteed that there isn't anything in a nonvirtual class between 173 //it's beginning in memory and it's actual data, we'll use an 174 //intermediary. 175 uint64_t csDescVal = csDesc; 176 physProxy.writeBlob(GDTBase + numGDTEntries * 8, 177 (uint8_t *)(&csDescVal), 8); 178 179 numGDTEntries++; 180 181 SegSelector cs = 0; 182 cs.si = numGDTEntries - 1; 183 184 tc->setMiscReg(MISCREG_CS, (MiscReg)cs); 185 186 //32 bit data segment 187 SegDescriptor dsDesc = initDesc; 188 uint64_t dsDescVal = dsDesc; 189 physProxy.writeBlob(GDTBase + numGDTEntries * 8, 190 (uint8_t *)(&dsDescVal), 8); 191 192 numGDTEntries++; 193 194 SegSelector ds = 0; 195 ds.si = numGDTEntries - 1; 196 197 tc->setMiscReg(MISCREG_DS, (MiscReg)ds); 198 tc->setMiscReg(MISCREG_ES, (MiscReg)ds); 199 tc->setMiscReg(MISCREG_FS, (MiscReg)ds); 200 tc->setMiscReg(MISCREG_GS, (MiscReg)ds); 201 tc->setMiscReg(MISCREG_SS, (MiscReg)ds); 202 203 tc->setMiscReg(MISCREG_TSL, 0); 204 tc->setMiscReg(MISCREG_TSG_BASE, GDTBase); 205 tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1); 206 207 SegDescriptor tssDesc = initDesc; 208 uint64_t tssDescVal = tssDesc; 209 physProxy.writeBlob(GDTBase + numGDTEntries * 8, 210 (uint8_t *)(&tssDescVal), 8); 211 212 numGDTEntries++; 213 214 SegSelector tss = 0; 215 tss.si = numGDTEntries - 1; 216 217 tc->setMiscReg(MISCREG_TR, (MiscReg)tss); 218 installSegDesc(tc, SYS_SEGMENT_REG_TR, tssDesc, true); 219 220 /* 221 * Identity map the first 4GB of memory. In order to map this region 222 * of memory in long mode, there needs to be one actual page map level 223 * 4 entry which points to one page directory pointer table which 224 * points to 4 different page directory tables which are full of two 225 * megabyte pages. All of the other entries in valid tables are set 226 * to indicate that they don't pertain to anything valid and will 227 * cause a fault if used. 228 */ 229 230 // Put valid values in all of the various table entries which indicate 231 // that those entries don't point to further tables or pages. Then 232 // set the values of those entries which are needed. 233 234 // Page Map Level 4 235 236 // read/write, user, not present 237 uint64_t pml4e = X86ISA::htog(0x6); 238 for (int offset = 0; offset < (1 << PML4Bits) * 8; offset += 8) { 239 physProxy.writeBlob(PageMapLevel4 + offset, (uint8_t *)(&pml4e), 8); 240 } 241 // Point to the only PDPT 242 pml4e = X86ISA::htog(0x7 | PageDirPtrTable); 243 physProxy.writeBlob(PageMapLevel4, (uint8_t *)(&pml4e), 8); 244 245 // Page Directory Pointer Table 246 247 // read/write, user, not present 248 uint64_t pdpe = X86ISA::htog(0x6); 249 for (int offset = 0; offset < (1 << PDPTBits) * 8; offset += 8) { 250 physProxy.writeBlob(PageDirPtrTable + offset, 251 (uint8_t *)(&pdpe), 8); 252 } 253 // Point to the PDTs 254 for (int table = 0; table < NumPDTs; table++) { 255 pdpe = X86ISA::htog(0x7 | PageDirTable[table]); 256 physProxy.writeBlob(PageDirPtrTable + table * 8, 257 (uint8_t *)(&pdpe), 8); 258 } 259 260 // Page Directory Tables 261 262 Addr base = 0; 263 const Addr pageSize = 2 << 20; 264 for (int table = 0; table < NumPDTs; table++) { 265 for (int offset = 0; offset < (1 << PDTBits) * 8; offset += 8) { 266 // read/write, user, present, 4MB 267 uint64_t pdte = X86ISA::htog(0x87 | base); 268 physProxy.writeBlob(PageDirTable[table] + offset, 269 (uint8_t *)(&pdte), 8); 270 base += pageSize; 271 } 272 } 273 274 /* 275 * Transition from real mode all the way up to Long mode 276 */ 277 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); 278 //Turn off paging. 279 cr0.pg = 0; 280 tc->setMiscReg(MISCREG_CR0, cr0); 281 //Turn on protected mode. 282 cr0.pe = 1; 283 tc->setMiscReg(MISCREG_CR0, cr0); 284 285 CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4); 286 //Turn on pae. 287 cr4.pae = 1; 288 tc->setMiscReg(MISCREG_CR4, cr4); 289 290 //Point to the page tables. 291 tc->setMiscReg(MISCREG_CR3, PageMapLevel4); 292 293 Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER); 294 //Enable long mode. 295 efer.lme = 1; 296 tc->setMiscReg(MISCREG_EFER, efer); 297 298 //Start using longmode segments. 299 installSegDesc(tc, SEGMENT_REG_CS, csDesc, true); 300 installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true); 301 installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true); 302 installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true); 303 installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true); 304 installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true); 305 306 //Activate long mode. 307 cr0.pg = 1; 308 tc->setMiscReg(MISCREG_CR0, cr0); 309 310 tc->pcState(tc->getSystemPtr()->kernelEntry); 311 312 // We should now be in long mode. Yay! 313 314 Addr ebdaPos = 0xF0000; 315 Addr fixed, table; 316 317 //Write out the SMBios/DMI table 318 writeOutSMBiosTable(ebdaPos, fixed, table); 319 ebdaPos += (fixed + table); 320 ebdaPos = roundUp(ebdaPos, 16); 321 322 //Write out the Intel MP Specification configuration table 323 writeOutMPTable(ebdaPos, fixed, table); 324 ebdaPos += (fixed + table); 325} 326 327void 328X86System::writeOutSMBiosTable(Addr header, 329 Addr &headerSize, Addr &structSize, Addr table) 330{ 331 // If the table location isn't specified, just put it after the header. 332 // The header size as of the 2.5 SMBios specification is 0x1F bytes 333 if (!table) 334 table = header + 0x1F; 335 smbiosTable->setTableAddr(table); 336 337 smbiosTable->writeOut(physProxy, header, headerSize, structSize); 338 339 // Do some bounds checking to make sure we at least didn't step on 340 // ourselves. 341 assert(header > table || header + headerSize <= table); 342 assert(table > header || table + structSize <= header); 343} 344 345void 346X86System::writeOutMPTable(Addr fp, 347 Addr &fpSize, Addr &tableSize, Addr table) 348{ 349 // If the table location isn't specified and it exists, just put 350 // it after the floating pointer. The fp size as of the 1.4 Intel MP 351 // specification is 0x10 bytes. 352 if (mpConfigTable) { 353 if (!table) 354 table = fp + 0x10; 355 mpFloatingPointer->setTableAddr(table); 356 } 357 358 fpSize = mpFloatingPointer->writeOut(physProxy, fp); 359 if (mpConfigTable) 360 tableSize = mpConfigTable->writeOut(physProxy, table); 361 else 362 tableSize = 0; 363 364 // Do some bounds checking to make sure we at least didn't step on 365 // ourselves and the fp structure was the size we thought it was. 366 assert(fp > table || fp + fpSize <= table); 367 assert(table > fp || table + tableSize <= fp); 368 assert(fpSize == 0x10); 369} 370 371 372X86System::~X86System() 373{ 374 delete smbiosTable; 375} 376 377X86System * 378X86SystemParams::create() 379{ 380 return new X86System(this); 381} 382