system.cc revision 6222
15132Sgblack@eecs.umich.edu/* 25132Sgblack@eecs.umich.edu * Copyright (c) 2007 The Hewlett-Packard Development Company 35132Sgblack@eecs.umich.edu * All rights reserved. 45132Sgblack@eecs.umich.edu * 55132Sgblack@eecs.umich.edu * Redistribution and use of this software in source and binary forms, 65132Sgblack@eecs.umich.edu * with or without modification, are permitted provided that the 75132Sgblack@eecs.umich.edu * following conditions are met: 85132Sgblack@eecs.umich.edu * 95132Sgblack@eecs.umich.edu * The software must be used only for Non-Commercial Use which means any 105132Sgblack@eecs.umich.edu * use which is NOT directed to receiving any direct monetary 115132Sgblack@eecs.umich.edu * compensation for, or commercial advantage from such use. Illustrative 125132Sgblack@eecs.umich.edu * examples of non-commercial use are academic research, personal study, 135132Sgblack@eecs.umich.edu * teaching, education and corporate research & development. 145132Sgblack@eecs.umich.edu * Illustrative examples of commercial use are distributing products for 155132Sgblack@eecs.umich.edu * commercial advantage and providing services using the software for 165132Sgblack@eecs.umich.edu * commercial advantage. 175132Sgblack@eecs.umich.edu * 185132Sgblack@eecs.umich.edu * If you wish to use this software or functionality therein that may be 195132Sgblack@eecs.umich.edu * covered by patents for commercial use, please contact: 205132Sgblack@eecs.umich.edu * Director of Intellectual Property Licensing 215132Sgblack@eecs.umich.edu * Office of Strategy and Technology 225132Sgblack@eecs.umich.edu * Hewlett-Packard Company 235132Sgblack@eecs.umich.edu * 1501 Page Mill Road 245132Sgblack@eecs.umich.edu * Palo Alto, California 94304 255132Sgblack@eecs.umich.edu * 265132Sgblack@eecs.umich.edu * Redistributions of source code must retain the above copyright notice, 275132Sgblack@eecs.umich.edu * this list of conditions and the following disclaimer. Redistributions 285132Sgblack@eecs.umich.edu * in binary form must reproduce the above copyright notice, this list of 295132Sgblack@eecs.umich.edu * conditions and the following disclaimer in the documentation and/or 305132Sgblack@eecs.umich.edu * other materials provided with the distribution. Neither the name of 315132Sgblack@eecs.umich.edu * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 325132Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 335132Sgblack@eecs.umich.edu * this software without specific prior written permission. No right of 345132Sgblack@eecs.umich.edu * sublicense is granted herewith. Derivatives of the software and 355132Sgblack@eecs.umich.edu * output created using the software may be prepared, but only for 365132Sgblack@eecs.umich.edu * Non-Commercial Uses. Derivatives of the software may be shared with 375132Sgblack@eecs.umich.edu * others provided: (i) the others agree to abide by the list of 385132Sgblack@eecs.umich.edu * conditions herein which includes the Non-Commercial Use restrictions; 395132Sgblack@eecs.umich.edu * and (ii) such Derivatives of the software include the above copyright 405132Sgblack@eecs.umich.edu * notice to acknowledge the contribution from this software where 415132Sgblack@eecs.umich.edu * applicable, this list of conditions and the disclaimer below. 425132Sgblack@eecs.umich.edu * 435132Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 445132Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 455132Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 465132Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 475132Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 485132Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 495132Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 505132Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 515132Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 525132Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 535132Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 545132Sgblack@eecs.umich.edu * 555132Sgblack@eecs.umich.edu * Authors: Gabe Black 565132Sgblack@eecs.umich.edu */ 575132Sgblack@eecs.umich.edu 585612Sgblack@eecs.umich.edu#include "arch/x86/bios/smbios.hh" 595625Sgblack@eecs.umich.edu#include "arch/x86/bios/intelmp.hh" 605299Sgblack@eecs.umich.edu#include "arch/x86/miscregs.hh" 615132Sgblack@eecs.umich.edu#include "arch/x86/system.hh" 625132Sgblack@eecs.umich.edu#include "arch/vtophys.hh" 635625Sgblack@eecs.umich.edu#include "base/intmath.hh" 645132Sgblack@eecs.umich.edu#include "base/loader/object_file.hh" 655132Sgblack@eecs.umich.edu#include "base/loader/symtab.hh" 665625Sgblack@eecs.umich.edu#include "base/remote_gdb.hh" 675132Sgblack@eecs.umich.edu#include "base/trace.hh" 685299Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 695132Sgblack@eecs.umich.edu#include "mem/physical.hh" 705132Sgblack@eecs.umich.edu#include "params/X86System.hh" 715132Sgblack@eecs.umich.edu#include "sim/byteswap.hh" 725132Sgblack@eecs.umich.edu 735132Sgblack@eecs.umich.edu 745299Sgblack@eecs.umich.eduusing namespace LittleEndianGuest; 755299Sgblack@eecs.umich.eduusing namespace X86ISA; 765132Sgblack@eecs.umich.edu 775625Sgblack@eecs.umich.eduX86System::X86System(Params *p) : 785625Sgblack@eecs.umich.edu System(p), smbiosTable(p->smbios_table), 795625Sgblack@eecs.umich.edu mpFloatingPointer(p->intel_mp_pointer), 805627Sgblack@eecs.umich.edu mpConfigTable(p->intel_mp_table), 815627Sgblack@eecs.umich.edu rsdp(p->acpi_description_table_pointer) 825615Sgblack@eecs.umich.edu{} 835132Sgblack@eecs.umich.edu 846220Sgblack@eecs.umich.edustatic void 856220Sgblack@eecs.umich.eduinstallSegDesc(ThreadContext *tc, SegmentRegIndex seg, 866220Sgblack@eecs.umich.edu SegDescriptor desc, bool longmode) 876220Sgblack@eecs.umich.edu{ 886220Sgblack@eecs.umich.edu uint64_t base = desc.baseLow + (desc.baseHigh << 24); 896220Sgblack@eecs.umich.edu bool honorBase = !longmode || seg == SEGMENT_REG_FS || 906220Sgblack@eecs.umich.edu seg == SEGMENT_REG_GS || 916220Sgblack@eecs.umich.edu seg == SEGMENT_REG_TSL || 926220Sgblack@eecs.umich.edu seg == SYS_SEGMENT_REG_TR; 936220Sgblack@eecs.umich.edu uint64_t limit = desc.limitLow | (desc.limitHigh << 16); 946220Sgblack@eecs.umich.edu 956220Sgblack@eecs.umich.edu SegAttr attr = 0; 966222Sgblack@eecs.umich.edu 976222Sgblack@eecs.umich.edu attr.dpl = desc.dpl; 986222Sgblack@eecs.umich.edu attr.unusable = 0; 996222Sgblack@eecs.umich.edu attr.defaultSize = desc.d; 1006222Sgblack@eecs.umich.edu attr.longMode = desc.l; 1016222Sgblack@eecs.umich.edu attr.avl = desc.avl; 1026222Sgblack@eecs.umich.edu attr.granularity = desc.g; 1036222Sgblack@eecs.umich.edu attr.present = desc.p; 1046222Sgblack@eecs.umich.edu attr.system = desc.s; 1056222Sgblack@eecs.umich.edu attr.type = desc.type; 1066220Sgblack@eecs.umich.edu if (desc.s) { 1076220Sgblack@eecs.umich.edu if (desc.type.codeOrData) { 1086220Sgblack@eecs.umich.edu // Code segment 1096222Sgblack@eecs.umich.edu attr.expandDown = 0; 1106220Sgblack@eecs.umich.edu attr.readable = desc.type.r; 1116222Sgblack@eecs.umich.edu attr.writable = 0; 1126220Sgblack@eecs.umich.edu } else { 1136220Sgblack@eecs.umich.edu // Data segment 1146222Sgblack@eecs.umich.edu attr.expandDown = desc.type.e; 1156220Sgblack@eecs.umich.edu attr.readable = 1; 1166220Sgblack@eecs.umich.edu attr.writable = desc.type.w; 1176220Sgblack@eecs.umich.edu } 1186220Sgblack@eecs.umich.edu } else { 1196222Sgblack@eecs.umich.edu attr.readable = 1; 1206220Sgblack@eecs.umich.edu attr.writable = 1; 1216220Sgblack@eecs.umich.edu attr.expandDown = 0; 1226220Sgblack@eecs.umich.edu } 1236220Sgblack@eecs.umich.edu 1246220Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SEG_BASE(seg), base); 1256220Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), honorBase ? base : 0); 1266220Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SEG_LIMIT(seg), limit); 1276220Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SEG_ATTR(seg), (MiscReg)attr); 1286220Sgblack@eecs.umich.edu} 1296220Sgblack@eecs.umich.edu 1305299Sgblack@eecs.umich.eduvoid 1315299Sgblack@eecs.umich.eduX86System::startup() 1325299Sgblack@eecs.umich.edu{ 1335299Sgblack@eecs.umich.edu System::startup(); 1346220Sgblack@eecs.umich.edu ThreadContext *tc = threadContexts[0]; 1355299Sgblack@eecs.umich.edu // This is the boot strap processor (BSP). Initialize it to look like 1365299Sgblack@eecs.umich.edu // the boot loader has just turned control over to the 64 bit OS. We 1375299Sgblack@eecs.umich.edu // won't actually set up real mode or legacy protected mode descriptor 1385299Sgblack@eecs.umich.edu // tables because we aren't executing any code that would require 1395299Sgblack@eecs.umich.edu // them. We do, however toggle the control bits in the correct order 1405299Sgblack@eecs.umich.edu // while allowing consistency checks and the underlying mechansims 1415299Sgblack@eecs.umich.edu // just to be safe. 1425299Sgblack@eecs.umich.edu 1435299Sgblack@eecs.umich.edu const int NumPDTs = 4; 1445299Sgblack@eecs.umich.edu 1455299Sgblack@eecs.umich.edu const Addr PageMapLevel4 = 0x70000; 1465299Sgblack@eecs.umich.edu const Addr PageDirPtrTable = 0x71000; 1475299Sgblack@eecs.umich.edu const Addr PageDirTable[NumPDTs] = 1485299Sgblack@eecs.umich.edu {0x72000, 0x73000, 0x74000, 0x75000}; 1495299Sgblack@eecs.umich.edu const Addr GDTBase = 0x76000; 1505299Sgblack@eecs.umich.edu 1515299Sgblack@eecs.umich.edu const int PML4Bits = 9; 1525299Sgblack@eecs.umich.edu const int PDPTBits = 9; 1535299Sgblack@eecs.umich.edu const int PDTBits = 9; 1545299Sgblack@eecs.umich.edu 1555299Sgblack@eecs.umich.edu // Get a port to write the page tables and descriptor tables. 1566220Sgblack@eecs.umich.edu FunctionalPort * physPort = tc->getPhysPort(); 1575299Sgblack@eecs.umich.edu 1585299Sgblack@eecs.umich.edu /* 1595299Sgblack@eecs.umich.edu * Set up the gdt. 1605299Sgblack@eecs.umich.edu */ 1616220Sgblack@eecs.umich.edu uint8_t numGDTEntries = 0; 1625299Sgblack@eecs.umich.edu // Place holder at selector 0 1635299Sgblack@eecs.umich.edu uint64_t nullDescriptor = 0; 1646220Sgblack@eecs.umich.edu physPort->writeBlob(GDTBase + numGDTEntries * 8, 1656220Sgblack@eecs.umich.edu (uint8_t *)(&nullDescriptor), 8); 1666220Sgblack@eecs.umich.edu numGDTEntries++; 1675299Sgblack@eecs.umich.edu 1685299Sgblack@eecs.umich.edu //64 bit code segment 1695299Sgblack@eecs.umich.edu SegDescriptor csDesc = 0; 1706220Sgblack@eecs.umich.edu csDesc.type.codeOrData = 1; 1715299Sgblack@eecs.umich.edu csDesc.type.c = 0; // Not conforming 1726220Sgblack@eecs.umich.edu csDesc.type.r = 1; // Readable 1735299Sgblack@eecs.umich.edu csDesc.dpl = 0; // Privelege level 0 1745299Sgblack@eecs.umich.edu csDesc.p = 1; // Present 1755299Sgblack@eecs.umich.edu csDesc.l = 1; // 64 bit 1765299Sgblack@eecs.umich.edu csDesc.d = 0; // default operand size 1776220Sgblack@eecs.umich.edu csDesc.g = 1; // Page granularity 1786220Sgblack@eecs.umich.edu csDesc.s = 1; // Not a system segment 1796220Sgblack@eecs.umich.edu csDesc.limitHigh = 0xF; 1806220Sgblack@eecs.umich.edu csDesc.limitLow = 0xFF; 1815299Sgblack@eecs.umich.edu //Because we're dealing with a pointer and I don't think it's 1825299Sgblack@eecs.umich.edu //guaranteed that there isn't anything in a nonvirtual class between 1835299Sgblack@eecs.umich.edu //it's beginning in memory and it's actual data, we'll use an 1845299Sgblack@eecs.umich.edu //intermediary. 1855299Sgblack@eecs.umich.edu uint64_t csDescVal = csDesc; 1866220Sgblack@eecs.umich.edu physPort->writeBlob(GDTBase + numGDTEntries * 8, 1876220Sgblack@eecs.umich.edu (uint8_t *)(&csDescVal), 8); 1885299Sgblack@eecs.umich.edu 1896220Sgblack@eecs.umich.edu numGDTEntries++; 1906220Sgblack@eecs.umich.edu 1916220Sgblack@eecs.umich.edu SegSelector cs = 0; 1926220Sgblack@eecs.umich.edu cs.si = numGDTEntries - 1; 1936220Sgblack@eecs.umich.edu 1946220Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CS, (MiscReg)cs); 1956220Sgblack@eecs.umich.edu 1966220Sgblack@eecs.umich.edu //32 bit data segment 1976220Sgblack@eecs.umich.edu SegDescriptor dsDesc = 0; 1986220Sgblack@eecs.umich.edu dsDesc.type.codeOrData = 0; 1996220Sgblack@eecs.umich.edu dsDesc.type.e = 0; // Not expand down 2006220Sgblack@eecs.umich.edu dsDesc.type.w = 1; // Writable 2016220Sgblack@eecs.umich.edu dsDesc.dpl = 0; // Privelege level 0 2026220Sgblack@eecs.umich.edu dsDesc.p = 1; // Present 2036220Sgblack@eecs.umich.edu dsDesc.d = 1; // default operand size 2046220Sgblack@eecs.umich.edu dsDesc.g = 1; // Page granularity 2056220Sgblack@eecs.umich.edu dsDesc.s = 1; // Not a system segment 2066220Sgblack@eecs.umich.edu dsDesc.limitHigh = 0xF; 2076220Sgblack@eecs.umich.edu dsDesc.limitLow = 0xFF; 2086220Sgblack@eecs.umich.edu uint64_t dsDescVal = dsDesc; 2096220Sgblack@eecs.umich.edu physPort->writeBlob(GDTBase + numGDTEntries * 8, 2106220Sgblack@eecs.umich.edu (uint8_t *)(&dsDescVal), 8); 2116220Sgblack@eecs.umich.edu 2126220Sgblack@eecs.umich.edu numGDTEntries++; 2136220Sgblack@eecs.umich.edu 2146220Sgblack@eecs.umich.edu SegSelector ds; 2156220Sgblack@eecs.umich.edu ds.si = numGDTEntries - 1; 2166220Sgblack@eecs.umich.edu 2176220Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_DS, (MiscReg)ds); 2186220Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_ES, (MiscReg)ds); 2196220Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_FS, (MiscReg)ds); 2206220Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_GS, (MiscReg)ds); 2216220Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SS, (MiscReg)ds); 2226220Sgblack@eecs.umich.edu 2236220Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TSL, 0); 2246220Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TSG_BASE, GDTBase); 2256220Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1); 2266220Sgblack@eecs.umich.edu 2276220Sgblack@eecs.umich.edu SegDescriptor tssDesc = 0; 2286220Sgblack@eecs.umich.edu tssDesc.type = 0xB; 2296220Sgblack@eecs.umich.edu tssDesc.dpl = 0; // Privelege level 0 2306220Sgblack@eecs.umich.edu tssDesc.p = 1; // Present 2316220Sgblack@eecs.umich.edu tssDesc.d = 1; // default operand size 2326220Sgblack@eecs.umich.edu tssDesc.g = 1; // Page granularity 2336220Sgblack@eecs.umich.edu tssDesc.s = 1; // Not a system segment 2346220Sgblack@eecs.umich.edu tssDesc.limitHigh = 0xF; 2356220Sgblack@eecs.umich.edu tssDesc.limitLow = 0xFF; 2366220Sgblack@eecs.umich.edu uint64_t tssDescVal = tssDesc; 2376220Sgblack@eecs.umich.edu physPort->writeBlob(GDTBase + numGDTEntries * 8, 2386220Sgblack@eecs.umich.edu (uint8_t *)(&tssDescVal), 8); 2396220Sgblack@eecs.umich.edu 2406220Sgblack@eecs.umich.edu numGDTEntries++; 2416220Sgblack@eecs.umich.edu 2426220Sgblack@eecs.umich.edu SegSelector tss = 0; 2436220Sgblack@eecs.umich.edu tss.si = numGDTEntries - 1; 2446220Sgblack@eecs.umich.edu 2456220Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_TR, (MiscReg)tss); 2466220Sgblack@eecs.umich.edu installSegDesc(tc, SYS_SEGMENT_REG_TR, tssDesc, true); 2475299Sgblack@eecs.umich.edu 2485299Sgblack@eecs.umich.edu /* 2495299Sgblack@eecs.umich.edu * Identity map the first 4GB of memory. In order to map this region 2505299Sgblack@eecs.umich.edu * of memory in long mode, there needs to be one actual page map level 2515299Sgblack@eecs.umich.edu * 4 entry which points to one page directory pointer table which 2525299Sgblack@eecs.umich.edu * points to 4 different page directory tables which are full of two 2535299Sgblack@eecs.umich.edu * megabyte pages. All of the other entries in valid tables are set 2545299Sgblack@eecs.umich.edu * to indicate that they don't pertain to anything valid and will 2555299Sgblack@eecs.umich.edu * cause a fault if used. 2565299Sgblack@eecs.umich.edu */ 2575299Sgblack@eecs.umich.edu 2585299Sgblack@eecs.umich.edu // Put valid values in all of the various table entries which indicate 2595299Sgblack@eecs.umich.edu // that those entries don't point to further tables or pages. Then 2605299Sgblack@eecs.umich.edu // set the values of those entries which are needed. 2615299Sgblack@eecs.umich.edu 2625299Sgblack@eecs.umich.edu // Page Map Level 4 2635299Sgblack@eecs.umich.edu 2645299Sgblack@eecs.umich.edu // read/write, user, not present 2655299Sgblack@eecs.umich.edu uint64_t pml4e = X86ISA::htog(0x6); 2665299Sgblack@eecs.umich.edu for (int offset = 0; offset < (1 << PML4Bits) * 8; offset += 8) { 2675299Sgblack@eecs.umich.edu physPort->writeBlob(PageMapLevel4 + offset, (uint8_t *)(&pml4e), 8); 2685299Sgblack@eecs.umich.edu } 2695299Sgblack@eecs.umich.edu // Point to the only PDPT 2705299Sgblack@eecs.umich.edu pml4e = X86ISA::htog(0x7 | PageDirPtrTable); 2715299Sgblack@eecs.umich.edu physPort->writeBlob(PageMapLevel4, (uint8_t *)(&pml4e), 8); 2725299Sgblack@eecs.umich.edu 2735299Sgblack@eecs.umich.edu // Page Directory Pointer Table 2745299Sgblack@eecs.umich.edu 2755299Sgblack@eecs.umich.edu // read/write, user, not present 2765299Sgblack@eecs.umich.edu uint64_t pdpe = X86ISA::htog(0x6); 2775299Sgblack@eecs.umich.edu for (int offset = 0; offset < (1 << PDPTBits) * 8; offset += 8) { 2785299Sgblack@eecs.umich.edu physPort->writeBlob(PageDirPtrTable + offset, 2795299Sgblack@eecs.umich.edu (uint8_t *)(&pdpe), 8); 2805299Sgblack@eecs.umich.edu } 2815299Sgblack@eecs.umich.edu // Point to the PDTs 2825299Sgblack@eecs.umich.edu for (int table = 0; table < NumPDTs; table++) { 2835299Sgblack@eecs.umich.edu pdpe = X86ISA::htog(0x7 | PageDirTable[table]); 2845299Sgblack@eecs.umich.edu physPort->writeBlob(PageDirPtrTable + table * 8, 2855299Sgblack@eecs.umich.edu (uint8_t *)(&pdpe), 8); 2865299Sgblack@eecs.umich.edu } 2875299Sgblack@eecs.umich.edu 2885299Sgblack@eecs.umich.edu // Page Directory Tables 2895299Sgblack@eecs.umich.edu 2905299Sgblack@eecs.umich.edu Addr base = 0; 2915299Sgblack@eecs.umich.edu const Addr pageSize = 2 << 20; 2925299Sgblack@eecs.umich.edu for (int table = 0; table < NumPDTs; table++) { 2935299Sgblack@eecs.umich.edu for (int offset = 0; offset < (1 << PDTBits) * 8; offset += 8) { 2945299Sgblack@eecs.umich.edu // read/write, user, present, 4MB 2955299Sgblack@eecs.umich.edu uint64_t pdte = X86ISA::htog(0x87 | base); 2965299Sgblack@eecs.umich.edu physPort->writeBlob(PageDirTable[table] + offset, 2975299Sgblack@eecs.umich.edu (uint8_t *)(&pdte), 8); 2985299Sgblack@eecs.umich.edu base += pageSize; 2995299Sgblack@eecs.umich.edu } 3005299Sgblack@eecs.umich.edu } 3015299Sgblack@eecs.umich.edu 3025299Sgblack@eecs.umich.edu /* 3035299Sgblack@eecs.umich.edu * Transition from real mode all the way up to Long mode 3045299Sgblack@eecs.umich.edu */ 3056220Sgblack@eecs.umich.edu CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); 3065299Sgblack@eecs.umich.edu //Turn off paging. 3075299Sgblack@eecs.umich.edu cr0.pg = 0; 3086220Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR0, cr0); 3095299Sgblack@eecs.umich.edu //Turn on protected mode. 3105299Sgblack@eecs.umich.edu cr0.pe = 1; 3116220Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR0, cr0); 3125299Sgblack@eecs.umich.edu 3136220Sgblack@eecs.umich.edu CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4); 3145299Sgblack@eecs.umich.edu //Turn on pae. 3155299Sgblack@eecs.umich.edu cr4.pae = 1; 3166220Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR4, cr4); 3175299Sgblack@eecs.umich.edu 3185299Sgblack@eecs.umich.edu //Point to the page tables. 3196220Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR3, PageMapLevel4); 3205299Sgblack@eecs.umich.edu 3216220Sgblack@eecs.umich.edu Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER); 3225299Sgblack@eecs.umich.edu //Enable long mode. 3235299Sgblack@eecs.umich.edu efer.lme = 1; 3246220Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_EFER, efer); 3256220Sgblack@eecs.umich.edu 3266220Sgblack@eecs.umich.edu //Start using longmode segments. 3276220Sgblack@eecs.umich.edu installSegDesc(tc, SEGMENT_REG_CS, csDesc, true); 3286220Sgblack@eecs.umich.edu installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true); 3296220Sgblack@eecs.umich.edu installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true); 3306220Sgblack@eecs.umich.edu installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true); 3316220Sgblack@eecs.umich.edu installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true); 3326220Sgblack@eecs.umich.edu installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true); 3335299Sgblack@eecs.umich.edu 3345299Sgblack@eecs.umich.edu //Activate long mode. 3355299Sgblack@eecs.umich.edu cr0.pg = 1; 3366220Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR0, cr0); 3375299Sgblack@eecs.umich.edu 3386220Sgblack@eecs.umich.edu tc->setPC(tc->getSystemPtr()->kernelEntry); 3396220Sgblack@eecs.umich.edu tc->setNextPC(tc->readPC()); 3405299Sgblack@eecs.umich.edu 3415299Sgblack@eecs.umich.edu // We should now be in long mode. Yay! 3425334Sgblack@eecs.umich.edu 3435615Sgblack@eecs.umich.edu Addr ebdaPos = 0xF0000; 3445625Sgblack@eecs.umich.edu Addr fixed, table; 3455615Sgblack@eecs.umich.edu 3465334Sgblack@eecs.umich.edu //Write out the SMBios/DMI table 3475625Sgblack@eecs.umich.edu writeOutSMBiosTable(ebdaPos, fixed, table); 3485625Sgblack@eecs.umich.edu ebdaPos += (fixed + table); 3495625Sgblack@eecs.umich.edu ebdaPos = roundUp(ebdaPos, 16); 3505625Sgblack@eecs.umich.edu 3515625Sgblack@eecs.umich.edu //Write out the Intel MP Specification configuration table 3525625Sgblack@eecs.umich.edu writeOutMPTable(ebdaPos, fixed, table); 3535625Sgblack@eecs.umich.edu ebdaPos += (fixed + table); 3545299Sgblack@eecs.umich.edu} 3555299Sgblack@eecs.umich.edu 3565334Sgblack@eecs.umich.eduvoid 3575615Sgblack@eecs.umich.eduX86System::writeOutSMBiosTable(Addr header, 3585615Sgblack@eecs.umich.edu Addr &headerSize, Addr &structSize, Addr table) 3595334Sgblack@eecs.umich.edu{ 3605334Sgblack@eecs.umich.edu // Get a port to write the table and header to memory. 3615334Sgblack@eecs.umich.edu FunctionalPort * physPort = threadContexts[0]->getPhysPort(); 3625334Sgblack@eecs.umich.edu 3635334Sgblack@eecs.umich.edu // If the table location isn't specified, just put it after the header. 3645334Sgblack@eecs.umich.edu // The header size as of the 2.5 SMBios specification is 0x1F bytes 3655615Sgblack@eecs.umich.edu if (!table) 3665615Sgblack@eecs.umich.edu table = header + 0x1F; 3675615Sgblack@eecs.umich.edu smbiosTable->setTableAddr(table); 3685334Sgblack@eecs.umich.edu 3695615Sgblack@eecs.umich.edu smbiosTable->writeOut(physPort, header, headerSize, structSize); 3705615Sgblack@eecs.umich.edu 3715615Sgblack@eecs.umich.edu // Do some bounds checking to make sure we at least didn't step on 3725615Sgblack@eecs.umich.edu // ourselves. 3735615Sgblack@eecs.umich.edu assert(header > table || header + headerSize <= table); 3745615Sgblack@eecs.umich.edu assert(table > header || table + structSize <= header); 3755334Sgblack@eecs.umich.edu} 3765334Sgblack@eecs.umich.edu 3775625Sgblack@eecs.umich.eduvoid 3785625Sgblack@eecs.umich.eduX86System::writeOutMPTable(Addr fp, 3795625Sgblack@eecs.umich.edu Addr &fpSize, Addr &tableSize, Addr table) 3805625Sgblack@eecs.umich.edu{ 3815625Sgblack@eecs.umich.edu // Get a port to write the table and header to memory. 3825625Sgblack@eecs.umich.edu FunctionalPort * physPort = threadContexts[0]->getPhysPort(); 3835625Sgblack@eecs.umich.edu 3845625Sgblack@eecs.umich.edu // If the table location isn't specified and it exists, just put 3855625Sgblack@eecs.umich.edu // it after the floating pointer. The fp size as of the 1.4 Intel MP 3865625Sgblack@eecs.umich.edu // specification is 0x10 bytes. 3875625Sgblack@eecs.umich.edu if (mpConfigTable) { 3885625Sgblack@eecs.umich.edu if (!table) 3895625Sgblack@eecs.umich.edu table = fp + 0x10; 3905625Sgblack@eecs.umich.edu mpFloatingPointer->setTableAddr(table); 3915625Sgblack@eecs.umich.edu } 3925625Sgblack@eecs.umich.edu 3935625Sgblack@eecs.umich.edu fpSize = mpFloatingPointer->writeOut(physPort, fp); 3945625Sgblack@eecs.umich.edu if (mpConfigTable) 3955625Sgblack@eecs.umich.edu tableSize = mpConfigTable->writeOut(physPort, table); 3965625Sgblack@eecs.umich.edu else 3975625Sgblack@eecs.umich.edu tableSize = 0; 3985625Sgblack@eecs.umich.edu 3995625Sgblack@eecs.umich.edu // Do some bounds checking to make sure we at least didn't step on 4005625Sgblack@eecs.umich.edu // ourselves and the fp structure was the size we thought it was. 4015625Sgblack@eecs.umich.edu assert(fp > table || fp + fpSize <= table); 4025625Sgblack@eecs.umich.edu assert(table > fp || table + tableSize <= fp); 4035625Sgblack@eecs.umich.edu assert(fpSize == 0x10); 4045625Sgblack@eecs.umich.edu} 4055625Sgblack@eecs.umich.edu 4065334Sgblack@eecs.umich.edu 4075132Sgblack@eecs.umich.eduX86System::~X86System() 4085132Sgblack@eecs.umich.edu{ 4095334Sgblack@eecs.umich.edu delete smbiosTable; 4105132Sgblack@eecs.umich.edu} 4115132Sgblack@eecs.umich.edu 4125132Sgblack@eecs.umich.eduvoid 4135132Sgblack@eecs.umich.eduX86System::serialize(std::ostream &os) 4145132Sgblack@eecs.umich.edu{ 4155132Sgblack@eecs.umich.edu System::serialize(os); 4165132Sgblack@eecs.umich.edu} 4175132Sgblack@eecs.umich.edu 4185132Sgblack@eecs.umich.edu 4195132Sgblack@eecs.umich.eduvoid 4205132Sgblack@eecs.umich.eduX86System::unserialize(Checkpoint *cp, const std::string §ion) 4215132Sgblack@eecs.umich.edu{ 4225132Sgblack@eecs.umich.edu System::unserialize(cp,section); 4235132Sgblack@eecs.umich.edu} 4245132Sgblack@eecs.umich.edu 4255132Sgblack@eecs.umich.eduX86System * 4265132Sgblack@eecs.umich.eduX86SystemParams::create() 4275132Sgblack@eecs.umich.edu{ 4285132Sgblack@eecs.umich.edu return new X86System(this); 4295132Sgblack@eecs.umich.edu} 430