misc.hh revision 9211:46c3a74952ec
1/* 2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 */ 39 40#ifndef __ARCH_X86_MISCREGS_HH__ 41#define __ARCH_X86_MISCREGS_HH__ 42 43#include "arch/x86/regs/segment.hh" 44#include "arch/x86/x86_traits.hh" 45#include "base/bitunion.hh" 46 47//These get defined in some system headers (at least termbits.h). That confuses 48//things here significantly. 49#undef CR0 50#undef CR2 51#undef CR3 52 53namespace X86ISA 54{ 55 enum CondFlagBit { 56 CFBit = 1 << 0, 57 PFBit = 1 << 2, 58 ECFBit = 1 << 3, 59 AFBit = 1 << 4, 60 EZFBit = 1 << 5, 61 ZFBit = 1 << 6, 62 SFBit = 1 << 7, 63 DFBit = 1 << 10, 64 OFBit = 1 << 11 65 }; 66 67 const uint32_t cfofMask = CFBit | OFBit; 68 const uint32_t ccFlagMask = PFBit | AFBit | ZFBit | SFBit; 69 70 enum RFLAGBit { 71 TFBit = 1 << 8, 72 IFBit = 1 << 9, 73 NTBit = 1 << 14, 74 RFBit = 1 << 16, 75 VMBit = 1 << 17, 76 ACBit = 1 << 18, 77 VIFBit = 1 << 19, 78 VIPBit = 1 << 20, 79 IDBit = 1 << 21 80 }; 81 82 enum MiscRegIndex 83 { 84 // Control registers 85 // Most of these are invalid. 86 MISCREG_CR_BASE, 87 MISCREG_CR0 = MISCREG_CR_BASE, 88 MISCREG_CR1, 89 MISCREG_CR2, 90 MISCREG_CR3, 91 MISCREG_CR4, 92 MISCREG_CR5, 93 MISCREG_CR6, 94 MISCREG_CR7, 95 MISCREG_CR8, 96 MISCREG_CR9, 97 MISCREG_CR10, 98 MISCREG_CR11, 99 MISCREG_CR12, 100 MISCREG_CR13, 101 MISCREG_CR14, 102 MISCREG_CR15, 103 104 // Debug registers 105 MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs, 106 MISCREG_DR0 = MISCREG_DR_BASE, 107 MISCREG_DR1, 108 MISCREG_DR2, 109 MISCREG_DR3, 110 MISCREG_DR4, 111 MISCREG_DR5, 112 MISCREG_DR6, 113 MISCREG_DR7, 114 115 // Flags register 116 MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs, 117 118 //Register to keep handy values like the CPU mode in. 119 MISCREG_M5_REG, 120 121 /* 122 * Model Specific Registers 123 */ 124 // Time stamp counter 125 MISCREG_TSC, 126 127 MISCREG_MTRRCAP, 128 129 MISCREG_SYSENTER_CS, 130 MISCREG_SYSENTER_ESP, 131 MISCREG_SYSENTER_EIP, 132 133 MISCREG_MCG_CAP, 134 MISCREG_MCG_STATUS, 135 MISCREG_MCG_CTL, 136 137 MISCREG_DEBUG_CTL_MSR, 138 139 MISCREG_LAST_BRANCH_FROM_IP, 140 MISCREG_LAST_BRANCH_TO_IP, 141 MISCREG_LAST_EXCEPTION_FROM_IP, 142 MISCREG_LAST_EXCEPTION_TO_IP, 143 144 MISCREG_MTRR_PHYS_BASE_BASE, 145 MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE, 146 MISCREG_MTRR_PHYS_BASE_1, 147 MISCREG_MTRR_PHYS_BASE_2, 148 MISCREG_MTRR_PHYS_BASE_3, 149 MISCREG_MTRR_PHYS_BASE_4, 150 MISCREG_MTRR_PHYS_BASE_5, 151 MISCREG_MTRR_PHYS_BASE_6, 152 MISCREG_MTRR_PHYS_BASE_7, 153 MISCREG_MTRR_PHYS_BASE_END, 154 155 MISCREG_MTRR_PHYS_MASK_BASE = MISCREG_MTRR_PHYS_BASE_END, 156 MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE, 157 MISCREG_MTRR_PHYS_MASK_1, 158 MISCREG_MTRR_PHYS_MASK_2, 159 MISCREG_MTRR_PHYS_MASK_3, 160 MISCREG_MTRR_PHYS_MASK_4, 161 MISCREG_MTRR_PHYS_MASK_5, 162 MISCREG_MTRR_PHYS_MASK_6, 163 MISCREG_MTRR_PHYS_MASK_7, 164 MISCREG_MTRR_PHYS_MASK_END, 165 166 MISCREG_MTRR_FIX_64K_00000 = MISCREG_MTRR_PHYS_MASK_END, 167 MISCREG_MTRR_FIX_16K_80000, 168 MISCREG_MTRR_FIX_16K_A0000, 169 MISCREG_MTRR_FIX_4K_C0000, 170 MISCREG_MTRR_FIX_4K_C8000, 171 MISCREG_MTRR_FIX_4K_D0000, 172 MISCREG_MTRR_FIX_4K_D8000, 173 MISCREG_MTRR_FIX_4K_E0000, 174 MISCREG_MTRR_FIX_4K_E8000, 175 MISCREG_MTRR_FIX_4K_F0000, 176 MISCREG_MTRR_FIX_4K_F8000, 177 178 MISCREG_PAT, 179 180 MISCREG_DEF_TYPE, 181 182 MISCREG_MC_CTL_BASE, 183 MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE, 184 MISCREG_MC1_CTL, 185 MISCREG_MC2_CTL, 186 MISCREG_MC3_CTL, 187 MISCREG_MC4_CTL, 188 MISCREG_MC5_CTL, 189 MISCREG_MC6_CTL, 190 MISCREG_MC7_CTL, 191 MISCREG_MC_CTL_END, 192 193 MISCREG_MC_STATUS_BASE = MISCREG_MC_CTL_END, 194 MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE, 195 MISCREG_MC1_STATUS, 196 MISCREG_MC2_STATUS, 197 MISCREG_MC3_STATUS, 198 MISCREG_MC4_STATUS, 199 MISCREG_MC5_STATUS, 200 MISCREG_MC6_STATUS, 201 MISCREG_MC7_STATUS, 202 MISCREG_MC_STATUS_END, 203 204 MISCREG_MC_ADDR_BASE = MISCREG_MC_STATUS_END, 205 MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE, 206 MISCREG_MC1_ADDR, 207 MISCREG_MC2_ADDR, 208 MISCREG_MC3_ADDR, 209 MISCREG_MC4_ADDR, 210 MISCREG_MC5_ADDR, 211 MISCREG_MC6_ADDR, 212 MISCREG_MC7_ADDR, 213 MISCREG_MC_ADDR_END, 214 215 MISCREG_MC_MISC_BASE = MISCREG_MC_ADDR_END, 216 MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE, 217 MISCREG_MC1_MISC, 218 MISCREG_MC2_MISC, 219 MISCREG_MC3_MISC, 220 MISCREG_MC4_MISC, 221 MISCREG_MC5_MISC, 222 MISCREG_MC6_MISC, 223 MISCREG_MC7_MISC, 224 MISCREG_MC_MISC_END, 225 226 // Extended feature enable register 227 MISCREG_EFER = MISCREG_MC_MISC_END, 228 229 MISCREG_STAR, 230 MISCREG_LSTAR, 231 MISCREG_CSTAR, 232 233 MISCREG_SF_MASK, 234 235 MISCREG_KERNEL_GS_BASE, 236 237 MISCREG_TSC_AUX, 238 239 MISCREG_PERF_EVT_SEL_BASE, 240 MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE, 241 MISCREG_PERF_EVT_SEL1, 242 MISCREG_PERF_EVT_SEL2, 243 MISCREG_PERF_EVT_SEL3, 244 MISCREG_PERF_EVT_SEL_END, 245 246 MISCREG_PERF_EVT_CTR_BASE = MISCREG_PERF_EVT_SEL_END, 247 MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE, 248 MISCREG_PERF_EVT_CTR1, 249 MISCREG_PERF_EVT_CTR2, 250 MISCREG_PERF_EVT_CTR3, 251 MISCREG_PERF_EVT_CTR_END, 252 253 MISCREG_SYSCFG = MISCREG_PERF_EVT_CTR_END, 254 255 MISCREG_IORR_BASE_BASE, 256 MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE, 257 MISCREG_IORR_BASE1, 258 MISCREG_IORR_BASE_END, 259 260 MISCREG_IORR_MASK_BASE = MISCREG_IORR_BASE_END, 261 MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE, 262 MISCREG_IORR_MASK1, 263 MISCREG_IORR_MASK_END, 264 265 MISCREG_TOP_MEM = MISCREG_IORR_MASK_END, 266 MISCREG_TOP_MEM2, 267 268 MISCREG_VM_CR, 269 MISCREG_IGNNE, 270 MISCREG_SMM_CTL, 271 MISCREG_VM_HSAVE_PA, 272 273 /* 274 * Segment registers 275 */ 276 // Segment selectors 277 MISCREG_SEG_SEL_BASE, 278 MISCREG_ES = MISCREG_SEG_SEL_BASE, 279 MISCREG_CS, 280 MISCREG_SS, 281 MISCREG_DS, 282 MISCREG_FS, 283 MISCREG_GS, 284 MISCREG_HS, 285 MISCREG_TSL, 286 MISCREG_TSG, 287 MISCREG_LS, 288 MISCREG_MS, 289 MISCREG_TR, 290 MISCREG_IDTR, 291 292 // Hidden segment base field 293 MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS, 294 MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE, 295 MISCREG_CS_BASE, 296 MISCREG_SS_BASE, 297 MISCREG_DS_BASE, 298 MISCREG_FS_BASE, 299 MISCREG_GS_BASE, 300 MISCREG_HS_BASE, 301 MISCREG_TSL_BASE, 302 MISCREG_TSG_BASE, 303 MISCREG_LS_BASE, 304 MISCREG_MS_BASE, 305 MISCREG_TR_BASE, 306 MISCREG_IDTR_BASE, 307 308 // The effective segment base, ie what is actually added to an 309 // address. In 64 bit mode this can be different from the above, 310 // namely 0. 311 MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS, 312 MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE, 313 MISCREG_CS_EFF_BASE, 314 MISCREG_SS_EFF_BASE, 315 MISCREG_DS_EFF_BASE, 316 MISCREG_FS_EFF_BASE, 317 MISCREG_GS_EFF_BASE, 318 MISCREG_HS_EFF_BASE, 319 MISCREG_TSL_EFF_BASE, 320 MISCREG_TSG_EFF_BASE, 321 MISCREG_LS_EFF_BASE, 322 MISCREG_MS_EFF_BASE, 323 MISCREG_TR_EFF_BASE, 324 MISCREG_IDTR_EFF_BASE, 325 326 // Hidden segment limit field 327 MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS, 328 MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE, 329 MISCREG_CS_LIMIT, 330 MISCREG_SS_LIMIT, 331 MISCREG_DS_LIMIT, 332 MISCREG_FS_LIMIT, 333 MISCREG_GS_LIMIT, 334 MISCREG_HS_LIMIT, 335 MISCREG_TSL_LIMIT, 336 MISCREG_TSG_LIMIT, 337 MISCREG_LS_LIMIT, 338 MISCREG_MS_LIMIT, 339 MISCREG_TR_LIMIT, 340 MISCREG_IDTR_LIMIT, 341 342 // Hidden segment limit attributes 343 MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS, 344 MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE, 345 MISCREG_CS_ATTR, 346 MISCREG_SS_ATTR, 347 MISCREG_DS_ATTR, 348 MISCREG_FS_ATTR, 349 MISCREG_GS_ATTR, 350 MISCREG_HS_ATTR, 351 MISCREG_TSL_ATTR, 352 MISCREG_TSG_ATTR, 353 MISCREG_LS_ATTR, 354 MISCREG_MS_ATTR, 355 MISCREG_TR_ATTR, 356 MISCREG_IDTR_ATTR, 357 358 // Floating point control registers 359 MISCREG_X87_TOP = 360 MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS, 361 362 MISCREG_MXCSR, 363 MISCREG_FCW, 364 MISCREG_FSW, 365 MISCREG_FTW, 366 MISCREG_FTAG, 367 MISCREG_FISEG, 368 MISCREG_FIOFF, 369 MISCREG_FOSEG, 370 MISCREG_FOOFF, 371 MISCREG_FOP, 372 373 //XXX Add "Model-Specific Registers" 374 375 MISCREG_APIC_BASE, 376 377 // "Fake" MSRs for internally implemented devices 378 MISCREG_PCI_CONFIG_ADDRESS, 379 380 NUM_MISCREGS 381 }; 382 383 static inline MiscRegIndex 384 MISCREG_CR(int index) 385 { 386 assert(index >= 0 && index < NumCRegs); 387 return (MiscRegIndex)(MISCREG_CR_BASE + index); 388 } 389 390 static inline MiscRegIndex 391 MISCREG_DR(int index) 392 { 393 assert(index >= 0 && index < NumDRegs); 394 return (MiscRegIndex)(MISCREG_DR_BASE + index); 395 } 396 397 static inline MiscRegIndex 398 MISCREG_MTRR_PHYS_BASE(int index) 399 { 400 assert(index >= 0 && index < (MISCREG_MTRR_PHYS_BASE_END - 401 MISCREG_MTRR_PHYS_BASE_BASE)); 402 return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index); 403 } 404 405 static inline MiscRegIndex 406 MISCREG_MTRR_PHYS_MASK(int index) 407 { 408 assert(index >= 0 && index < (MISCREG_MTRR_PHYS_MASK_END - 409 MISCREG_MTRR_PHYS_MASK_BASE)); 410 return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index); 411 } 412 413 static inline MiscRegIndex 414 MISCREG_MC_CTL(int index) 415 { 416 assert(index >= 0 && index < (MISCREG_MC_CTL_END - 417 MISCREG_MC_CTL_BASE)); 418 return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index); 419 } 420 421 static inline MiscRegIndex 422 MISCREG_MC_STATUS(int index) 423 { 424 assert(index >= 0 && index < (MISCREG_MC_STATUS_END - 425 MISCREG_MC_STATUS_BASE)); 426 return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index); 427 } 428 429 static inline MiscRegIndex 430 MISCREG_MC_ADDR(int index) 431 { 432 assert(index >= 0 && index < (MISCREG_MC_ADDR_END - 433 MISCREG_MC_ADDR_BASE)); 434 return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index); 435 } 436 437 static inline MiscRegIndex 438 MISCREG_MC_MISC(int index) 439 { 440 assert(index >= 0 && index < (MISCREG_MC_MISC_END - 441 MISCREG_MC_MISC_BASE)); 442 return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index); 443 } 444 445 static inline MiscRegIndex 446 MISCREG_PERF_EVT_SEL(int index) 447 { 448 assert(index >= 0 && index < (MISCREG_PERF_EVT_SEL_END - 449 MISCREG_PERF_EVT_SEL_BASE)); 450 return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index); 451 } 452 453 static inline MiscRegIndex 454 MISCREG_PERF_EVT_CTR(int index) 455 { 456 assert(index >= 0 && index < (MISCREG_PERF_EVT_CTR_END - 457 MISCREG_PERF_EVT_CTR_BASE)); 458 return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index); 459 } 460 461 static inline MiscRegIndex 462 MISCREG_IORR_BASE(int index) 463 { 464 assert(index >= 0 && index < (MISCREG_IORR_BASE_END - 465 MISCREG_IORR_BASE_BASE)); 466 return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index); 467 } 468 469 static inline MiscRegIndex 470 MISCREG_IORR_MASK(int index) 471 { 472 assert(index >= 0 && index < (MISCREG_IORR_MASK_END - 473 MISCREG_IORR_MASK_BASE)); 474 return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index); 475 } 476 477 static inline MiscRegIndex 478 MISCREG_SEG_SEL(int index) 479 { 480 assert(index >= 0 && index < NUM_SEGMENTREGS); 481 return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index); 482 } 483 484 static inline MiscRegIndex 485 MISCREG_SEG_BASE(int index) 486 { 487 assert(index >= 0 && index < NUM_SEGMENTREGS); 488 return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index); 489 } 490 491 static inline MiscRegIndex 492 MISCREG_SEG_EFF_BASE(int index) 493 { 494 assert(index >= 0 && index < NUM_SEGMENTREGS); 495 return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index); 496 } 497 498 static inline MiscRegIndex 499 MISCREG_SEG_LIMIT(int index) 500 { 501 assert(index >= 0 && index < NUM_SEGMENTREGS); 502 return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index); 503 } 504 505 static inline MiscRegIndex 506 MISCREG_SEG_ATTR(int index) 507 { 508 assert(index >= 0 && index < NUM_SEGMENTREGS); 509 return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index); 510 } 511 512 /** 513 * A type to describe the condition code bits of the RFLAGS register, 514 * plus two flags, EZF and ECF, which are only visible to microcode. 515 */ 516 BitUnion64(CCFlagBits) 517 Bitfield<11> of; 518 Bitfield<7> sf; 519 Bitfield<6> zf; 520 Bitfield<5> ezf; 521 Bitfield<4> af; 522 Bitfield<3> ecf; 523 Bitfield<2> pf; 524 Bitfield<0> cf; 525 EndBitUnion(CCFlagBits) 526 527 /** 528 * RFLAGS 529 */ 530 BitUnion64(RFLAGS) 531 Bitfield<21> id; // ID Flag 532 Bitfield<20> vip; // Virtual Interrupt Pending 533 Bitfield<19> vif; // Virtual Interrupt Flag 534 Bitfield<18> ac; // Alignment Check 535 Bitfield<17> vm; // Virtual-8086 Mode 536 Bitfield<16> rf; // Resume Flag 537 Bitfield<14> nt; // Nested Task 538 Bitfield<13, 12> iopl; // I/O Privilege Level 539 Bitfield<11> of; // Overflow Flag 540 Bitfield<10> df; // Direction Flag 541 Bitfield<9> intf; // Interrupt Flag 542 Bitfield<8> tf; // Trap Flag 543 Bitfield<7> sf; // Sign Flag 544 Bitfield<6> zf; // Zero Flag 545 Bitfield<4> af; // Auxiliary Flag 546 Bitfield<2> pf; // Parity Flag 547 Bitfield<0> cf; // Carry Flag 548 EndBitUnion(RFLAGS) 549 550 BitUnion64(HandyM5Reg) 551 Bitfield<0> mode; 552 Bitfield<3, 1> submode; 553 Bitfield<5, 4> cpl; 554 Bitfield<6> paging; 555 Bitfield<7> prot; 556 Bitfield<9, 8> defOp; 557 Bitfield<11, 10> altOp; 558 Bitfield<13, 12> defAddr; 559 Bitfield<15, 14> altAddr; 560 Bitfield<17, 16> stack; 561 EndBitUnion(HandyM5Reg) 562 563 /** 564 * Control registers 565 */ 566 BitUnion64(CR0) 567 Bitfield<31> pg; // Paging 568 Bitfield<30> cd; // Cache Disable 569 Bitfield<29> nw; // Not Writethrough 570 Bitfield<18> am; // Alignment Mask 571 Bitfield<16> wp; // Write Protect 572 Bitfield<5> ne; // Numeric Error 573 Bitfield<4> et; // Extension Type 574 Bitfield<3> ts; // Task Switched 575 Bitfield<2> em; // Emulation 576 Bitfield<1> mp; // Monitor Coprocessor 577 Bitfield<0> pe; // Protection Enabled 578 EndBitUnion(CR0) 579 580 // Page Fault Virtual Address 581 BitUnion64(CR2) 582 Bitfield<31, 0> legacy; 583 EndBitUnion(CR2) 584 585 BitUnion64(CR3) 586 Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table 587 // Base Address 588 Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table 589 // Base Address 590 Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table 591 // Base Address 592 Bitfield<4> pcd; // Page-Level Cache Disable 593 Bitfield<3> pwt; // Page-Level Writethrough 594 EndBitUnion(CR3) 595 596 BitUnion64(CR4) 597 Bitfield<10> osxmmexcpt; // Operating System Unmasked 598 // Exception Support 599 Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support 600 Bitfield<8> pce; // Performance-Monitoring Counter Enable 601 Bitfield<7> pge; // Page-Global Enable 602 Bitfield<6> mce; // Machine Check Enable 603 Bitfield<5> pae; // Physical-Address Extension 604 Bitfield<4> pse; // Page Size Extensions 605 Bitfield<3> de; // Debugging Extensions 606 Bitfield<2> tsd; // Time Stamp Disable 607 Bitfield<1> pvi; // Protected-Mode Virtual Interrupts 608 Bitfield<0> vme; // Virtual-8086 Mode Extensions 609 EndBitUnion(CR4) 610 611 BitUnion64(CR8) 612 Bitfield<3, 0> tpr; // Task Priority Register 613 EndBitUnion(CR8) 614 615 BitUnion64(DR6) 616 Bitfield<0> b0; 617 Bitfield<1> b1; 618 Bitfield<2> b2; 619 Bitfield<3> b3; 620 Bitfield<13> bd; 621 Bitfield<14> bs; 622 Bitfield<15> bt; 623 EndBitUnion(DR6) 624 625 BitUnion64(DR7) 626 Bitfield<0> l0; 627 Bitfield<1> g0; 628 Bitfield<2> l1; 629 Bitfield<3> g1; 630 Bitfield<4> l2; 631 Bitfield<5> g2; 632 Bitfield<6> l3; 633 Bitfield<7> g3; 634 Bitfield<8> le; 635 Bitfield<9> ge; 636 Bitfield<13> gd; 637 Bitfield<17, 16> rw0; 638 Bitfield<19, 18> len0; 639 Bitfield<21, 20> rw1; 640 Bitfield<23, 22> len1; 641 Bitfield<25, 24> rw2; 642 Bitfield<27, 26> len2; 643 Bitfield<29, 28> rw3; 644 Bitfield<31, 30> len3; 645 EndBitUnion(DR7) 646 647 // MTRR capabilities 648 BitUnion64(MTRRcap) 649 Bitfield<7, 0> vcnt; // Variable-Range Register Count 650 Bitfield<8> fix; // Fixed-Range Registers 651 Bitfield<10> wc; // Write-Combining 652 EndBitUnion(MTRRcap) 653 654 /** 655 * SYSENTER configuration registers 656 */ 657 BitUnion64(SysenterCS) 658 Bitfield<15, 0> targetCS; 659 EndBitUnion(SysenterCS) 660 661 BitUnion64(SysenterESP) 662 Bitfield<31, 0> targetESP; 663 EndBitUnion(SysenterESP) 664 665 BitUnion64(SysenterEIP) 666 Bitfield<31, 0> targetEIP; 667 EndBitUnion(SysenterEIP) 668 669 /** 670 * Global machine check registers 671 */ 672 BitUnion64(McgCap) 673 Bitfield<7, 0> count; // Number of error reporting register banks 674 Bitfield<8> MCGCP; // MCG_CTL register present. 675 EndBitUnion(McgCap) 676 677 BitUnion64(McgStatus) 678 Bitfield<0> ripv; // Restart-IP valid 679 Bitfield<1> eipv; // Error-IP valid 680 Bitfield<2> mcip; // Machine check in-progress 681 EndBitUnion(McgStatus) 682 683 BitUnion64(DebugCtlMsr) 684 Bitfield<0> lbr; // Last-branch record 685 Bitfield<1> btf; // Branch single step 686 Bitfield<2> pb0; // Performance monitoring pin control 0 687 Bitfield<3> pb1; // Performance monitoring pin control 1 688 Bitfield<4> pb2; // Performance monitoring pin control 2 689 Bitfield<5> pb3; // Performance monitoring pin control 3 690 /*uint64_t pb(int index) 691 { 692 return bits(__data, index + 2); 693 }*/ 694 EndBitUnion(DebugCtlMsr) 695 696 BitUnion64(MtrrPhysBase) 697 Bitfield<7, 0> type; // Default memory type 698 Bitfield<51, 12> physbase; // Range physical base address 699 EndBitUnion(MtrrPhysBase) 700 701 BitUnion64(MtrrPhysMask) 702 Bitfield<11> valid; // MTRR pair enable 703 Bitfield<51, 12> physmask; // Range physical mask 704 EndBitUnion(MtrrPhysMask) 705 706 BitUnion64(MtrrFixed) 707 /*uint64_t type(int index) 708 { 709 return bits(__data, index * 8 + 7, index * 8); 710 }*/ 711 EndBitUnion(MtrrFixed) 712 713 BitUnion64(Pat) 714 /*uint64_t pa(int index) 715 { 716 return bits(__data, index * 8 + 2, index * 8); 717 }*/ 718 EndBitUnion(Pat) 719 720 BitUnion64(MtrrDefType) 721 Bitfield<7, 0> type; // Default type 722 Bitfield<10> fe; // Fixed range enable 723 Bitfield<11> e; // MTRR enable 724 EndBitUnion(MtrrDefType) 725 726 /** 727 * Machine check 728 */ 729 BitUnion64(McStatus) 730 Bitfield<15,0> mcaErrorCode; 731 Bitfield<31,16> modelSpecificCode; 732 Bitfield<56,32> otherInfo; 733 Bitfield<57> pcc; // Processor-context corrupt 734 Bitfield<58> addrv; // Error-address register valid 735 Bitfield<59> miscv; // Miscellaneous-error register valid 736 Bitfield<60> en; // Error condition enabled 737 Bitfield<61> uc; // Uncorrected error 738 Bitfield<62> over; // Status register overflow 739 Bitfield<63> val; // Valid 740 EndBitUnion(McStatus) 741 742 BitUnion64(McCtl) 743 /*uint64_t en(int index) 744 { 745 return bits(__data, index); 746 }*/ 747 EndBitUnion(McCtl) 748 749 // Extended feature enable register 750 BitUnion64(Efer) 751 Bitfield<0> sce; // System call extensions 752 Bitfield<8> lme; // Long mode enable 753 Bitfield<10> lma; // Long mode active 754 Bitfield<11> nxe; // No-execute enable 755 Bitfield<12> svme; // Secure virtual machine enable 756 Bitfield<14> ffxsr; // Fast fxsave/fxrstor 757 EndBitUnion(Efer) 758 759 BitUnion64(Star) 760 Bitfield<31,0> targetEip; 761 Bitfield<47,32> syscallCsAndSs; 762 Bitfield<63,48> sysretCsAndSs; 763 EndBitUnion(Star) 764 765 BitUnion64(SfMask) 766 Bitfield<31,0> mask; 767 EndBitUnion(SfMask) 768 769 BitUnion64(PerfEvtSel) 770 Bitfield<7,0> eventMask; 771 Bitfield<15,8> unitMask; 772 Bitfield<16> usr; // User mode 773 Bitfield<17> os; // Operating-system mode 774 Bitfield<18> e; // Edge detect 775 Bitfield<19> pc; // Pin control 776 Bitfield<20> intEn; // Interrupt enable 777 Bitfield<22> en; // Counter enable 778 Bitfield<23> inv; // Invert mask 779 Bitfield<31,24> counterMask; 780 EndBitUnion(PerfEvtSel) 781 782 BitUnion32(Syscfg) 783 Bitfield<18> mfde; // MtrrFixDramEn 784 Bitfield<19> mfdm; // MtrrFixDramModEn 785 Bitfield<20> mvdm; // MtrrVarDramEn 786 Bitfield<21> tom2; // MtrrTom2En 787 EndBitUnion(Syscfg) 788 789 BitUnion64(IorrBase) 790 Bitfield<3> wr; // WrMem Enable 791 Bitfield<4> rd; // RdMem Enable 792 Bitfield<51,12> physbase; // Range physical base address 793 EndBitUnion(IorrBase) 794 795 BitUnion64(IorrMask) 796 Bitfield<11> v; // I/O register pair enable (valid) 797 Bitfield<51,12> physmask; // Range physical mask 798 EndBitUnion(IorrMask) 799 800 BitUnion64(Tom) 801 Bitfield<51,23> physAddr; // Top of memory physical address 802 EndBitUnion(Tom) 803 804 BitUnion64(VmCrMsr) 805 Bitfield<0> dpd; 806 Bitfield<1> rInit; 807 Bitfield<2> disA20M; 808 EndBitUnion(VmCrMsr) 809 810 BitUnion64(IgnneMsr) 811 Bitfield<0> ignne; 812 EndBitUnion(IgnneMsr) 813 814 BitUnion64(SmmCtlMsr) 815 Bitfield<0> dismiss; 816 Bitfield<1> enter; 817 Bitfield<2> smiCycle; 818 Bitfield<3> exit; 819 Bitfield<4> rsmCycle; 820 EndBitUnion(SmmCtlMsr) 821 822 /** 823 * Segment Selector 824 */ 825 BitUnion64(SegSelector) 826 // The following bitfield is not defined in the ISA, but it's useful 827 // when checking selectors in larger data types to make sure they 828 // aren't too large. 829 Bitfield<63, 3> esi; // Extended selector 830 Bitfield<15, 3> si; // Selector Index 831 Bitfield<2> ti; // Table Indicator 832 Bitfield<1, 0> rpl; // Requestor Privilege Level 833 EndBitUnion(SegSelector) 834 835 /** 836 * Segment Descriptors 837 */ 838 839 BitUnion64(SegDescriptor) 840 Bitfield<63, 56> baseHigh; 841 Bitfield<39, 16> baseLow; 842 Bitfield<55> g; // Granularity 843 Bitfield<54> d; // Default Operand Size 844 Bitfield<54> b; // Default Operand Size 845 Bitfield<53> l; // Long Attribute Bit 846 Bitfield<52> avl; // Available To Software 847 Bitfield<51, 48> limitHigh; 848 Bitfield<15, 0> limitLow; 849 Bitfield<47> p; // Present 850 Bitfield<46, 45> dpl; // Descriptor Privilege-Level 851 Bitfield<44> s; // System 852 SubBitUnion(type, 43, 40) 853 // Specifies whether this descriptor is for code or data. 854 Bitfield<43> codeOrData; 855 856 // These bit fields are for code segments 857 Bitfield<42> c; // Conforming 858 Bitfield<41> r; // Readable 859 860 // These bit fields are for data segments 861 Bitfield<42> e; // Expand-Down 862 Bitfield<41> w; // Writable 863 864 // This is used for both code and data segments. 865 Bitfield<40> a; // Accessed 866 EndSubBitUnion(type) 867 EndBitUnion(SegDescriptor) 868 869 BitUnion64(SegAttr) 870 Bitfield<1, 0> dpl; 871 Bitfield<2> unusable; 872 Bitfield<3> defaultSize; 873 Bitfield<4> longMode; 874 Bitfield<5> avl; 875 Bitfield<6> granularity; 876 Bitfield<7> present; 877 Bitfield<11, 8> type; 878 Bitfield<12> writable; 879 Bitfield<13> readable; 880 Bitfield<14> expandDown; 881 Bitfield<15> system; 882 EndBitUnion(SegAttr) 883 884 BitUnion64(GateDescriptor) 885 Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset 886 Bitfield<15, 0> offsetLow; // Target Code-Segment Offset 887 Bitfield<31, 16> selector; // Target Code-Segment Selector 888 Bitfield<47> p; // Present 889 Bitfield<46, 45> dpl; // Descriptor Privilege-Level 890 Bitfield<43, 40> type; 891 Bitfield<36, 32> count; // Parameter Count 892 EndBitUnion(GateDescriptor) 893 894 /** 895 * Descriptor-Table Registers 896 */ 897 BitUnion64(GDTR) 898 EndBitUnion(GDTR) 899 900 BitUnion64(IDTR) 901 EndBitUnion(IDTR) 902 903 BitUnion64(LDTR) 904 EndBitUnion(LDTR) 905 906 /** 907 * Task Register 908 */ 909 BitUnion64(TR) 910 EndBitUnion(TR) 911 912 913 /** 914 * Local APIC Base Register 915 */ 916 BitUnion64(LocalApicBase) 917 Bitfield<51, 12> base; 918 Bitfield<11> enable; 919 Bitfield<8> bsp; 920 EndBitUnion(LocalApicBase) 921} 922 923#endif // __ARCH_X86_INTREGS_HH__ 924