misc.hh revision 7629
1/* 2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 */ 39 40#ifndef __ARCH_X86_MISCREGS_HH__ 41#define __ARCH_X86_MISCREGS_HH__ 42 43#include "arch/x86/regs/segment.hh" 44#include "arch/x86/x86_traits.hh" 45#include "base/bitunion.hh" 46 47//These get defined in some system headers (at least termbits.h). That confuses 48//things here significantly. 49#undef CR0 50#undef CR2 51#undef CR3 52 53namespace X86ISA 54{ 55 enum CondFlagBit { 56 CFBit = 1 << 0, 57 PFBit = 1 << 2, 58 ECFBit = 1 << 3, 59 AFBit = 1 << 4, 60 EZFBit = 1 << 5, 61 ZFBit = 1 << 6, 62 SFBit = 1 << 7, 63 DFBit = 1 << 10, 64 OFBit = 1 << 11 65 }; 66 67 enum RFLAGBit { 68 TFBit = 1 << 8, 69 IFBit = 1 << 9, 70 NTBit = 1 << 14, 71 RFBit = 1 << 16, 72 VMBit = 1 << 17, 73 ACBit = 1 << 18, 74 VIFBit = 1 << 19, 75 VIPBit = 1 << 20, 76 IDBit = 1 << 21 77 }; 78 79 enum MiscRegIndex 80 { 81 // Control registers 82 // Most of these are invalid. 83 MISCREG_CR_BASE, 84 MISCREG_CR0 = MISCREG_CR_BASE, 85 MISCREG_CR1, 86 MISCREG_CR2, 87 MISCREG_CR3, 88 MISCREG_CR4, 89 MISCREG_CR5, 90 MISCREG_CR6, 91 MISCREG_CR7, 92 MISCREG_CR8, 93 MISCREG_CR9, 94 MISCREG_CR10, 95 MISCREG_CR11, 96 MISCREG_CR12, 97 MISCREG_CR13, 98 MISCREG_CR14, 99 MISCREG_CR15, 100 101 // Debug registers 102 MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs, 103 MISCREG_DR0 = MISCREG_DR_BASE, 104 MISCREG_DR1, 105 MISCREG_DR2, 106 MISCREG_DR3, 107 MISCREG_DR4, 108 MISCREG_DR5, 109 MISCREG_DR6, 110 MISCREG_DR7, 111 112 // Flags register 113 MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs, 114 115 //Register to keep handy values like the CPU mode in. 116 MISCREG_M5_REG, 117 118 /* 119 * Model Specific Registers 120 */ 121 // Time stamp counter 122 MISCREG_TSC, 123 124 MISCREG_MTRRCAP, 125 126 MISCREG_SYSENTER_CS, 127 MISCREG_SYSENTER_ESP, 128 MISCREG_SYSENTER_EIP, 129 130 MISCREG_MCG_CAP, 131 MISCREG_MCG_STATUS, 132 MISCREG_MCG_CTL, 133 134 MISCREG_DEBUG_CTL_MSR, 135 136 MISCREG_LAST_BRANCH_FROM_IP, 137 MISCREG_LAST_BRANCH_TO_IP, 138 MISCREG_LAST_EXCEPTION_FROM_IP, 139 MISCREG_LAST_EXCEPTION_TO_IP, 140 141 MISCREG_MTRR_PHYS_BASE_BASE, 142 MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE, 143 MISCREG_MTRR_PHYS_BASE_1, 144 MISCREG_MTRR_PHYS_BASE_2, 145 MISCREG_MTRR_PHYS_BASE_3, 146 MISCREG_MTRR_PHYS_BASE_4, 147 MISCREG_MTRR_PHYS_BASE_5, 148 MISCREG_MTRR_PHYS_BASE_6, 149 MISCREG_MTRR_PHYS_BASE_7, 150 MISCREG_MTRR_PHYS_BASE_END, 151 152 MISCREG_MTRR_PHYS_MASK_BASE = MISCREG_MTRR_PHYS_BASE_END, 153 MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE, 154 MISCREG_MTRR_PHYS_MASK_1, 155 MISCREG_MTRR_PHYS_MASK_2, 156 MISCREG_MTRR_PHYS_MASK_3, 157 MISCREG_MTRR_PHYS_MASK_4, 158 MISCREG_MTRR_PHYS_MASK_5, 159 MISCREG_MTRR_PHYS_MASK_6, 160 MISCREG_MTRR_PHYS_MASK_7, 161 MISCREG_MTRR_PHYS_MASK_END, 162 163 MISCREG_MTRR_FIX_64K_00000 = MISCREG_MTRR_PHYS_MASK_END, 164 MISCREG_MTRR_FIX_16K_80000, 165 MISCREG_MTRR_FIX_16K_A0000, 166 MISCREG_MTRR_FIX_4K_C0000, 167 MISCREG_MTRR_FIX_4K_C8000, 168 MISCREG_MTRR_FIX_4K_D0000, 169 MISCREG_MTRR_FIX_4K_D8000, 170 MISCREG_MTRR_FIX_4K_E0000, 171 MISCREG_MTRR_FIX_4K_E8000, 172 MISCREG_MTRR_FIX_4K_F0000, 173 MISCREG_MTRR_FIX_4K_F8000, 174 175 MISCREG_PAT, 176 177 MISCREG_DEF_TYPE, 178 179 MISCREG_MC_CTL_BASE, 180 MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE, 181 MISCREG_MC1_CTL, 182 MISCREG_MC2_CTL, 183 MISCREG_MC3_CTL, 184 MISCREG_MC4_CTL, 185 MISCREG_MC5_CTL, 186 MISCREG_MC6_CTL, 187 MISCREG_MC7_CTL, 188 MISCREG_MC_CTL_END, 189 190 MISCREG_MC_STATUS_BASE = MISCREG_MC_CTL_END, 191 MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE, 192 MISCREG_MC1_STATUS, 193 MISCREG_MC2_STATUS, 194 MISCREG_MC3_STATUS, 195 MISCREG_MC4_STATUS, 196 MISCREG_MC5_STATUS, 197 MISCREG_MC6_STATUS, 198 MISCREG_MC7_STATUS, 199 MISCREG_MC_STATUS_END, 200 201 MISCREG_MC_ADDR_BASE = MISCREG_MC_STATUS_END, 202 MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE, 203 MISCREG_MC1_ADDR, 204 MISCREG_MC2_ADDR, 205 MISCREG_MC3_ADDR, 206 MISCREG_MC4_ADDR, 207 MISCREG_MC5_ADDR, 208 MISCREG_MC6_ADDR, 209 MISCREG_MC7_ADDR, 210 MISCREG_MC_ADDR_END, 211 212 MISCREG_MC_MISC_BASE = MISCREG_MC_ADDR_END, 213 MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE, 214 MISCREG_MC1_MISC, 215 MISCREG_MC2_MISC, 216 MISCREG_MC3_MISC, 217 MISCREG_MC4_MISC, 218 MISCREG_MC5_MISC, 219 MISCREG_MC6_MISC, 220 MISCREG_MC7_MISC, 221 MISCREG_MC_MISC_END, 222 223 // Extended feature enable register 224 MISCREG_EFER = MISCREG_MC_MISC_END, 225 226 MISCREG_STAR, 227 MISCREG_LSTAR, 228 MISCREG_CSTAR, 229 230 MISCREG_SF_MASK, 231 232 MISCREG_KERNEL_GS_BASE, 233 234 MISCREG_TSC_AUX, 235 236 MISCREG_PERF_EVT_SEL_BASE, 237 MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE, 238 MISCREG_PERF_EVT_SEL1, 239 MISCREG_PERF_EVT_SEL2, 240 MISCREG_PERF_EVT_SEL3, 241 MISCREG_PERF_EVT_SEL_END, 242 243 MISCREG_PERF_EVT_CTR_BASE = MISCREG_PERF_EVT_SEL_END, 244 MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE, 245 MISCREG_PERF_EVT_CTR1, 246 MISCREG_PERF_EVT_CTR2, 247 MISCREG_PERF_EVT_CTR3, 248 MISCREG_PERF_EVT_CTR_END, 249 250 MISCREG_SYSCFG = MISCREG_PERF_EVT_CTR_END, 251 252 MISCREG_IORR_BASE_BASE, 253 MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE, 254 MISCREG_IORR_BASE1, 255 MISCREG_IORR_BASE_END, 256 257 MISCREG_IORR_MASK_BASE = MISCREG_IORR_BASE_END, 258 MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE, 259 MISCREG_IORR_MASK1, 260 MISCREG_IORR_MASK_END, 261 262 MISCREG_TOP_MEM = MISCREG_IORR_MASK_END, 263 MISCREG_TOP_MEM2, 264 265 MISCREG_VM_CR, 266 MISCREG_IGNNE, 267 MISCREG_SMM_CTL, 268 MISCREG_VM_HSAVE_PA, 269 270 /* 271 * Segment registers 272 */ 273 // Segment selectors 274 MISCREG_SEG_SEL_BASE, 275 MISCREG_ES = MISCREG_SEG_SEL_BASE, 276 MISCREG_CS, 277 MISCREG_SS, 278 MISCREG_DS, 279 MISCREG_FS, 280 MISCREG_GS, 281 MISCREG_HS, 282 MISCREG_TSL, 283 MISCREG_TSG, 284 MISCREG_LS, 285 MISCREG_MS, 286 MISCREG_TR, 287 MISCREG_IDTR, 288 289 // Hidden segment base field 290 MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS, 291 MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE, 292 MISCREG_CS_BASE, 293 MISCREG_SS_BASE, 294 MISCREG_DS_BASE, 295 MISCREG_FS_BASE, 296 MISCREG_GS_BASE, 297 MISCREG_HS_BASE, 298 MISCREG_TSL_BASE, 299 MISCREG_TSG_BASE, 300 MISCREG_LS_BASE, 301 MISCREG_MS_BASE, 302 MISCREG_TR_BASE, 303 MISCREG_IDTR_BASE, 304 305 // The effective segment base, ie what is actually added to an 306 // address. In 64 bit mode this can be different from the above, 307 // namely 0. 308 MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS, 309 MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE, 310 MISCREG_CS_EFF_BASE, 311 MISCREG_SS_EFF_BASE, 312 MISCREG_DS_EFF_BASE, 313 MISCREG_FS_EFF_BASE, 314 MISCREG_GS_EFF_BASE, 315 MISCREG_HS_EFF_BASE, 316 MISCREG_TSL_EFF_BASE, 317 MISCREG_TSG_EFF_BASE, 318 MISCREG_LS_EFF_BASE, 319 MISCREG_MS_EFF_BASE, 320 MISCREG_TR_EFF_BASE, 321 MISCREG_IDTR_EFF_BASE, 322 323 // Hidden segment limit field 324 MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS, 325 MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE, 326 MISCREG_CS_LIMIT, 327 MISCREG_SS_LIMIT, 328 MISCREG_DS_LIMIT, 329 MISCREG_FS_LIMIT, 330 MISCREG_GS_LIMIT, 331 MISCREG_HS_LIMIT, 332 MISCREG_TSL_LIMIT, 333 MISCREG_TSG_LIMIT, 334 MISCREG_LS_LIMIT, 335 MISCREG_MS_LIMIT, 336 MISCREG_TR_LIMIT, 337 MISCREG_IDTR_LIMIT, 338 339 // Hidden segment limit attributes 340 MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS, 341 MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE, 342 MISCREG_CS_ATTR, 343 MISCREG_SS_ATTR, 344 MISCREG_DS_ATTR, 345 MISCREG_FS_ATTR, 346 MISCREG_GS_ATTR, 347 MISCREG_HS_ATTR, 348 MISCREG_TSL_ATTR, 349 MISCREG_TSG_ATTR, 350 MISCREG_LS_ATTR, 351 MISCREG_MS_ATTR, 352 MISCREG_TR_ATTR, 353 MISCREG_IDTR_ATTR, 354 355 // Floating point control registers 356 MISCREG_X87_TOP = 357 MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS, 358 359 MISCREG_MXCSR, 360 MISCREG_FCW, 361 MISCREG_FSW, 362 MISCREG_FTW, 363 MISCREG_FTAG, 364 MISCREG_FISEG, 365 MISCREG_FIOFF, 366 MISCREG_FOSEG, 367 MISCREG_FOOFF, 368 MISCREG_FOP, 369 370 //XXX Add "Model-Specific Registers" 371 372 MISCREG_APIC_BASE, 373 374 // "Fake" MSRs for internally implemented devices 375 MISCREG_PCI_CONFIG_ADDRESS, 376 377 NUM_MISCREGS 378 }; 379 380 static inline MiscRegIndex 381 MISCREG_CR(int index) 382 { 383 assert(index >= 0 && index < NumCRegs); 384 return (MiscRegIndex)(MISCREG_CR_BASE + index); 385 } 386 387 static inline MiscRegIndex 388 MISCREG_DR(int index) 389 { 390 assert(index >= 0 && index < NumDRegs); 391 return (MiscRegIndex)(MISCREG_DR_BASE + index); 392 } 393 394 static inline MiscRegIndex 395 MISCREG_MTRR_PHYS_BASE(int index) 396 { 397 assert(index >= 0 && index < (MISCREG_MTRR_PHYS_BASE_END - 398 MISCREG_MTRR_PHYS_BASE_BASE)); 399 return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index); 400 } 401 402 static inline MiscRegIndex 403 MISCREG_MTRR_PHYS_MASK(int index) 404 { 405 assert(index >= 0 && index < (MISCREG_MTRR_PHYS_MASK_END - 406 MISCREG_MTRR_PHYS_MASK_BASE)); 407 return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index); 408 } 409 410 static inline MiscRegIndex 411 MISCREG_MC_CTL(int index) 412 { 413 assert(index >= 0 && index < (MISCREG_MC_CTL_END - 414 MISCREG_MC_CTL_BASE)); 415 return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index); 416 } 417 418 static inline MiscRegIndex 419 MISCREG_MC_STATUS(int index) 420 { 421 assert(index >= 0 && index < (MISCREG_MC_STATUS_END - 422 MISCREG_MC_STATUS_BASE)); 423 return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index); 424 } 425 426 static inline MiscRegIndex 427 MISCREG_MC_ADDR(int index) 428 { 429 assert(index >= 0 && index < (MISCREG_MC_ADDR_END - 430 MISCREG_MC_ADDR_BASE)); 431 return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index); 432 } 433 434 static inline MiscRegIndex 435 MISCREG_MC_MISC(int index) 436 { 437 assert(index >= 0 && index < (MISCREG_MC_MISC_END - 438 MISCREG_MC_MISC_BASE)); 439 return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index); 440 } 441 442 static inline MiscRegIndex 443 MISCREG_PERF_EVT_SEL(int index) 444 { 445 assert(index >= 0 && index < (MISCREG_PERF_EVT_SEL_END - 446 MISCREG_PERF_EVT_SEL_BASE)); 447 return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index); 448 } 449 450 static inline MiscRegIndex 451 MISCREG_PERF_EVT_CTR(int index) 452 { 453 assert(index >= 0 && index < (MISCREG_PERF_EVT_CTR_END - 454 MISCREG_PERF_EVT_CTR_BASE)); 455 return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index); 456 } 457 458 static inline MiscRegIndex 459 MISCREG_IORR_BASE(int index) 460 { 461 assert(index >= 0 && index < (MISCREG_IORR_BASE_END - 462 MISCREG_IORR_BASE_BASE)); 463 return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index); 464 } 465 466 static inline MiscRegIndex 467 MISCREG_IORR_MASK(int index) 468 { 469 assert(index >= 0 && index < (MISCREG_IORR_MASK_END - 470 MISCREG_IORR_MASK_BASE)); 471 return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index); 472 } 473 474 static inline MiscRegIndex 475 MISCREG_SEG_SEL(int index) 476 { 477 assert(index >= 0 && index < NUM_SEGMENTREGS); 478 return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index); 479 } 480 481 static inline MiscRegIndex 482 MISCREG_SEG_BASE(int index) 483 { 484 assert(index >= 0 && index < NUM_SEGMENTREGS); 485 return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index); 486 } 487 488 static inline MiscRegIndex 489 MISCREG_SEG_EFF_BASE(int index) 490 { 491 assert(index >= 0 && index < NUM_SEGMENTREGS); 492 return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index); 493 } 494 495 static inline MiscRegIndex 496 MISCREG_SEG_LIMIT(int index) 497 { 498 assert(index >= 0 && index < NUM_SEGMENTREGS); 499 return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index); 500 } 501 502 static inline MiscRegIndex 503 MISCREG_SEG_ATTR(int index) 504 { 505 assert(index >= 0 && index < NUM_SEGMENTREGS); 506 return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index); 507 } 508 509 /** 510 * A type to describe the condition code bits of the RFLAGS register, 511 * plus two flags, EZF and ECF, which are only visible to microcode. 512 */ 513 BitUnion64(CCFlagBits) 514 Bitfield<11> of; 515 Bitfield<7> sf; 516 Bitfield<6> zf; 517 Bitfield<5> ezf; 518 Bitfield<4> af; 519 Bitfield<3> ecf; 520 Bitfield<2> pf; 521 Bitfield<0> cf; 522 EndBitUnion(CCFlagBits) 523 524 /** 525 * RFLAGS 526 */ 527 BitUnion64(RFLAGS) 528 Bitfield<21> id; // ID Flag 529 Bitfield<20> vip; // Virtual Interrupt Pending 530 Bitfield<19> vif; // Virtual Interrupt Flag 531 Bitfield<18> ac; // Alignment Check 532 Bitfield<17> vm; // Virtual-8086 Mode 533 Bitfield<16> rf; // Resume Flag 534 Bitfield<14> nt; // Nested Task 535 Bitfield<13, 12> iopl; // I/O Privilege Level 536 Bitfield<11> of; // Overflow Flag 537 Bitfield<10> df; // Direction Flag 538 Bitfield<9> intf; // Interrupt Flag 539 Bitfield<8> tf; // Trap Flag 540 Bitfield<7> sf; // Sign Flag 541 Bitfield<6> zf; // Zero Flag 542 Bitfield<4> af; // Auxiliary Flag 543 Bitfield<2> pf; // Parity Flag 544 Bitfield<0> cf; // Carry Flag 545 EndBitUnion(RFLAGS) 546 547 BitUnion64(HandyM5Reg) 548 Bitfield<0> mode; 549 Bitfield<3, 1> submode; 550 Bitfield<5, 4> cpl; 551 Bitfield<6> paging; 552 Bitfield<7> prot; 553 Bitfield<9, 8> defOp; 554 Bitfield<11, 10> altOp; 555 Bitfield<13, 12> defAddr; 556 Bitfield<15, 14> altAddr; 557 Bitfield<17, 16> stack; 558 EndBitUnion(HandyM5Reg) 559 560 /** 561 * Control registers 562 */ 563 BitUnion64(CR0) 564 Bitfield<31> pg; // Paging 565 Bitfield<30> cd; // Cache Disable 566 Bitfield<29> nw; // Not Writethrough 567 Bitfield<18> am; // Alignment Mask 568 Bitfield<16> wp; // Write Protect 569 Bitfield<5> ne; // Numeric Error 570 Bitfield<4> et; // Extension Type 571 Bitfield<3> ts; // Task Switched 572 Bitfield<2> em; // Emulation 573 Bitfield<1> mp; // Monitor Coprocessor 574 Bitfield<0> pe; // Protection Enabled 575 EndBitUnion(CR0) 576 577 // Page Fault Virtual Address 578 BitUnion64(CR2) 579 Bitfield<31, 0> legacy; 580 EndBitUnion(CR2) 581 582 BitUnion64(CR3) 583 Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table 584 // Base Address 585 Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table 586 // Base Address 587 Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table 588 // Base Address 589 Bitfield<4> pcd; // Page-Level Cache Disable 590 Bitfield<3> pwt; // Page-Level Writethrough 591 EndBitUnion(CR3) 592 593 BitUnion64(CR4) 594 Bitfield<10> osxmmexcpt; // Operating System Unmasked 595 // Exception Support 596 Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support 597 Bitfield<8> pce; // Performance-Monitoring Counter Enable 598 Bitfield<7> pge; // Page-Global Enable 599 Bitfield<6> mce; // Machine Check Enable 600 Bitfield<5> pae; // Physical-Address Extension 601 Bitfield<4> pse; // Page Size Extensions 602 Bitfield<3> de; // Debugging Extensions 603 Bitfield<2> tsd; // Time Stamp Disable 604 Bitfield<1> pvi; // Protected-Mode Virtual Interrupts 605 Bitfield<0> vme; // Virtual-8086 Mode Extensions 606 EndBitUnion(CR4) 607 608 BitUnion64(CR8) 609 Bitfield<3, 0> tpr; // Task Priority Register 610 EndBitUnion(CR8) 611 612 BitUnion64(DR6) 613 Bitfield<0> b0; 614 Bitfield<1> b1; 615 Bitfield<2> b2; 616 Bitfield<3> b3; 617 Bitfield<13> bd; 618 Bitfield<14> bs; 619 Bitfield<15> bt; 620 EndBitUnion(DR6) 621 622 BitUnion64(DR7) 623 Bitfield<0> l0; 624 Bitfield<1> g0; 625 Bitfield<2> l1; 626 Bitfield<3> g1; 627 Bitfield<4> l2; 628 Bitfield<5> g2; 629 Bitfield<6> l3; 630 Bitfield<7> g3; 631 Bitfield<8> le; 632 Bitfield<9> ge; 633 Bitfield<13> gd; 634 Bitfield<17, 16> rw0; 635 Bitfield<19, 18> len0; 636 Bitfield<21, 20> rw1; 637 Bitfield<23, 22> len1; 638 Bitfield<25, 24> rw2; 639 Bitfield<27, 26> len2; 640 Bitfield<29, 28> rw3; 641 Bitfield<31, 30> len3; 642 EndBitUnion(DR7) 643 644 // MTRR capabilities 645 BitUnion64(MTRRcap) 646 Bitfield<7, 0> vcnt; // Variable-Range Register Count 647 Bitfield<8> fix; // Fixed-Range Registers 648 Bitfield<10> wc; // Write-Combining 649 EndBitUnion(MTRRcap) 650 651 /** 652 * SYSENTER configuration registers 653 */ 654 BitUnion64(SysenterCS) 655 Bitfield<15, 0> targetCS; 656 EndBitUnion(SysenterCS) 657 658 BitUnion64(SysenterESP) 659 Bitfield<31, 0> targetESP; 660 EndBitUnion(SysenterESP) 661 662 BitUnion64(SysenterEIP) 663 Bitfield<31, 0> targetEIP; 664 EndBitUnion(SysenterEIP) 665 666 /** 667 * Global machine check registers 668 */ 669 BitUnion64(McgCap) 670 Bitfield<7, 0> count; // Number of error reporting register banks 671 Bitfield<8> MCGCP; // MCG_CTL register present. 672 EndBitUnion(McgCap) 673 674 BitUnion64(McgStatus) 675 Bitfield<0> ripv; // Restart-IP valid 676 Bitfield<1> eipv; // Error-IP valid 677 Bitfield<2> mcip; // Machine check in-progress 678 EndBitUnion(McgStatus) 679 680 BitUnion64(DebugCtlMsr) 681 Bitfield<0> lbr; // Last-branch record 682 Bitfield<1> btf; // Branch single step 683 Bitfield<2> pb0; // Performance monitoring pin control 0 684 Bitfield<3> pb1; // Performance monitoring pin control 1 685 Bitfield<4> pb2; // Performance monitoring pin control 2 686 Bitfield<5> pb3; // Performance monitoring pin control 3 687 /*uint64_t pb(int index) 688 { 689 return bits(__data, index + 2); 690 }*/ 691 EndBitUnion(DebugCtlMsr) 692 693 BitUnion64(MtrrPhysBase) 694 Bitfield<7, 0> type; // Default memory type 695 Bitfield<51, 12> physbase; // Range physical base address 696 EndBitUnion(MtrrPhysBase) 697 698 BitUnion64(MtrrPhysMask) 699 Bitfield<11> valid; // MTRR pair enable 700 Bitfield<51, 12> physmask; // Range physical mask 701 EndBitUnion(MtrrPhysMask) 702 703 BitUnion64(MtrrFixed) 704 /*uint64_t type(int index) 705 { 706 return bits(__data, index * 8 + 7, index * 8); 707 }*/ 708 EndBitUnion(MtrrFixed) 709 710 BitUnion64(Pat) 711 /*uint64_t pa(int index) 712 { 713 return bits(__data, index * 8 + 2, index * 8); 714 }*/ 715 EndBitUnion(Pat) 716 717 BitUnion64(MtrrDefType) 718 Bitfield<7, 0> type; // Default type 719 Bitfield<10> fe; // Fixed range enable 720 Bitfield<11> e; // MTRR enable 721 EndBitUnion(MtrrDefType) 722 723 /** 724 * Machine check 725 */ 726 BitUnion64(McStatus) 727 Bitfield<15,0> mcaErrorCode; 728 Bitfield<31,16> modelSpecificCode; 729 Bitfield<56,32> otherInfo; 730 Bitfield<57> pcc; // Processor-context corrupt 731 Bitfield<58> addrv; // Error-address register valid 732 Bitfield<59> miscv; // Miscellaneous-error register valid 733 Bitfield<60> en; // Error condition enabled 734 Bitfield<61> uc; // Uncorrected error 735 Bitfield<62> over; // Status register overflow 736 Bitfield<63> val; // Valid 737 EndBitUnion(McStatus) 738 739 BitUnion64(McCtl) 740 /*uint64_t en(int index) 741 { 742 return bits(__data, index); 743 }*/ 744 EndBitUnion(McCtl) 745 746 // Extended feature enable register 747 BitUnion64(Efer) 748 Bitfield<0> sce; // System call extensions 749 Bitfield<8> lme; // Long mode enable 750 Bitfield<10> lma; // Long mode active 751 Bitfield<11> nxe; // No-execute enable 752 Bitfield<12> svme; // Secure virtual machine enable 753 Bitfield<14> ffxsr; // Fast fxsave/fxrstor 754 EndBitUnion(Efer) 755 756 BitUnion64(Star) 757 Bitfield<31,0> targetEip; 758 Bitfield<47,32> syscallCsAndSs; 759 Bitfield<63,48> sysretCsAndSs; 760 EndBitUnion(Star) 761 762 BitUnion64(SfMask) 763 Bitfield<31,0> mask; 764 EndBitUnion(SfMask) 765 766 BitUnion64(PerfEvtSel) 767 Bitfield<7,0> eventMask; 768 Bitfield<15,8> unitMask; 769 Bitfield<16> usr; // User mode 770 Bitfield<17> os; // Operating-system mode 771 Bitfield<18> e; // Edge detect 772 Bitfield<19> pc; // Pin control 773 Bitfield<20> intEn; // Interrupt enable 774 Bitfield<22> en; // Counter enable 775 Bitfield<23> inv; // Invert mask 776 Bitfield<31,24> counterMask; 777 EndBitUnion(PerfEvtSel) 778 779 BitUnion32(Syscfg) 780 Bitfield<18> mfde; // MtrrFixDramEn 781 Bitfield<19> mfdm; // MtrrFixDramModEn 782 Bitfield<20> mvdm; // MtrrVarDramEn 783 Bitfield<21> tom2; // MtrrTom2En 784 EndBitUnion(Syscfg) 785 786 BitUnion64(IorrBase) 787 Bitfield<3> wr; // WrMem Enable 788 Bitfield<4> rd; // RdMem Enable 789 Bitfield<51,12> physbase; // Range physical base address 790 EndBitUnion(IorrBase) 791 792 BitUnion64(IorrMask) 793 Bitfield<11> v; // I/O register pair enable (valid) 794 Bitfield<51,12> physmask; // Range physical mask 795 EndBitUnion(IorrMask) 796 797 BitUnion64(Tom) 798 Bitfield<51,23> physAddr; // Top of memory physical address 799 EndBitUnion(Tom) 800 801 BitUnion64(VmCrMsr) 802 Bitfield<0> dpd; 803 Bitfield<1> rInit; 804 Bitfield<2> disA20M; 805 EndBitUnion(VmCrMsr) 806 807 BitUnion64(IgnneMsr) 808 Bitfield<0> ignne; 809 EndBitUnion(IgnneMsr) 810 811 BitUnion64(SmmCtlMsr) 812 Bitfield<0> dismiss; 813 Bitfield<1> enter; 814 Bitfield<2> smiCycle; 815 Bitfield<3> exit; 816 Bitfield<4> rsmCycle; 817 EndBitUnion(SmmCtlMsr) 818 819 /** 820 * Segment Selector 821 */ 822 BitUnion64(SegSelector) 823 // The following bitfield is not defined in the ISA, but it's useful 824 // when checking selectors in larger data types to make sure they 825 // aren't too large. 826 Bitfield<63, 3> esi; // Extended selector 827 Bitfield<15, 3> si; // Selector Index 828 Bitfield<2> ti; // Table Indicator 829 Bitfield<1, 0> rpl; // Requestor Privilege Level 830 EndBitUnion(SegSelector) 831 832 /** 833 * Segment Descriptors 834 */ 835 836 BitUnion64(SegDescriptor) 837 Bitfield<63, 56> baseHigh; 838 Bitfield<39, 16> baseLow; 839 Bitfield<55> g; // Granularity 840 Bitfield<54> d; // Default Operand Size 841 Bitfield<54> b; // Default Operand Size 842 Bitfield<53> l; // Long Attribute Bit 843 Bitfield<52> avl; // Available To Software 844 Bitfield<51, 48> limitHigh; 845 Bitfield<15, 0> limitLow; 846 Bitfield<47> p; // Present 847 Bitfield<46, 45> dpl; // Descriptor Privilege-Level 848 Bitfield<44> s; // System 849 SubBitUnion(type, 43, 40) 850 // Specifies whether this descriptor is for code or data. 851 Bitfield<43> codeOrData; 852 853 // These bit fields are for code segments 854 Bitfield<42> c; // Conforming 855 Bitfield<41> r; // Readable 856 857 // These bit fields are for data segments 858 Bitfield<42> e; // Expand-Down 859 Bitfield<41> w; // Writable 860 861 // This is used for both code and data segments. 862 Bitfield<40> a; // Accessed 863 EndSubBitUnion(type) 864 EndBitUnion(SegDescriptor) 865 866 BitUnion64(SegAttr) 867 Bitfield<1, 0> dpl; 868 Bitfield<2> unusable; 869 Bitfield<3> defaultSize; 870 Bitfield<4> longMode; 871 Bitfield<5> avl; 872 Bitfield<6> granularity; 873 Bitfield<7> present; 874 Bitfield<11, 8> type; 875 Bitfield<12> writable; 876 Bitfield<13> readable; 877 Bitfield<14> expandDown; 878 Bitfield<15> system; 879 EndBitUnion(SegAttr) 880 881 BitUnion64(GateDescriptor) 882 Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset 883 Bitfield<15, 0> offsetLow; // Target Code-Segment Offset 884 Bitfield<31, 16> selector; // Target Code-Segment Selector 885 Bitfield<47> p; // Present 886 Bitfield<46, 45> dpl; // Descriptor Privilege-Level 887 Bitfield<43, 40> type; 888 Bitfield<36, 32> count; // Parameter Count 889 EndBitUnion(GateDescriptor) 890 891 /** 892 * Descriptor-Table Registers 893 */ 894 BitUnion64(GDTR) 895 EndBitUnion(GDTR) 896 897 BitUnion64(IDTR) 898 EndBitUnion(IDTR) 899 900 BitUnion64(LDTR) 901 EndBitUnion(LDTR) 902 903 /** 904 * Task Register 905 */ 906 BitUnion64(TR) 907 EndBitUnion(TR) 908 909 910 /** 911 * Local APIC Base Register 912 */ 913 BitUnion64(LocalApicBase) 914 Bitfield<51, 12> base; 915 Bitfield<11> enable; 916 Bitfield<8> bsp; 917 EndBitUnion(LocalApicBase) 918}; 919 920#endif // __ARCH_X86_INTREGS_HH__ 921