misc.hh revision 5360 
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use.  Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 *     Director of Intellectual Property Licensing
21 *     Office of Strategy and Technology
22 *     Hewlett-Packard Company
23 *     1501 Page Mill Road
24 *     Palo Alto, California  94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer.  Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution.  Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission.  No right of
34 * sublicense is granted herewith.  Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses.  Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#ifndef __ARCH_X86_MISCREGS_HH__
59#define __ARCH_X86_MISCREGS_HH__
60
61#include "arch/x86/segmentregs.hh"
62#include "arch/x86/x86_traits.hh"
63#include "base/bitunion.hh"
64
65//These get defined in some system headers (at least termbits.h). That confuses
66//things here significantly.
67#undef CR0
68#undef CR2
69#undef CR3
70
71namespace X86ISA
72{
73    enum CondFlagBit {
74        CFBit = 1 << 0,
75        PFBit = 1 << 2,
76        ECFBit = 1 << 3,
77        AFBit = 1 << 4,
78        EZFBit = 1 << 5,
79        ZFBit = 1 << 6,
80        SFBit = 1 << 7,
81        DFBit = 1 << 10,
82        OFBit = 1 << 11
83    };
84
85    enum MiscRegIndex
86    {
87        // Control registers
88        // Most of these are invalid.
89        MISCREG_CR_BASE,
90        MISCREG_CR0 = MISCREG_CR_BASE,
91        MISCREG_CR1,
92        MISCREG_CR2,
93        MISCREG_CR3,
94        MISCREG_CR4,
95        MISCREG_CR5,
96        MISCREG_CR6,
97        MISCREG_CR7,
98        MISCREG_CR8,
99        MISCREG_CR9,
100        MISCREG_CR10,
101        MISCREG_CR11,
102        MISCREG_CR12,
103        MISCREG_CR13,
104        MISCREG_CR14,
105        MISCREG_CR15,
106
107        // Debug registers
108        MISCREG_DR_BASE = MISCREG_CR_BASE + NumCRegs,
109        MISCREG_DR0 = MISCREG_DR_BASE,
110        MISCREG_DR1,
111        MISCREG_DR2,
112        MISCREG_DR3,
113        MISCREG_DR4,
114        MISCREG_DR5,
115        MISCREG_DR6,
116        MISCREG_DR7,
117
118        // Flags register
119        MISCREG_RFLAGS = MISCREG_DR_BASE + NumDRegs,
120
121        /*
122         * Model Specific Registers
123         */
124        // Time stamp counter
125        MISCREG_TSC,
126
127        MISCREG_MTRRCAP,
128
129        MISCREG_SYSENTER_CS,
130        MISCREG_SYSENTER_ESP,
131        MISCREG_SYSENTER_EIP,
132
133        MISCREG_MCG_CAP,
134        MISCREG_MCG_STATUS,
135        MISCREG_MCG_CTL,
136
137        MISCREG_DEBUG_CTL_MSR,
138
139        MISCREG_LAST_BRANCH_FROM_IP,
140        MISCREG_LAST_BRANCH_TO_IP,
141        MISCREG_LAST_EXCEPTION_FROM_IP,
142        MISCREG_LAST_EXCEPTION_TO_IP,
143
144        MISCREG_MTRR_PHYS_BASE_BASE,
145        MISCREG_MTRR_PHYS_BASE_0 = MISCREG_MTRR_PHYS_BASE_BASE,
146        MISCREG_MTRR_PHYS_BASE_1,
147        MISCREG_MTRR_PHYS_BASE_2,
148        MISCREG_MTRR_PHYS_BASE_3,
149        MISCREG_MTRR_PHYS_BASE_4,
150        MISCREG_MTRR_PHYS_BASE_5,
151        MISCREG_MTRR_PHYS_BASE_6,
152        MISCREG_MTRR_PHYS_BASE_7,
153
154        MISCREG_MTRR_PHYS_MASK_BASE,
155        MISCREG_MTRR_PHYS_MASK_0 = MISCREG_MTRR_PHYS_MASK_BASE,
156        MISCREG_MTRR_PHYS_MASK_1,
157        MISCREG_MTRR_PHYS_MASK_2,
158        MISCREG_MTRR_PHYS_MASK_3,
159        MISCREG_MTRR_PHYS_MASK_4,
160        MISCREG_MTRR_PHYS_MASK_5,
161        MISCREG_MTRR_PHYS_MASK_6,
162        MISCREG_MTRR_PHYS_MASK_7,
163
164        MISCREG_MTRR_FIX_64K_00000,
165        MISCREG_MTRR_FIX_16K_80000,
166        MISCREG_MTRR_FIX_16K_A0000,
167        MISCREG_MTRR_FIX_4K_C0000,
168        MISCREG_MTRR_FIX_4K_C8000,
169        MISCREG_MTRR_FIX_4K_D0000,
170        MISCREG_MTRR_FIX_4K_D8000,
171        MISCREG_MTRR_FIX_4K_E0000,
172        MISCREG_MTRR_FIX_4K_E8000,
173        MISCREG_MTRR_FIX_4K_F0000,
174        MISCREG_MTRR_FIX_4K_F8000,
175
176        MISCREG_PAT,
177
178        MISCREG_DEF_TYPE,
179
180        MISCREG_MC_CTL_BASE,
181        MISCREG_MC0_CTL = MISCREG_MC_CTL_BASE,
182        MISCREG_MC1_CTL,
183        MISCREG_MC2_CTL,
184        MISCREG_MC3_CTL,
185        MISCREG_MC4_CTL,
186
187        MISCREG_MC_STATUS_BASE,
188        MISCREG_MC0_STATUS = MISCREG_MC_STATUS_BASE,
189        MISCREG_MC1_STATUS,
190        MISCREG_MC2_STATUS,
191        MISCREG_MC3_STATUS,
192        MISCREG_MC4_STATUS,
193
194        MISCREG_MC_ADDR_BASE,
195        MISCREG_MC0_ADDR = MISCREG_MC_ADDR_BASE,
196        MISCREG_MC1_ADDR,
197        MISCREG_MC2_ADDR,
198        MISCREG_MC3_ADDR,
199        MISCREG_MC4_ADDR,
200
201        MISCREG_MC_MISC_BASE,
202        MISCREG_MC0_MISC = MISCREG_MC_MISC_BASE,
203        MISCREG_MC1_MISC,
204        MISCREG_MC2_MISC,
205        MISCREG_MC3_MISC,
206        MISCREG_MC4_MISC,
207
208        // Extended feature enable register
209        MISCREG_EFER,
210
211        MISCREG_STAR,
212        MISCREG_LSTAR,
213        MISCREG_CSTAR,
214
215        MISCREG_SF_MASK,
216
217        MISCREG_KERNEL_GS_BASE,
218
219        MISCREG_TSC_AUX,
220
221        MISCREG_PERF_EVT_SEL_BASE,
222        MISCREG_PERF_EVT_SEL0 = MISCREG_PERF_EVT_SEL_BASE,
223        MISCREG_PERF_EVT_SEL1,
224        MISCREG_PERF_EVT_SEL2,
225        MISCREG_PERF_EVT_SEL3,
226
227        MISCREG_PERF_EVT_CTR_BASE,
228        MISCREG_PERF_EVT_CTR0 = MISCREG_PERF_EVT_CTR_BASE,
229        MISCREG_PERF_EVT_CTR1,
230        MISCREG_PERF_EVT_CTR2,
231        MISCREG_PERF_EVT_CTR3,
232
233        MISCREG_SYSCFG,
234
235        MISCREG_IORR_BASE_BASE,
236        MISCREG_IORR_BASE0 = MISCREG_IORR_BASE_BASE,
237        MISCREG_IORR_BASE1,
238
239        MISCREG_IORR_MASK_BASE,
240        MISCREG_IORR_MASK0 = MISCREG_IORR_MASK_BASE,
241        MISCREG_IORR_MASK1,
242
243        MISCREG_TOP_MEM,
244        MISCREG_TOP_MEM2,
245
246        MISCREG_VM_CR,
247        MISCREG_IGNNE,
248        MISCREG_SMM_CTL,
249        MISCREG_VM_HSAVE_PA,
250
251        /*
252         * Segment registers
253         */
254        // Segment selectors
255        MISCREG_SEG_SEL_BASE,
256        MISCREG_ES = MISCREG_SEG_SEL_BASE,
257        MISCREG_CS,
258        MISCREG_SS,
259        MISCREG_DS,
260        MISCREG_FS,
261        MISCREG_GS,
262        MISCREG_HS,
263        MISCREG_TSL,
264        MISCREG_TSG,
265        MISCREG_LS,
266        MISCREG_MS,
267        MISCREG_TR,
268        MISCREG_IDTR,
269
270        // Hidden segment base field
271        MISCREG_SEG_BASE_BASE = MISCREG_SEG_SEL_BASE + NUM_SEGMENTREGS,
272        MISCREG_ES_BASE = MISCREG_SEG_BASE_BASE,
273        MISCREG_CS_BASE,
274        MISCREG_SS_BASE,
275        MISCREG_DS_BASE,
276        MISCREG_FS_BASE,
277        MISCREG_GS_BASE,
278        MISCREG_HS_BASE,
279        MISCREG_TSL_BASE,
280        MISCREG_TSG_BASE,
281        MISCREG_LS_BASE,
282        MISCREG_MS_BASE,
283        MISCREG_TR_BASE,
284        MISCREG_IDTR_BASE,
285
286        // The effective segment base, ie what is actually added to an
287        // address. In 64 bit mode this can be different from the above,
288        // namely 0.
289        MISCREG_SEG_EFF_BASE_BASE = MISCREG_SEG_BASE_BASE + NUM_SEGMENTREGS,
290        MISCREG_ES_EFF_BASE = MISCREG_SEG_EFF_BASE_BASE,
291        MISCREG_CS_EFF_BASE,
292        MISCREG_SS_EFF_BASE,
293        MISCREG_DS_EFF_BASE,
294        MISCREG_FS_EFF_BASE,
295        MISCREG_GS_EFF_BASE,
296        MISCREG_HS_EFF_BASE,
297        MISCREG_TSL_EFF_BASE,
298        MISCREG_TSG_EFF_BASE,
299        MISCREG_LS_EFF_BASE,
300        MISCREG_MS_EFF_BASE,
301        MISCREG_TR_EFF_BASE,
302        MISCREG_IDTR_EFF_BASE,
303
304        // Hidden segment limit field
305        MISCREG_SEG_LIMIT_BASE = MISCREG_SEG_EFF_BASE_BASE + NUM_SEGMENTREGS,
306        MISCREG_ES_LIMIT = MISCREG_SEG_LIMIT_BASE,
307        MISCREG_CS_LIMIT,
308        MISCREG_SS_LIMIT,
309        MISCREG_DS_LIMIT,
310        MISCREG_FS_LIMIT,
311        MISCREG_GS_LIMIT,
312        MISCREG_HS_LIMIT,
313        MISCREG_TSL_LIMIT,
314        MISCREG_TSG_LIMIT,
315        MISCREG_LS_LIMIT,
316        MISCREG_MS_LIMIT,
317        MISCREG_TR_LIMIT,
318        MISCREG_IDTR_LIMIT,
319
320        // Hidden segment limit attributes
321        MISCREG_SEG_ATTR_BASE = MISCREG_SEG_LIMIT_BASE + NUM_SEGMENTREGS,
322        MISCREG_ES_ATTR = MISCREG_SEG_ATTR_BASE,
323        MISCREG_CS_ATTR,
324        MISCREG_SS_ATTR,
325        MISCREG_DS_ATTR,
326        MISCREG_FS_ATTR,
327        MISCREG_GS_ATTR,
328        MISCREG_HS_ATTR,
329        MISCREG_TSL_ATTR,
330        MISCREG_TSG_ATTR,
331        MISCREG_LS_ATTR,
332        MISCREG_MS_ATTR,
333        MISCREG_TR_ATTR,
334        MISCREG_IDTR_ATTR,
335
336        // Floating point control registers
337        MISCREG_X87_TOP =
338            MISCREG_SEG_ATTR_BASE + NUM_SEGMENTREGS,
339
340        //XXX Add "Model-Specific Registers"
341
342        MISCREG_APIC_BASE,
343
344        MISCREG_APIC_START,
345        MISCREG_APIC_ID = MISCREG_APIC_START,
346        MISCREG_APIC_VERSION,
347        MISCREG_APIC_TASK_PRIORITY,
348        MISCREG_APIC_ARBITRATION_PRIORITY,
349        MISCREG_APIC_PROCESSOR_PRIORITY,
350        MISCREG_APIC_EOI,
351        MISCREG_APIC_LOGICAL_DESTINATION,
352        MISCREG_APIC_DESTINATION_FORMAT,
353        MISCREG_APIC_SPURIOUS_INTERRUPT_VECTOR,
354
355        MISCREG_APIC_IN_SERVICE_BASE,
356
357        MISCREG_APIC_TRIGGER_MODE_BASE = MISCREG_APIC_IN_SERVICE_BASE + 16,
358
359        MISCREG_APIC_INTERRUPT_REQUEST_BASE =
360            MISCREG_APIC_TRIGGER_MODE_BASE + 16,
361
362        MISCREG_APIC_ERROR_STATUS = MISCREG_APIC_INTERRUPT_REQUEST_BASE + 16,
363        MISCREG_APIC_INTERRUPT_COMMAND_LOW,
364        MISCREG_APIC_INTERRUPT_COMMAND_HIGH,
365        MISCREG_APIC_LVT_TIMER,
366        MISCREG_APIC_LVT_THERMAL_SENSOR,
367        MISCREG_APIC_LVT_PERFORMANCE_MONITORING_COUNTERS,
368        MISCREG_APIC_LVT_LINT0,
369        MISCREG_APIC_LVT_LINT1,
370        MISCREG_APIC_LVT_ERROR,
371        MISCREG_APIC_INITIAL_COUNT,
372        MISCREG_APIC_CURRENT_COUNT,
373        MISCREG_APIC_DIVIDE_COUNT,
374        MISCREG_APIC_END = MISCREG_APIC_DIVIDE_COUNT,
375
376        // "Fake" MSRs for internally implemented devices
377        MISCREG_PCI_CONFIG_ADDRESS,
378
379        NUM_MISCREGS
380    };
381
382    static inline MiscRegIndex
383    MISCREG_CR(int index)
384    {
385        return (MiscRegIndex)(MISCREG_CR_BASE + index);
386    }
387
388    static inline MiscRegIndex
389    MISCREG_DR(int index)
390    {
391        return (MiscRegIndex)(MISCREG_DR_BASE + index);
392    }
393
394    static inline MiscRegIndex
395    MISCREG_MTRR_PHYS_BASE(int index)
396    {
397        return (MiscRegIndex)(MISCREG_MTRR_PHYS_BASE_BASE + index);
398    }
399
400    static inline MiscRegIndex
401    MISCREG_MTRR_PHYS_MASK(int index)
402    {
403        return (MiscRegIndex)(MISCREG_MTRR_PHYS_MASK_BASE + index);
404    }
405
406    static inline MiscRegIndex
407    MISCREG_MC_CTL(int index)
408    {
409        return (MiscRegIndex)(MISCREG_MC_CTL_BASE + index);
410    }
411
412    static inline MiscRegIndex
413    MISCREG_MC_STATUS(int index)
414    {
415        return (MiscRegIndex)(MISCREG_MC_STATUS_BASE + index);
416    }
417
418    static inline MiscRegIndex
419    MISCREG_MC_ADDR(int index)
420    {
421        return (MiscRegIndex)(MISCREG_MC_ADDR_BASE + index);
422    }
423
424    static inline MiscRegIndex
425    MISCREG_MC_MISC(int index)
426    {
427        return (MiscRegIndex)(MISCREG_MC_MISC_BASE + index);
428    }
429
430    static inline MiscRegIndex
431    MISCREG_PERF_EVT_SEL(int index)
432    {
433        return (MiscRegIndex)(MISCREG_PERF_EVT_SEL_BASE + index);
434    }
435
436    static inline MiscRegIndex
437    MISCREG_PERF_EVT_CTR(int index)
438    {
439        return (MiscRegIndex)(MISCREG_PERF_EVT_CTR_BASE + index);
440    }
441
442    static inline MiscRegIndex
443    MISCREG_IORR_BASE(int index)
444    {
445        return (MiscRegIndex)(MISCREG_IORR_BASE_BASE + index);
446    }
447
448    static inline MiscRegIndex
449    MISCREG_IORR_MASK(int index)
450    {
451        return (MiscRegIndex)(MISCREG_IORR_MASK_BASE + index);
452    }
453
454    static inline MiscRegIndex
455    MISCREG_SEG_SEL(int index)
456    {
457        return (MiscRegIndex)(MISCREG_SEG_SEL_BASE + index);
458    }
459
460    static inline MiscRegIndex
461    MISCREG_SEG_BASE(int index)
462    {
463        return (MiscRegIndex)(MISCREG_SEG_BASE_BASE + index);
464    }
465
466    static inline MiscRegIndex
467    MISCREG_SEG_EFF_BASE(int index)
468    {
469        return (MiscRegIndex)(MISCREG_SEG_EFF_BASE_BASE + index);
470    }
471
472    static inline MiscRegIndex
473    MISCREG_SEG_LIMIT(int index)
474    {
475        return (MiscRegIndex)(MISCREG_SEG_LIMIT_BASE + index);
476    }
477
478    static inline MiscRegIndex
479    MISCREG_SEG_ATTR(int index)
480    {
481        return (MiscRegIndex)(MISCREG_SEG_ATTR_BASE + index);
482    }
483
484    static inline MiscRegIndex
485    MISCREG_APIC_IN_SERVICE(int index)
486    {
487        return (MiscRegIndex)(MISCREG_APIC_IN_SERVICE_BASE + index);
488    }
489
490    static inline MiscRegIndex
491    MISCREG_APIC_TRIGGER_MODE(int index)
492    {
493        return (MiscRegIndex)(MISCREG_APIC_TRIGGER_MODE_BASE + index);
494    }
495
496    static inline MiscRegIndex
497    MISCREG_APIC_INTERRUPT_REQUEST(int index)
498    {
499        return (MiscRegIndex)(MISCREG_APIC_INTERRUPT_REQUEST_BASE + index);
500    }
501
502    /**
503     * A type to describe the condition code bits of the RFLAGS register,
504     * plus two flags, EZF and ECF, which are only visible to microcode.
505     */
506    BitUnion64(CCFlagBits)
507        Bitfield<11> of;
508        Bitfield<7> sf;
509        Bitfield<6> zf;
510        Bitfield<5> ezf;
511        Bitfield<4> af;
512        Bitfield<3> ecf;
513        Bitfield<2> pf;
514        Bitfield<0> cf;
515    EndBitUnion(CCFlagBits)
516
517    /**
518     * RFLAGS
519     */
520    BitUnion64(RFLAGS)
521        Bitfield<21> id; // ID Flag
522        Bitfield<20> vip; // Virtual Interrupt Pending
523        Bitfield<19> vif; // Virtual Interrupt Flag
524        Bitfield<18> ac; // Alignment Check
525        Bitfield<17> vm; // Virtual-8086 Mode
526        Bitfield<16> rf; // Resume Flag
527        Bitfield<14> nt; // Nested Task
528        Bitfield<13, 12> iopl; // I/O Privilege Level
529        Bitfield<11> of; // Overflow Flag
530        Bitfield<10> df; // Direction Flag
531        Bitfield<9> intf; // Interrupt Flag
532        Bitfield<8> tf; // Trap Flag
533        Bitfield<7> sf; // Sign Flag
534        Bitfield<6> zf; // Zero Flag
535        Bitfield<4> af; // Auxiliary Flag
536        Bitfield<2> pf; // Parity Flag
537        Bitfield<0> cf; // Carry Flag
538    EndBitUnion(RFLAGS)
539
540    /**
541     * Control registers
542     */
543    BitUnion64(CR0)
544        Bitfield<31> pg; // Paging
545        Bitfield<30> cd; // Cache Disable
546        Bitfield<29> nw; // Not Writethrough
547        Bitfield<18> am; // Alignment Mask
548        Bitfield<16> wp; // Write Protect
549        Bitfield<5> ne; // Numeric Error
550        Bitfield<4> et; // Extension Type
551        Bitfield<3> ts; // Task Switched
552        Bitfield<2> em; // Emulation
553        Bitfield<1> mp; // Monitor Coprocessor
554        Bitfield<0> pe; // Protection Enabled
555    EndBitUnion(CR0)
556
557    // Page Fault Virtual Address
558    BitUnion64(CR2)
559        Bitfield<31, 0> legacy;
560    EndBitUnion(CR2)
561
562    BitUnion64(CR3)
563        Bitfield<51, 12> longPdtb; // Long Mode Page-Directory-Table
564                                   // Base Address
565        Bitfield<31, 12> pdtb; // Non-PAE Addressing Page-Directory-Table
566                               // Base Address
567        Bitfield<31, 5> paePdtb; // PAE Addressing Page-Directory-Table
568                                 // Base Address
569        Bitfield<4> pcd; // Page-Level Cache Disable
570        Bitfield<3> pwt; // Page-Level Writethrough
571    EndBitUnion(CR3)
572
573    BitUnion64(CR4)
574        Bitfield<10> osxmmexcpt; // Operating System Unmasked
575                                 // Exception Support
576        Bitfield<9> osfxsr; // Operating System FXSave/FSRSTOR Support
577        Bitfield<8> pce; // Performance-Monitoring Counter Enable
578        Bitfield<7> pge; // Page-Global Enable
579        Bitfield<6> mce; // Machine Check Enable
580        Bitfield<5> pae; // Physical-Address Extension
581        Bitfield<4> pse; // Page Size Extensions
582        Bitfield<3> de; // Debugging Extensions
583        Bitfield<2> tsd; // Time Stamp Disable
584        Bitfield<1> pvi; // Protected-Mode Virtual Interrupts
585        Bitfield<0> vme; // Virtual-8086 Mode Extensions
586    EndBitUnion(CR4)
587
588    BitUnion64(CR8)
589        Bitfield<3, 0> tpr; // Task Priority Register
590    EndBitUnion(CR8)
591
592    // MTRR capabilities
593    BitUnion64(MTRRcap)
594        Bitfield<7, 0> vcnt; // Variable-Range Register Count
595        Bitfield<8> fix; // Fixed-Range Registers
596        Bitfield<10> wc; // Write-Combining
597    EndBitUnion(MTRRcap)
598
599    /**
600     * SYSENTER configuration registers
601     */
602    BitUnion64(SysenterCS)
603        Bitfield<15, 0> targetCS;
604    EndBitUnion(SysenterCS)
605
606    BitUnion64(SysenterESP)
607        Bitfield<31, 0> targetESP;
608    EndBitUnion(SysenterESP)
609
610    BitUnion64(SysenterEIP)
611        Bitfield<31, 0> targetEIP;
612    EndBitUnion(SysenterEIP)
613
614    /**
615     * Global machine check registers
616     */
617    BitUnion64(McgCap)
618        Bitfield<7, 0> count; // Number of error reporting register banks
619        Bitfield<8> MCGCP; // MCG_CTL register present.
620    EndBitUnion(McgCap)
621
622    BitUnion64(McgStatus)
623        Bitfield<0> ripv; // Restart-IP valid
624        Bitfield<1> eipv; // Error-IP valid
625        Bitfield<2> mcip; // Machine check in-progress
626    EndBitUnion(McgStatus)
627
628    BitUnion64(DebugCtlMsr)
629        Bitfield<0> lbr; // Last-branch record
630        Bitfield<1> btf; // Branch single step
631        Bitfield<2> pb0; // Performance monitoring pin control 0
632        Bitfield<3> pb1; // Performance monitoring pin control 1
633        Bitfield<4> pb2; // Performance monitoring pin control 2
634        Bitfield<5> pb3; // Performance monitoring pin control 3
635        /*uint64_t pb(int index)
636        {
637            return bits(__data, index + 2);
638        }*/
639    EndBitUnion(DebugCtlMsr)
640
641    BitUnion64(MtrrPhysBase)
642        Bitfield<7, 0> type; // Default memory type
643        Bitfield<51, 12> physbase; // Range physical base address
644    EndBitUnion(MtrrPhysBase)
645
646    BitUnion64(MtrrPhysMask)
647        Bitfield<11> valid; // MTRR pair enable
648        Bitfield<51, 12> physmask; // Range physical mask
649    EndBitUnion(MtrrPhysMask)
650
651    BitUnion64(MtrrFixed)
652        /*uint64_t type(int index)
653        {
654            return bits(__data, index * 8 + 7, index * 8);
655        }*/
656    EndBitUnion(MtrrFixed)
657
658    BitUnion64(Pat)
659        /*uint64_t pa(int index)
660        {
661            return bits(__data, index * 8 + 2, index * 8);
662        }*/
663    EndBitUnion(Pat)
664
665    BitUnion64(MtrrDefType)
666        Bitfield<7, 0> type; // Default type
667        Bitfield<10> fe; // Fixed range enable
668        Bitfield<11> e; // MTRR enable
669    EndBitUnion(MtrrDefType)
670
671    /**
672     * Machine check
673     */
674    BitUnion64(McStatus)
675        Bitfield<15,0> mcaErrorCode;
676        Bitfield<31,16> modelSpecificCode;
677        Bitfield<56,32> otherInfo;
678        Bitfield<57> pcc; // Processor-context corrupt
679        Bitfield<58> addrv; // Error-address register valid
680        Bitfield<59> miscv; // Miscellaneous-error register valid
681        Bitfield<60> en; // Error condition enabled
682        Bitfield<61> uc; // Uncorrected error
683        Bitfield<62> over; // Status register overflow
684        Bitfield<63> val; // Valid
685    EndBitUnion(McStatus)
686
687    BitUnion64(McCtl)
688        /*uint64_t en(int index)
689        {
690            return bits(__data, index);
691        }*/
692    EndBitUnion(McCtl)
693
694    // Extended feature enable register
695    BitUnion64(Efer)
696        Bitfield<0> sce; // System call extensions
697        Bitfield<8> lme; // Long mode enable
698        Bitfield<10> lma; // Long mode active
699        Bitfield<11> nxe; // No-execute enable
700        Bitfield<12> svme; // Secure virtual machine enable
701        Bitfield<14> ffxsr; // Fast fxsave/fxrstor
702    EndBitUnion(Efer)
703
704    BitUnion64(Star)
705        Bitfield<31,0> targetEip;
706        Bitfield<47,32> syscallCsAndSs;
707        Bitfield<63,48> sysretCsAndSs;
708    EndBitUnion(Star)
709
710    BitUnion64(SfMask)
711        Bitfield<31,0> mask;
712    EndBitUnion(SfMask)
713
714    BitUnion64(PerfEvtSel)
715        Bitfield<7,0> eventMask;
716        Bitfield<15,8> unitMask;
717        Bitfield<16> usr; // User mode
718        Bitfield<17> os; // Operating-system mode
719        Bitfield<18> e; // Edge detect
720        Bitfield<19> pc; // Pin control
721        Bitfield<20> intEn; // Interrupt enable
722        Bitfield<22> en; // Counter enable
723        Bitfield<23> inv; // Invert mask
724        Bitfield<31,24> counterMask;
725    EndBitUnion(PerfEvtSel)
726
727    BitUnion32(Syscfg)
728        Bitfield<18> mfde; // MtrrFixDramEn
729        Bitfield<19> mfdm; // MtrrFixDramModEn
730        Bitfield<20> mvdm; // MtrrVarDramEn
731        Bitfield<21> tom2; // MtrrTom2En
732    EndBitUnion(Syscfg)
733
734    BitUnion64(IorrBase)
735        Bitfield<3> wr; // WrMem Enable
736        Bitfield<4> rd; // RdMem Enable
737        Bitfield<51,12> physbase; // Range physical base address
738    EndBitUnion(IorrBase)
739
740    BitUnion64(IorrMask)
741        Bitfield<11> v; // I/O register pair enable (valid)
742        Bitfield<51,12> physmask; // Range physical mask
743    EndBitUnion(IorrMask)
744
745    BitUnion64(Tom)
746        Bitfield<51,23> physAddr; // Top of memory physical address
747    EndBitUnion(Tom)
748
749    BitUnion64(VmCrMsr)
750        Bitfield<0> dpd;
751        Bitfield<1> rInit;
752        Bitfield<2> disA20M;
753    EndBitUnion(VmCrMsr)
754
755    BitUnion64(IgnneMsr)
756        Bitfield<0> ignne;
757    EndBitUnion(IgnneMsr)
758
759    BitUnion64(SmmCtlMsr)
760        Bitfield<0> dismiss;
761        Bitfield<1> enter;
762        Bitfield<2> smiCycle;
763        Bitfield<3> exit;
764        Bitfield<4> rsmCycle;
765    EndBitUnion(SmmCtlMsr)
766
767    /**
768     * Segment Selector
769     */
770    BitUnion64(SegSelector)
771        // The following bitfield is not defined in the ISA, but it's useful
772        // when checking selectors in larger data types to make sure they
773        // aren't too large.
774        Bitfield<63, 3> esi; // Extended selector
775        Bitfield<15, 3> si; // Selector Index
776        Bitfield<2> ti; // Table Indicator
777        Bitfield<1, 0> rpl; // Requestor Privilege Level
778    EndBitUnion(SegSelector)
779
780    /**
781     * Segment Descriptors
782     */
783
784    BitUnion64(SegDescriptor)
785        Bitfield<63, 56> baseHigh;
786        Bitfield<39, 16> baseLow;
787        Bitfield<55> g; // Granularity
788        Bitfield<54> d; // Default Operand Size
789        Bitfield<54> b; // Default Operand Size
790        Bitfield<53> l; // Long Attribute Bit
791        Bitfield<52> avl; // Available To Software
792        Bitfield<51, 48> limitHigh;
793        Bitfield<15, 0> limitLow;
794        Bitfield<47> p; // Present
795        Bitfield<46, 45> dpl; // Descriptor Privilege-Level
796        Bitfield<44> s; // System
797        SubBitUnion(type, 43, 40)
798            // Specifies whether this descriptor is for code or data.
799            Bitfield<43> codeOrData;
800
801            // These bit fields are for code segments
802            Bitfield<42> c; // Conforming
803            Bitfield<41> r; // Readable
804
805            // These bit fields are for data segments
806            Bitfield<42> e; // Expand-Down
807            Bitfield<41> w; // Writable
808
809            // This is used for both code and data segments.
810            Bitfield<40> a; // Accessed
811        EndSubBitUnion(type)
812    EndBitUnion(SegDescriptor)
813
814    BitUnion64(SegAttr)
815        Bitfield<0> writable;
816        Bitfield<1> readable;
817        Bitfield<2> expandDown;
818        Bitfield<4, 3> dpl;
819        Bitfield<5> defaultSize;
820        Bitfield<6> longMode;
821    EndBitUnion(SegAttr)
822
823    BitUnion64(GateDescriptor)
824        Bitfield<63, 48> offsetHigh; // Target Code-Segment Offset
825        Bitfield<15, 0> offsetLow; // Target Code-Segment Offset
826        Bitfield<31, 16> selector; // Target Code-Segment Selector
827        Bitfield<47> p; // Present
828        Bitfield<46, 45> dpl; // Descriptor Privilege-Level
829        Bitfield<43, 40> type;
830        Bitfield<36, 32> count; // Parameter Count
831    EndBitUnion(GateDescriptor)
832
833    /**
834     * Descriptor-Table Registers
835     */
836    BitUnion64(GDTR)
837    EndBitUnion(GDTR)
838
839    BitUnion64(IDTR)
840    EndBitUnion(IDTR)
841
842    BitUnion64(LDTR)
843    EndBitUnion(LDTR)
844
845    /**
846     * Task Register
847     */
848    BitUnion64(TR)
849    EndBitUnion(TR)
850
851
852    /**
853     * Local APIC Base Register
854     */
855    BitUnion64(LocalApicBase)
856        Bitfield<51, 12> base;
857        Bitfield<11> enable;
858        Bitfield<8> bsp;
859    EndBitUnion(LocalApicBase)
860};
861
862#endif // __ARCH_X86_INTREGS_HH__
863