process.cc revision 12457:b9b7bdb5a8ac
1/* 2 * Copyright (c) 2014 Advanced Micro Devices, Inc. 3 * Copyright (c) 2007 The Hewlett-Packard Development Company 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated 12 * unmodified and in its entirety in all distributions of the software, 13 * modified or unmodified, in source code or in binary form. 14 * 15 * Copyright (c) 2003-2006 The Regents of The University of Michigan 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Gabe Black 42 * Ali Saidi 43 */ 44 45#include "arch/x86/process.hh" 46 47#include <string> 48#include <vector> 49 50#include "arch/x86/isa_traits.hh" 51#include "arch/x86/regs/misc.hh" 52#include "arch/x86/regs/segment.hh" 53#include "arch/x86/system.hh" 54#include "arch/x86/types.hh" 55#include "base/loader/elf_object.hh" 56#include "base/loader/object_file.hh" 57#include "base/logging.hh" 58#include "base/trace.hh" 59#include "cpu/thread_context.hh" 60#include "debug/Stack.hh" 61#include "mem/multi_level_page_table.hh" 62#include "mem/page_table.hh" 63#include "params/Process.hh" 64#include "sim/aux_vector.hh" 65#include "sim/process_impl.hh" 66#include "sim/syscall_desc.hh" 67#include "sim/syscall_return.hh" 68#include "sim/system.hh" 69 70using namespace std; 71using namespace X86ISA; 72 73static const int ArgumentReg[] = { 74 INTREG_RDI, 75 INTREG_RSI, 76 INTREG_RDX, 77 // This argument register is r10 for syscalls and rcx for C. 78 INTREG_R10W, 79 // INTREG_RCX, 80 INTREG_R8W, 81 INTREG_R9W 82}; 83 84static const int NumArgumentRegs M5_VAR_USED = 85 sizeof(ArgumentReg) / sizeof(const int); 86 87static const int ArgumentReg32[] = { 88 INTREG_EBX, 89 INTREG_ECX, 90 INTREG_EDX, 91 INTREG_ESI, 92 INTREG_EDI, 93 INTREG_EBP 94}; 95 96static const int NumArgumentRegs32 M5_VAR_USED = 97 sizeof(ArgumentReg) / sizeof(const int); 98 99X86Process::X86Process(ProcessParams *params, ObjectFile *objFile, 100 SyscallDesc *_syscallDescs, int _numSyscallDescs) 101 : Process(params, params->useArchPT ? 102 static_cast<EmulationPageTable *>( 103 new ArchPageTable( 104 params->name, params->pid, 105 params->system, PageBytes, 106 PageTableLayout, 107 pageTablePhysAddr >> PageShift)) : 108 new EmulationPageTable(params->name, params->pid, 109 PageBytes), 110 objFile), 111 syscallDescs(_syscallDescs), numSyscallDescs(_numSyscallDescs) 112{ 113} 114 115void X86Process::clone(ThreadContext *old_tc, ThreadContext *new_tc, 116 Process *p, TheISA::IntReg flags) 117{ 118 Process::clone(old_tc, new_tc, p, flags); 119 X86Process *process = (X86Process*)p; 120 *process = *this; 121} 122 123X86_64Process::X86_64Process(ProcessParams *params, ObjectFile *objFile, 124 SyscallDesc *_syscallDescs, int _numSyscallDescs) 125 : X86Process(params, objFile, _syscallDescs, _numSyscallDescs) 126{ 127 128 vsyscallPage.base = 0xffffffffff600000ULL; 129 vsyscallPage.size = PageBytes; 130 vsyscallPage.vtimeOffset = 0x400; 131 vsyscallPage.vgettimeofdayOffset = 0x0; 132 133 Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() + 134 objFile->bssSize(), PageBytes); 135 Addr stack_base = 0x7FFFFFFFF000ULL; 136 Addr max_stack_size = 8 * 1024 * 1024; 137 Addr next_thread_stack_base = stack_base - max_stack_size; 138 Addr mmap_end = 0x7FFFF7FFF000ULL; 139 140 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size, 141 next_thread_stack_base, mmap_end); 142} 143 144void 145I386Process::syscall(int64_t callnum, ThreadContext *tc, Fault *fault) 146{ 147 TheISA::PCState pc = tc->pcState(); 148 Addr eip = pc.pc(); 149 if (eip >= vsyscallPage.base && 150 eip < vsyscallPage.base + vsyscallPage.size) { 151 pc.npc(vsyscallPage.base + vsyscallPage.vsysexitOffset); 152 tc->pcState(pc); 153 } 154 X86Process::syscall(callnum, tc, fault); 155} 156 157 158I386Process::I386Process(ProcessParams *params, ObjectFile *objFile, 159 SyscallDesc *_syscallDescs, int _numSyscallDescs) 160 : X86Process(params, objFile, _syscallDescs, _numSyscallDescs) 161{ 162 _gdtStart = ULL(0xffffd000); 163 _gdtSize = PageBytes; 164 165 vsyscallPage.base = 0xffffe000ULL; 166 vsyscallPage.size = PageBytes; 167 vsyscallPage.vsyscallOffset = 0x400; 168 vsyscallPage.vsysexitOffset = 0x410; 169 170 Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() + 171 objFile->bssSize(), PageBytes); 172 Addr stack_base = _gdtStart; 173 Addr max_stack_size = 8 * 1024 * 1024; 174 Addr next_thread_stack_base = stack_base - max_stack_size; 175 Addr mmap_end = 0xB7FFF000ULL; 176 177 memState = make_shared<MemState>(brk_point, stack_base, max_stack_size, 178 next_thread_stack_base, mmap_end); 179} 180 181SyscallDesc* 182X86Process::getDesc(int callnum) 183{ 184 if (callnum < 0 || callnum >= numSyscallDescs) 185 return NULL; 186 return &syscallDescs[callnum]; 187} 188 189void 190X86_64Process::initState() 191{ 192 X86Process::initState(); 193 194 argsInit(PageBytes); 195 196 // Set up the vsyscall page for this process. 197 allocateMem(vsyscallPage.base, vsyscallPage.size); 198 uint8_t vtimeBlob[] = { 199 0x48,0xc7,0xc0,0xc9,0x00,0x00,0x00, // mov $0xc9,%rax 200 0x0f,0x05, // syscall 201 0xc3 // retq 202 }; 203 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vtimeOffset, 204 vtimeBlob, sizeof(vtimeBlob)); 205 206 uint8_t vgettimeofdayBlob[] = { 207 0x48,0xc7,0xc0,0x60,0x00,0x00,0x00, // mov $0x60,%rax 208 0x0f,0x05, // syscall 209 0xc3 // retq 210 }; 211 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vgettimeofdayOffset, 212 vgettimeofdayBlob, sizeof(vgettimeofdayBlob)); 213 214 if (kvmInSE) { 215 PortProxy physProxy = system->physProxy; 216 217 /* 218 * Set up the gdt. 219 */ 220 uint8_t numGDTEntries = 0; 221 uint64_t nullDescriptor = 0; 222 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8, 223 (uint8_t *)(&nullDescriptor), 8); 224 numGDTEntries++; 225 226 SegDescriptor initDesc = 0; 227 initDesc.type.codeOrData = 0; // code or data type 228 initDesc.type.c = 0; // conforming 229 initDesc.type.r = 1; // readable 230 initDesc.dpl = 0; // privilege 231 initDesc.p = 1; // present 232 initDesc.l = 1; // longmode - 64 bit 233 initDesc.d = 0; // operand size 234 initDesc.g = 1; // granularity 235 initDesc.s = 1; // system segment 236 initDesc.limitHigh = 0xFFFF; 237 initDesc.limitLow = 0xF; 238 initDesc.baseHigh = 0x0; 239 initDesc.baseLow = 0x0; 240 241 //64 bit code segment 242 SegDescriptor csLowPLDesc = initDesc; 243 csLowPLDesc.type.codeOrData = 1; 244 csLowPLDesc.dpl = 0; 245 uint64_t csLowPLDescVal = csLowPLDesc; 246 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8, 247 (uint8_t *)(&csLowPLDescVal), 8); 248 249 numGDTEntries++; 250 251 SegSelector csLowPL = 0; 252 csLowPL.si = numGDTEntries - 1; 253 csLowPL.rpl = 0; 254 255 //64 bit data segment 256 SegDescriptor dsLowPLDesc = initDesc; 257 dsLowPLDesc.type.codeOrData = 0; 258 dsLowPLDesc.dpl = 0; 259 uint64_t dsLowPLDescVal = dsLowPLDesc; 260 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8, 261 (uint8_t *)(&dsLowPLDescVal), 8); 262 263 numGDTEntries++; 264 265 SegSelector dsLowPL = 0; 266 dsLowPL.si = numGDTEntries - 1; 267 dsLowPL.rpl = 0; 268 269 //64 bit data segment 270 SegDescriptor dsDesc = initDesc; 271 dsDesc.type.codeOrData = 0; 272 dsDesc.dpl = 3; 273 uint64_t dsDescVal = dsDesc; 274 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8, 275 (uint8_t *)(&dsDescVal), 8); 276 277 numGDTEntries++; 278 279 SegSelector ds = 0; 280 ds.si = numGDTEntries - 1; 281 ds.rpl = 3; 282 283 //64 bit code segment 284 SegDescriptor csDesc = initDesc; 285 csDesc.type.codeOrData = 1; 286 csDesc.dpl = 3; 287 uint64_t csDescVal = csDesc; 288 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8, 289 (uint8_t *)(&csDescVal), 8); 290 291 numGDTEntries++; 292 293 SegSelector cs = 0; 294 cs.si = numGDTEntries - 1; 295 cs.rpl = 3; 296 297 SegSelector scall = 0; 298 scall.si = csLowPL.si; 299 scall.rpl = 0; 300 301 SegSelector sret = 0; 302 sret.si = dsLowPL.si; 303 sret.rpl = 3; 304 305 /* In long mode the TSS has been extended to 16 Bytes */ 306 TSSlow TSSDescLow = 0; 307 TSSDescLow.type = 0xB; 308 TSSDescLow.dpl = 0; // Privelege level 0 309 TSSDescLow.p = 1; // Present 310 TSSDescLow.g = 1; // Page granularity 311 TSSDescLow.limitHigh = 0xF; 312 TSSDescLow.limitLow = 0xFFFF; 313 TSSDescLow.baseLow = bits(TSSVirtAddr, 23, 0); 314 TSSDescLow.baseHigh = bits(TSSVirtAddr, 31, 24); 315 316 TSShigh TSSDescHigh = 0; 317 TSSDescHigh.base = bits(TSSVirtAddr, 63, 32); 318 319 struct TSSDesc { 320 uint64_t low; 321 uint64_t high; 322 } tssDescVal = {TSSDescLow, TSSDescHigh}; 323 324 physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8, 325 (uint8_t *)(&tssDescVal), sizeof(tssDescVal)); 326 327 numGDTEntries++; 328 329 SegSelector tssSel = 0; 330 tssSel.si = numGDTEntries - 1; 331 332 uint64_t tss_base_addr = (TSSDescHigh.base << 32) | 333 (TSSDescLow.baseHigh << 24) | 334 TSSDescLow.baseLow; 335 uint64_t tss_limit = TSSDescLow.limitLow | (TSSDescLow.limitHigh << 16); 336 337 SegAttr tss_attr = 0; 338 339 tss_attr.type = TSSDescLow.type; 340 tss_attr.dpl = TSSDescLow.dpl; 341 tss_attr.present = TSSDescLow.p; 342 tss_attr.granularity = TSSDescLow.g; 343 tss_attr.unusable = 0; 344 345 for (int i = 0; i < contextIds.size(); i++) { 346 ThreadContext * tc = system->getThreadContext(contextIds[i]); 347 348 tc->setMiscReg(MISCREG_CS, cs); 349 tc->setMiscReg(MISCREG_DS, ds); 350 tc->setMiscReg(MISCREG_ES, ds); 351 tc->setMiscReg(MISCREG_FS, ds); 352 tc->setMiscReg(MISCREG_GS, ds); 353 tc->setMiscReg(MISCREG_SS, ds); 354 355 // LDT 356 tc->setMiscReg(MISCREG_TSL, 0); 357 SegAttr tslAttr = 0; 358 tslAttr.present = 1; 359 tslAttr.type = 2; 360 tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr); 361 362 tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr); 363 tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1); 364 365 tc->setMiscReg(MISCREG_TR, tssSel); 366 tc->setMiscReg(MISCREG_TR_BASE, tss_base_addr); 367 tc->setMiscReg(MISCREG_TR_EFF_BASE, 0); 368 tc->setMiscReg(MISCREG_TR_LIMIT, tss_limit); 369 tc->setMiscReg(MISCREG_TR_ATTR, tss_attr); 370 371 //Start using longmode segments. 372 installSegDesc(tc, SEGMENT_REG_CS, csDesc, true); 373 installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true); 374 installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true); 375 installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true); 376 installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true); 377 installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true); 378 379 Efer efer = 0; 380 efer.sce = 1; // Enable system call extensions. 381 efer.lme = 1; // Enable long mode. 382 efer.lma = 1; // Activate long mode. 383 efer.nxe = 0; // Enable nx support. 384 efer.svme = 1; // Enable svm support for now. 385 efer.ffxsr = 0; // Turn on fast fxsave and fxrstor. 386 tc->setMiscReg(MISCREG_EFER, efer); 387 388 //Set up the registers that describe the operating mode. 389 CR0 cr0 = 0; 390 cr0.pg = 1; // Turn on paging. 391 cr0.cd = 0; // Don't disable caching. 392 cr0.nw = 0; // This is bit is defined to be ignored. 393 cr0.am = 1; // No alignment checking 394 cr0.wp = 1; // Supervisor mode can write read only pages 395 cr0.ne = 1; 396 cr0.et = 1; // This should always be 1 397 cr0.ts = 0; // We don't do task switching, so causing fp exceptions 398 // would be pointless. 399 cr0.em = 0; // Allow x87 instructions to execute natively. 400 cr0.mp = 1; // This doesn't really matter, but the manual suggests 401 // setting it to one. 402 cr0.pe = 1; // We're definitely in protected mode. 403 tc->setMiscReg(MISCREG_CR0, cr0); 404 405 CR0 cr2 = 0; 406 tc->setMiscReg(MISCREG_CR2, cr2); 407 408 CR3 cr3 = pageTablePhysAddr; 409 tc->setMiscReg(MISCREG_CR3, cr3); 410 411 CR4 cr4 = 0; 412 //Turn on pae. 413 cr4.osxsave = 1; // Enable XSAVE and Proc Extended States 414 cr4.osxmmexcpt = 1; // Operating System Unmasked Exception 415 cr4.osfxsr = 1; // Operating System FXSave/FSRSTOR Support 416 cr4.pce = 0; // Performance-Monitoring Counter Enable 417 cr4.pge = 0; // Page-Global Enable 418 cr4.mce = 0; // Machine Check Enable 419 cr4.pae = 1; // Physical-Address Extension 420 cr4.pse = 0; // Page Size Extensions 421 cr4.de = 0; // Debugging Extensions 422 cr4.tsd = 0; // Time Stamp Disable 423 cr4.pvi = 0; // Protected-Mode Virtual Interrupts 424 cr4.vme = 0; // Virtual-8086 Mode Extensions 425 426 tc->setMiscReg(MISCREG_CR4, cr4); 427 428 CR4 cr8 = 0; 429 tc->setMiscReg(MISCREG_CR8, cr8); 430 431 const Addr PageMapLevel4 = pageTablePhysAddr; 432 //Point to the page tables. 433 tc->setMiscReg(MISCREG_CR3, PageMapLevel4); 434 435 tc->setMiscReg(MISCREG_MXCSR, 0x1f80); 436 437 tc->setMiscReg(MISCREG_APIC_BASE, 0xfee00900); 438 439 tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr); 440 tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff); 441 442 tc->setMiscReg(MISCREG_IDTR_BASE, IDTVirtAddr); 443 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff); 444 445 /* enabling syscall and sysret */ 446 MiscReg star = ((MiscReg)sret << 48) | ((MiscReg)scall << 32); 447 tc->setMiscReg(MISCREG_STAR, star); 448 MiscReg lstar = (MiscReg)syscallCodeVirtAddr; 449 tc->setMiscReg(MISCREG_LSTAR, lstar); 450 MiscReg sfmask = (1 << 8) | (1 << 10); // TF | DF 451 tc->setMiscReg(MISCREG_SF_MASK, sfmask); 452 } 453 454 /* Set up the content of the TSS and write it to physical memory. */ 455 456 struct { 457 uint32_t reserved0; // +00h 458 uint32_t RSP0_low; // +04h 459 uint32_t RSP0_high; // +08h 460 uint32_t RSP1_low; // +0Ch 461 uint32_t RSP1_high; // +10h 462 uint32_t RSP2_low; // +14h 463 uint32_t RSP2_high; // +18h 464 uint32_t reserved1; // +1Ch 465 uint32_t reserved2; // +20h 466 uint32_t IST1_low; // +24h 467 uint32_t IST1_high; // +28h 468 uint32_t IST2_low; // +2Ch 469 uint32_t IST2_high; // +30h 470 uint32_t IST3_low; // +34h 471 uint32_t IST3_high; // +38h 472 uint32_t IST4_low; // +3Ch 473 uint32_t IST4_high; // +40h 474 uint32_t IST5_low; // +44h 475 uint32_t IST5_high; // +48h 476 uint32_t IST6_low; // +4Ch 477 uint32_t IST6_high; // +50h 478 uint32_t IST7_low; // +54h 479 uint32_t IST7_high; // +58h 480 uint32_t reserved3; // +5Ch 481 uint32_t reserved4; // +60h 482 uint16_t reserved5; // +64h 483 uint16_t IO_MapBase; // +66h 484 } tss; 485 486 /** setting Interrupt Stack Table */ 487 uint64_t IST_start = ISTVirtAddr + PageBytes; 488 tss.IST1_low = IST_start; 489 tss.IST1_high = IST_start >> 32; 490 tss.RSP0_low = tss.IST1_low; 491 tss.RSP0_high = tss.IST1_high; 492 tss.RSP1_low = tss.IST1_low; 493 tss.RSP1_high = tss.IST1_high; 494 tss.RSP2_low = tss.IST1_low; 495 tss.RSP2_high = tss.IST1_high; 496 physProxy.writeBlob(TSSPhysAddr, (uint8_t *)(&tss), sizeof(tss)); 497 498 /* Setting IDT gates */ 499 GateDescriptorLow PFGateLow = 0; 500 PFGateLow.offsetHigh = bits(PFHandlerVirtAddr, 31, 16); 501 PFGateLow.offsetLow = bits(PFHandlerVirtAddr, 15, 0); 502 PFGateLow.selector = csLowPL; 503 PFGateLow.p = 1; 504 PFGateLow.dpl = 0; 505 PFGateLow.type = 0xe; // gate interrupt type 506 PFGateLow.IST = 0; // setting IST to 0 and using RSP0 507 508 GateDescriptorHigh PFGateHigh = 0; 509 PFGateHigh.offset = bits(PFHandlerVirtAddr, 63, 32); 510 511 struct { 512 uint64_t low; 513 uint64_t high; 514 } PFGate = {PFGateLow, PFGateHigh}; 515 516 physProxy.writeBlob(IDTPhysAddr + 0xE0, 517 (uint8_t *)(&PFGate), sizeof(PFGate)); 518 519 /* System call handler */ 520 uint8_t syscallBlob[] = { 521 // mov %rax, (0xffffc90000005600) 522 0x48, 0xa3, 0x00, 0x60, 0x00, 523 0x00, 0x00, 0xc9, 0xff, 0xff, 524 // sysret 525 0x48, 0x0f, 0x07 526 }; 527 528 physProxy.writeBlob(syscallCodePhysAddr, 529 syscallBlob, sizeof(syscallBlob)); 530 531 /** Page fault handler */ 532 uint8_t faultBlob[] = { 533 // mov %rax, (0xffffc90000005700) 534 0x48, 0xa3, 0x00, 0x61, 0x00, 535 0x00, 0x00, 0xc9, 0xff, 0xff, 536 // add $0x8, %rsp # skip error 537 0x48, 0x83, 0xc4, 0x08, 538 // iretq 539 0x48, 0xcf 540 }; 541 542 physProxy.writeBlob(PFHandlerPhysAddr, faultBlob, sizeof(faultBlob)); 543 544 MultiLevelPageTable<PageTableOps> *pt = 545 dynamic_cast<MultiLevelPageTable<PageTableOps> *>(pTable); 546 547 /* Syscall handler */ 548 pt->map(syscallCodeVirtAddr, syscallCodePhysAddr, PageBytes, false); 549 /* GDT */ 550 pt->map(GDTVirtAddr, GDTPhysAddr, PageBytes, false); 551 /* IDT */ 552 pt->map(IDTVirtAddr, IDTPhysAddr, PageBytes, false); 553 /* TSS */ 554 pt->map(TSSVirtAddr, TSSPhysAddr, PageBytes, false); 555 /* IST */ 556 pt->map(ISTVirtAddr, ISTPhysAddr, PageBytes, false); 557 /* PF handler */ 558 pt->map(PFHandlerVirtAddr, PFHandlerPhysAddr, PageBytes, false); 559 /* MMIO region for m5ops */ 560 pt->map(MMIORegionVirtAddr, MMIORegionPhysAddr, 16*PageBytes, false); 561 } else { 562 for (int i = 0; i < contextIds.size(); i++) { 563 ThreadContext * tc = system->getThreadContext(contextIds[i]); 564 565 SegAttr dataAttr = 0; 566 dataAttr.dpl = 3; 567 dataAttr.unusable = 0; 568 dataAttr.defaultSize = 1; 569 dataAttr.longMode = 1; 570 dataAttr.avl = 0; 571 dataAttr.granularity = 1; 572 dataAttr.present = 1; 573 dataAttr.type = 3; 574 dataAttr.writable = 1; 575 dataAttr.readable = 1; 576 dataAttr.expandDown = 0; 577 dataAttr.system = 1; 578 579 // Initialize the segment registers. 580 for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) { 581 tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0); 582 tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0); 583 tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr); 584 } 585 586 SegAttr csAttr = 0; 587 csAttr.dpl = 3; 588 csAttr.unusable = 0; 589 csAttr.defaultSize = 0; 590 csAttr.longMode = 1; 591 csAttr.avl = 0; 592 csAttr.granularity = 1; 593 csAttr.present = 1; 594 csAttr.type = 10; 595 csAttr.writable = 0; 596 csAttr.readable = 1; 597 csAttr.expandDown = 0; 598 csAttr.system = 1; 599 600 tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr); 601 602 Efer efer = 0; 603 efer.sce = 1; // Enable system call extensions. 604 efer.lme = 1; // Enable long mode. 605 efer.lma = 1; // Activate long mode. 606 efer.nxe = 1; // Enable nx support. 607 efer.svme = 0; // Disable svm support for now. It isn't implemented. 608 efer.ffxsr = 1; // Turn on fast fxsave and fxrstor. 609 tc->setMiscReg(MISCREG_EFER, efer); 610 611 // Set up the registers that describe the operating mode. 612 CR0 cr0 = 0; 613 cr0.pg = 1; // Turn on paging. 614 cr0.cd = 0; // Don't disable caching. 615 cr0.nw = 0; // This is bit is defined to be ignored. 616 cr0.am = 0; // No alignment checking 617 cr0.wp = 0; // Supervisor mode can write read only pages 618 cr0.ne = 1; 619 cr0.et = 1; // This should always be 1 620 cr0.ts = 0; // We don't do task switching, so causing fp exceptions 621 // would be pointless. 622 cr0.em = 0; // Allow x87 instructions to execute natively. 623 cr0.mp = 1; // This doesn't really matter, but the manual suggests 624 // setting it to one. 625 cr0.pe = 1; // We're definitely in protected mode. 626 tc->setMiscReg(MISCREG_CR0, cr0); 627 628 tc->setMiscReg(MISCREG_MXCSR, 0x1f80); 629 } 630 } 631} 632 633void 634I386Process::initState() 635{ 636 X86Process::initState(); 637 638 argsInit(PageBytes); 639 640 /* 641 * Set up a GDT for this process. The whole GDT wouldn't really be for 642 * this process, but the only parts we care about are. 643 */ 644 allocateMem(_gdtStart, _gdtSize); 645 uint64_t zero = 0; 646 assert(_gdtSize % sizeof(zero) == 0); 647 for (Addr gdtCurrent = _gdtStart; 648 gdtCurrent < _gdtStart + _gdtSize; gdtCurrent += sizeof(zero)) { 649 initVirtMem.write(gdtCurrent, zero); 650 } 651 652 // Set up the vsyscall page for this process. 653 allocateMem(vsyscallPage.base, vsyscallPage.size); 654 uint8_t vsyscallBlob[] = { 655 0x51, // push %ecx 656 0x52, // push %edp 657 0x55, // push %ebp 658 0x89, 0xe5, // mov %esp, %ebp 659 0x0f, 0x34 // sysenter 660 }; 661 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vsyscallOffset, 662 vsyscallBlob, sizeof(vsyscallBlob)); 663 664 uint8_t vsysexitBlob[] = { 665 0x5d, // pop %ebp 666 0x5a, // pop %edx 667 0x59, // pop %ecx 668 0xc3 // ret 669 }; 670 initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vsysexitOffset, 671 vsysexitBlob, sizeof(vsysexitBlob)); 672 673 for (int i = 0; i < contextIds.size(); i++) { 674 ThreadContext * tc = system->getThreadContext(contextIds[i]); 675 676 SegAttr dataAttr = 0; 677 dataAttr.dpl = 3; 678 dataAttr.unusable = 0; 679 dataAttr.defaultSize = 1; 680 dataAttr.longMode = 0; 681 dataAttr.avl = 0; 682 dataAttr.granularity = 1; 683 dataAttr.present = 1; 684 dataAttr.type = 3; 685 dataAttr.writable = 1; 686 dataAttr.readable = 1; 687 dataAttr.expandDown = 0; 688 dataAttr.system = 1; 689 690 // Initialize the segment registers. 691 for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) { 692 tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0); 693 tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0); 694 tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr); 695 tc->setMiscRegNoEffect(MISCREG_SEG_SEL(seg), 0xB); 696 tc->setMiscRegNoEffect(MISCREG_SEG_LIMIT(seg), (uint32_t)(-1)); 697 } 698 699 SegAttr csAttr = 0; 700 csAttr.dpl = 3; 701 csAttr.unusable = 0; 702 csAttr.defaultSize = 1; 703 csAttr.longMode = 0; 704 csAttr.avl = 0; 705 csAttr.granularity = 1; 706 csAttr.present = 1; 707 csAttr.type = 0xa; 708 csAttr.writable = 0; 709 csAttr.readable = 1; 710 csAttr.expandDown = 0; 711 csAttr.system = 1; 712 713 tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr); 714 715 tc->setMiscRegNoEffect(MISCREG_TSG_BASE, _gdtStart); 716 tc->setMiscRegNoEffect(MISCREG_TSG_EFF_BASE, _gdtStart); 717 tc->setMiscRegNoEffect(MISCREG_TSG_LIMIT, _gdtStart + _gdtSize - 1); 718 719 // Set the LDT selector to 0 to deactivate it. 720 tc->setMiscRegNoEffect(MISCREG_TSL, 0); 721 722 Efer efer = 0; 723 efer.sce = 1; // Enable system call extensions. 724 efer.lme = 1; // Enable long mode. 725 efer.lma = 0; // Deactivate long mode. 726 efer.nxe = 1; // Enable nx support. 727 efer.svme = 0; // Disable svm support for now. It isn't implemented. 728 efer.ffxsr = 1; // Turn on fast fxsave and fxrstor. 729 tc->setMiscReg(MISCREG_EFER, efer); 730 731 // Set up the registers that describe the operating mode. 732 CR0 cr0 = 0; 733 cr0.pg = 1; // Turn on paging. 734 cr0.cd = 0; // Don't disable caching. 735 cr0.nw = 0; // This is bit is defined to be ignored. 736 cr0.am = 0; // No alignment checking 737 cr0.wp = 0; // Supervisor mode can write read only pages 738 cr0.ne = 1; 739 cr0.et = 1; // This should always be 1 740 cr0.ts = 0; // We don't do task switching, so causing fp exceptions 741 // would be pointless. 742 cr0.em = 0; // Allow x87 instructions to execute natively. 743 cr0.mp = 1; // This doesn't really matter, but the manual suggests 744 // setting it to one. 745 cr0.pe = 1; // We're definitely in protected mode. 746 tc->setMiscReg(MISCREG_CR0, cr0); 747 748 tc->setMiscReg(MISCREG_MXCSR, 0x1f80); 749 } 750} 751 752template<class IntType> 753void 754X86Process::argsInit(int pageSize, 755 std::vector<AuxVector<IntType> > extraAuxvs) 756{ 757 int intSize = sizeof(IntType); 758 759 typedef AuxVector<IntType> auxv_t; 760 std::vector<auxv_t> auxv = extraAuxvs; 761 762 string filename; 763 if (argv.size() < 1) 764 filename = ""; 765 else 766 filename = argv[0]; 767 768 // We want 16 byte alignment 769 uint64_t align = 16; 770 771 // Patch the ld_bias for dynamic executables. 772 updateBias(); 773 774 // load object file into target memory 775 objFile->loadSections(initVirtMem); 776 777 enum X86CpuFeature { 778 X86_OnboardFPU = 1 << 0, 779 X86_VirtualModeExtensions = 1 << 1, 780 X86_DebuggingExtensions = 1 << 2, 781 X86_PageSizeExtensions = 1 << 3, 782 783 X86_TimeStampCounter = 1 << 4, 784 X86_ModelSpecificRegisters = 1 << 5, 785 X86_PhysicalAddressExtensions = 1 << 6, 786 X86_MachineCheckExtensions = 1 << 7, 787 788 X86_CMPXCHG8Instruction = 1 << 8, 789 X86_OnboardAPIC = 1 << 9, 790 X86_SYSENTER_SYSEXIT = 1 << 11, 791 792 X86_MemoryTypeRangeRegisters = 1 << 12, 793 X86_PageGlobalEnable = 1 << 13, 794 X86_MachineCheckArchitecture = 1 << 14, 795 X86_CMOVInstruction = 1 << 15, 796 797 X86_PageAttributeTable = 1 << 16, 798 X86_36BitPSEs = 1 << 17, 799 X86_ProcessorSerialNumber = 1 << 18, 800 X86_CLFLUSHInstruction = 1 << 19, 801 802 X86_DebugTraceStore = 1 << 21, 803 X86_ACPIViaMSR = 1 << 22, 804 X86_MultimediaExtensions = 1 << 23, 805 806 X86_FXSAVE_FXRSTOR = 1 << 24, 807 X86_StreamingSIMDExtensions = 1 << 25, 808 X86_StreamingSIMDExtensions2 = 1 << 26, 809 X86_CPUSelfSnoop = 1 << 27, 810 811 X86_HyperThreading = 1 << 28, 812 X86_AutomaticClockControl = 1 << 29, 813 X86_IA64Processor = 1 << 30 814 }; 815 816 // Setup the auxiliary vectors. These will already have endian 817 // conversion. Auxiliary vectors are loaded only for elf formatted 818 // executables; the auxv is responsible for passing information from 819 // the OS to the interpreter. 820 ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 821 if (elfObject) { 822 uint64_t features = 823 X86_OnboardFPU | 824 X86_VirtualModeExtensions | 825 X86_DebuggingExtensions | 826 X86_PageSizeExtensions | 827 X86_TimeStampCounter | 828 X86_ModelSpecificRegisters | 829 X86_PhysicalAddressExtensions | 830 X86_MachineCheckExtensions | 831 X86_CMPXCHG8Instruction | 832 X86_OnboardAPIC | 833 X86_SYSENTER_SYSEXIT | 834 X86_MemoryTypeRangeRegisters | 835 X86_PageGlobalEnable | 836 X86_MachineCheckArchitecture | 837 X86_CMOVInstruction | 838 X86_PageAttributeTable | 839 X86_36BitPSEs | 840// X86_ProcessorSerialNumber | 841 X86_CLFLUSHInstruction | 842// X86_DebugTraceStore | 843// X86_ACPIViaMSR | 844 X86_MultimediaExtensions | 845 X86_FXSAVE_FXRSTOR | 846 X86_StreamingSIMDExtensions | 847 X86_StreamingSIMDExtensions2 | 848// X86_CPUSelfSnoop | 849// X86_HyperThreading | 850// X86_AutomaticClockControl | 851// X86_IA64Processor | 852 0; 853 854 // Bits which describe the system hardware capabilities 855 // XXX Figure out what these should be 856 auxv.push_back(auxv_t(M5_AT_HWCAP, features)); 857 // The system page size 858 auxv.push_back(auxv_t(M5_AT_PAGESZ, X86ISA::PageBytes)); 859 // Frequency at which times() increments 860 // Defined to be 100 in the kernel source. 861 auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 862 // This is the virtual address of the program header tables if they 863 // appear in the executable image. 864 auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 865 // This is the size of a program header entry from the elf file. 866 auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 867 // This is the number of program headers from the original elf file. 868 auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 869 // This is the base address of the ELF interpreter; it should be 870 // zero for static executables or contain the base address for 871 // dynamic executables. 872 auxv.push_back(auxv_t(M5_AT_BASE, getBias())); 873 // XXX Figure out what this should be. 874 auxv.push_back(auxv_t(M5_AT_FLAGS, 0)); 875 // The entry point to the program 876 auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 877 // Different user and group IDs 878 auxv.push_back(auxv_t(M5_AT_UID, uid())); 879 auxv.push_back(auxv_t(M5_AT_EUID, euid())); 880 auxv.push_back(auxv_t(M5_AT_GID, gid())); 881 auxv.push_back(auxv_t(M5_AT_EGID, egid())); 882 // Whether to enable "secure mode" in the executable 883 auxv.push_back(auxv_t(M5_AT_SECURE, 0)); 884 // The address of 16 "random" bytes. 885 auxv.push_back(auxv_t(M5_AT_RANDOM, 0)); 886 // The name of the program 887 auxv.push_back(auxv_t(M5_AT_EXECFN, 0)); 888 // The platform string 889 auxv.push_back(auxv_t(M5_AT_PLATFORM, 0)); 890 } 891 892 // Figure out how big the initial stack needs to be 893 894 // A sentry NULL void pointer at the top of the stack. 895 int sentry_size = intSize; 896 897 // This is the name of the file which is present on the initial stack 898 // It's purpose is to let the user space linker examine the original file. 899 int file_name_size = filename.size() + 1; 900 901 const int numRandomBytes = 16; 902 int aux_data_size = numRandomBytes; 903 904 string platform = "x86_64"; 905 aux_data_size += platform.size() + 1; 906 907 int env_data_size = 0; 908 for (int i = 0; i < envp.size(); ++i) 909 env_data_size += envp[i].size() + 1; 910 int arg_data_size = 0; 911 for (int i = 0; i < argv.size(); ++i) 912 arg_data_size += argv[i].size() + 1; 913 914 // The info_block needs to be padded so its size is a multiple of the 915 // alignment mask. Also, it appears that there needs to be at least some 916 // padding, so if the size is already a multiple, we need to increase it 917 // anyway. 918 int base_info_block_size = 919 sentry_size + file_name_size + env_data_size + arg_data_size; 920 921 int info_block_size = roundUp(base_info_block_size, align); 922 923 int info_block_padding = info_block_size - base_info_block_size; 924 925 // Each auxiliary vector is two 8 byte words 926 int aux_array_size = intSize * 2 * (auxv.size() + 1); 927 928 int envp_array_size = intSize * (envp.size() + 1); 929 int argv_array_size = intSize * (argv.size() + 1); 930 931 int argc_size = intSize; 932 933 // Figure out the size of the contents of the actual initial frame 934 int frame_size = 935 aux_array_size + 936 envp_array_size + 937 argv_array_size + 938 argc_size; 939 940 // There needs to be padding after the auxiliary vector data so that the 941 // very bottom of the stack is aligned properly. 942 int partial_size = frame_size + aux_data_size; 943 int aligned_partial_size = roundUp(partial_size, align); 944 int aux_padding = aligned_partial_size - partial_size; 945 946 int space_needed = 947 info_block_size + 948 aux_data_size + 949 aux_padding + 950 frame_size; 951 952 Addr stack_base = memState->getStackBase(); 953 954 Addr stack_min = stack_base - space_needed; 955 stack_min = roundDown(stack_min, align); 956 957 unsigned stack_size = stack_base - stack_min; 958 stack_size = roundUp(stack_size, pageSize); 959 memState->setStackSize(stack_size); 960 961 // map memory 962 Addr stack_end = roundDown(stack_base - stack_size, pageSize); 963 964 DPRINTF(Stack, "Mapping the stack: 0x%x %dB\n", stack_end, stack_size); 965 allocateMem(stack_end, stack_size); 966 967 // map out initial stack contents 968 IntType sentry_base = stack_base - sentry_size; 969 IntType file_name_base = sentry_base - file_name_size; 970 IntType env_data_base = file_name_base - env_data_size; 971 IntType arg_data_base = env_data_base - arg_data_size; 972 IntType aux_data_base = arg_data_base - info_block_padding - aux_data_size; 973 IntType auxv_array_base = aux_data_base - aux_array_size - aux_padding; 974 IntType envp_array_base = auxv_array_base - envp_array_size; 975 IntType argv_array_base = envp_array_base - argv_array_size; 976 IntType argc_base = argv_array_base - argc_size; 977 978 DPRINTF(Stack, "The addresses of items on the initial stack:\n"); 979 DPRINTF(Stack, "0x%x - file name\n", file_name_base); 980 DPRINTF(Stack, "0x%x - env data\n", env_data_base); 981 DPRINTF(Stack, "0x%x - arg data\n", arg_data_base); 982 DPRINTF(Stack, "0x%x - aux data\n", aux_data_base); 983 DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base); 984 DPRINTF(Stack, "0x%x - envp array\n", envp_array_base); 985 DPRINTF(Stack, "0x%x - argv array\n", argv_array_base); 986 DPRINTF(Stack, "0x%x - argc \n", argc_base); 987 DPRINTF(Stack, "0x%x - stack min\n", stack_min); 988 989 // write contents to stack 990 991 // figure out argc 992 IntType argc = argv.size(); 993 IntType guestArgc = X86ISA::htog(argc); 994 995 // Write out the sentry void * 996 IntType sentry_NULL = 0; 997 initVirtMem.writeBlob(sentry_base, (uint8_t*)&sentry_NULL, sentry_size); 998 999 // Write the file name 1000 initVirtMem.writeString(file_name_base, filename.c_str()); 1001 1002 // Fix up the aux vectors which point to data 1003 assert(auxv[auxv.size() - 3].a_type == M5_AT_RANDOM); 1004 auxv[auxv.size() - 3].a_val = aux_data_base; 1005 assert(auxv[auxv.size() - 2].a_type == M5_AT_EXECFN); 1006 auxv[auxv.size() - 2].a_val = argv_array_base; 1007 assert(auxv[auxv.size() - 1].a_type == M5_AT_PLATFORM); 1008 auxv[auxv.size() - 1].a_val = aux_data_base + numRandomBytes; 1009 1010 1011 // Copy the aux stuff 1012 for (int x = 0; x < auxv.size(); x++) { 1013 initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize, 1014 (uint8_t*)&(auxv[x].a_type), intSize); 1015 initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 1016 (uint8_t*)&(auxv[x].a_val), intSize); 1017 } 1018 // Write out the terminating zeroed auxiliary vector 1019 const uint64_t zero = 0; 1020 initVirtMem.writeBlob(auxv_array_base + auxv.size() * 2 * intSize, 1021 (uint8_t*)&zero, intSize); 1022 initVirtMem.writeBlob(auxv_array_base + (auxv.size() * 2 + 1) * intSize, 1023 (uint8_t*)&zero, intSize); 1024 1025 initVirtMem.writeString(aux_data_base, platform.c_str()); 1026 1027 copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 1028 copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 1029 1030 initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); 1031 1032 ThreadContext *tc = system->getThreadContext(contextIds[0]); 1033 // Set the stack pointer register 1034 tc->setIntReg(StackPointerReg, stack_min); 1035 1036 // There doesn't need to be any segment base added in since we're dealing 1037 // with the flat segmentation model. 1038 tc->pcState(getStartPC()); 1039 1040 // Align the "stack_min" to a page boundary. 1041 memState->setStackMin(roundDown(stack_min, pageSize)); 1042} 1043 1044void 1045X86_64Process::argsInit(int pageSize) 1046{ 1047 std::vector<AuxVector<uint64_t> > extraAuxvs; 1048 extraAuxvs.push_back(AuxVector<uint64_t>(M5_AT_SYSINFO_EHDR, 1049 vsyscallPage.base)); 1050 X86Process::argsInit<uint64_t>(pageSize, extraAuxvs); 1051} 1052 1053void 1054I386Process::argsInit(int pageSize) 1055{ 1056 std::vector<AuxVector<uint32_t> > extraAuxvs; 1057 //Tell the binary where the vsyscall part of the vsyscall page is. 1058 extraAuxvs.push_back(AuxVector<uint32_t>(M5_AT_SYSINFO, 1059 vsyscallPage.base + vsyscallPage.vsyscallOffset)); 1060 extraAuxvs.push_back(AuxVector<uint32_t>(M5_AT_SYSINFO_EHDR, 1061 vsyscallPage.base)); 1062 X86Process::argsInit<uint32_t>(pageSize, extraAuxvs); 1063} 1064 1065void 1066X86Process::setSyscallReturn(ThreadContext *tc, SyscallReturn retval) 1067{ 1068 tc->setIntReg(INTREG_RAX, retval.encodedValue()); 1069} 1070 1071X86ISA::IntReg 1072X86_64Process::getSyscallArg(ThreadContext *tc, int &i) 1073{ 1074 assert(i < NumArgumentRegs); 1075 return tc->readIntReg(ArgumentReg[i++]); 1076} 1077 1078void 1079X86_64Process::setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val) 1080{ 1081 assert(i < NumArgumentRegs); 1082 return tc->setIntReg(ArgumentReg[i], val); 1083} 1084 1085void 1086X86_64Process::clone(ThreadContext *old_tc, ThreadContext *new_tc, 1087 Process *p, TheISA::IntReg flags) 1088{ 1089 X86Process::clone(old_tc, new_tc, p, flags); 1090 ((X86_64Process*)p)->vsyscallPage = vsyscallPage; 1091} 1092 1093X86ISA::IntReg 1094I386Process::getSyscallArg(ThreadContext *tc, int &i) 1095{ 1096 assert(i < NumArgumentRegs32); 1097 return tc->readIntReg(ArgumentReg32[i++]); 1098} 1099 1100X86ISA::IntReg 1101I386Process::getSyscallArg(ThreadContext *tc, int &i, int width) 1102{ 1103 assert(width == 32 || width == 64); 1104 assert(i < NumArgumentRegs); 1105 uint64_t retVal = tc->readIntReg(ArgumentReg32[i++]) & mask(32); 1106 if (width == 64) 1107 retVal |= ((uint64_t)tc->readIntReg(ArgumentReg[i++]) << 32); 1108 return retVal; 1109} 1110 1111void 1112I386Process::setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val) 1113{ 1114 assert(i < NumArgumentRegs); 1115 return tc->setIntReg(ArgumentReg[i], val); 1116} 1117 1118void 1119I386Process::clone(ThreadContext *old_tc, ThreadContext *new_tc, 1120 Process *p, TheISA::IntReg flags) 1121{ 1122 X86Process::clone(old_tc, new_tc, p, flags); 1123 ((I386Process*)p)->vsyscallPage = vsyscallPage; 1124} 1125