process.cc revision 11884
14166Sgblack@eecs.umich.edu/* 210554Salexandru.dutu@amd.com * Copyright (c) 2014 Advanced Micro Devices, Inc. 37087Snate@binkert.org * Copyright (c) 2007 The Hewlett-Packard Development Company 47087Snate@binkert.org * All rights reserved. 57087Snate@binkert.org * 67087Snate@binkert.org * The license below extends only to copyright in the software and shall 77087Snate@binkert.org * not be construed as granting a license to any other intellectual 87087Snate@binkert.org * property including but not limited to intellectual property relating 97087Snate@binkert.org * to a hardware implementation of the functionality of the software 107087Snate@binkert.org * licensed hereunder. You may use the software subject to the license 117087Snate@binkert.org * terms below provided that you ensure that this notice is replicated 127087Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 137087Snate@binkert.org * modified or unmodified, in source code or in binary form. 147087Snate@binkert.org * 154166Sgblack@eecs.umich.edu * Copyright (c) 2003-2006 The Regents of The University of Michigan 164166Sgblack@eecs.umich.edu * All rights reserved. 174166Sgblack@eecs.umich.edu * 184166Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 194166Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 204166Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 214166Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 224166Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 234166Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 244166Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 254166Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 264166Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 274166Sgblack@eecs.umich.edu * this software without specific prior written permission. 284166Sgblack@eecs.umich.edu * 294166Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 304166Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 314166Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 324166Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 334166Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 344166Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 354166Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 364166Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 374166Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 384166Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 394166Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 404166Sgblack@eecs.umich.edu * 414166Sgblack@eecs.umich.edu * Authors: Gabe Black 424166Sgblack@eecs.umich.edu * Ali Saidi 434166Sgblack@eecs.umich.edu */ 444166Sgblack@eecs.umich.edu 4511793Sbrandon.potter@amd.com#include "arch/x86/process.hh" 4611793Sbrandon.potter@amd.com 4711854Sbrandon.potter@amd.com#include <string> 4811854Sbrandon.potter@amd.com#include <vector> 4911854Sbrandon.potter@amd.com 5011793Sbrandon.potter@amd.com#include "arch/x86/isa_traits.hh" 518229Snate@binkert.org#include "arch/x86/regs/misc.hh" 528229Snate@binkert.org#include "arch/x86/regs/segment.hh" 5310554Salexandru.dutu@amd.com#include "arch/x86/system.hh" 544166Sgblack@eecs.umich.edu#include "arch/x86/types.hh" 558229Snate@binkert.org#include "base/loader/elf_object.hh" 564166Sgblack@eecs.umich.edu#include "base/loader/object_file.hh" 574166Sgblack@eecs.umich.edu#include "base/misc.hh" 585004Sgblack@eecs.umich.edu#include "base/trace.hh" 594166Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 608232Snate@binkert.org#include "debug/Stack.hh" 6110554Salexandru.dutu@amd.com#include "mem/multi_level_page_table.hh" 624166Sgblack@eecs.umich.edu#include "mem/page_table.hh" 6311854Sbrandon.potter@amd.com#include "sim/aux_vector.hh" 644434Ssaidi@eecs.umich.edu#include "sim/process_impl.hh" 6511794Sbrandon.potter@amd.com#include "sim/syscall_desc.hh" 6611800Sbrandon.potter@amd.com#include "sim/syscall_return.hh" 674166Sgblack@eecs.umich.edu#include "sim/system.hh" 684166Sgblack@eecs.umich.edu 694166Sgblack@eecs.umich.eduusing namespace std; 704166Sgblack@eecs.umich.eduusing namespace X86ISA; 714166Sgblack@eecs.umich.edu 725958Sgblack@eecs.umich.edustatic const int ArgumentReg[] = { 735958Sgblack@eecs.umich.edu INTREG_RDI, 745958Sgblack@eecs.umich.edu INTREG_RSI, 755958Sgblack@eecs.umich.edu INTREG_RDX, 765958Sgblack@eecs.umich.edu //This argument register is r10 for syscalls and rcx for C. 775958Sgblack@eecs.umich.edu INTREG_R10W, 785958Sgblack@eecs.umich.edu //INTREG_RCX, 795958Sgblack@eecs.umich.edu INTREG_R8W, 805958Sgblack@eecs.umich.edu INTREG_R9W 815958Sgblack@eecs.umich.edu}; 8211704Santhony.gutierrez@amd.com 8311704Santhony.gutierrez@amd.comstatic const int NumArgumentRegs M5_VAR_USED = 8411704Santhony.gutierrez@amd.com sizeof(ArgumentReg) / sizeof(const int); 8511704Santhony.gutierrez@amd.com 865959Sgblack@eecs.umich.edustatic const int ArgumentReg32[] = { 875959Sgblack@eecs.umich.edu INTREG_EBX, 885959Sgblack@eecs.umich.edu INTREG_ECX, 895959Sgblack@eecs.umich.edu INTREG_EDX, 905959Sgblack@eecs.umich.edu INTREG_ESI, 915959Sgblack@eecs.umich.edu INTREG_EDI, 9211385Sbrandon.potter@amd.com INTREG_EBP 935959Sgblack@eecs.umich.edu}; 9411704Santhony.gutierrez@amd.com 9511704Santhony.gutierrez@amd.comstatic const int NumArgumentRegs32 M5_VAR_USED = 9611704Santhony.gutierrez@amd.com sizeof(ArgumentReg) / sizeof(const int); 974166Sgblack@eecs.umich.edu 9811851Sbrandon.potter@amd.comX86Process::X86Process(ProcessParams * params, ObjectFile *objFile, 9911851Sbrandon.potter@amd.com SyscallDesc *_syscallDescs, int _numSyscallDescs) 10011851Sbrandon.potter@amd.com : Process(params, objFile), syscallDescs(_syscallDescs), 10111851Sbrandon.potter@amd.com numSyscallDescs(_numSyscallDescs) 1024166Sgblack@eecs.umich.edu{ 1034166Sgblack@eecs.umich.edu brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize(); 10410318Sandreas.hansson@arm.com brk_point = roundUp(brk_point, PageBytes); 1055956Sgblack@eecs.umich.edu} 1064166Sgblack@eecs.umich.edu 10711851Sbrandon.potter@amd.comX86_64Process::X86_64Process(ProcessParams *params, ObjectFile *objFile, 10811851Sbrandon.potter@amd.com SyscallDesc *_syscallDescs, int _numSyscallDescs) 10911851Sbrandon.potter@amd.com : X86Process(params, objFile, _syscallDescs, _numSyscallDescs) 1105956Sgblack@eecs.umich.edu{ 1116709Svince@csl.cornell.edu 1126709Svince@csl.cornell.edu vsyscallPage.base = 0xffffffffff600000ULL; 11310318Sandreas.hansson@arm.com vsyscallPage.size = PageBytes; 1146709Svince@csl.cornell.edu vsyscallPage.vtimeOffset = 0x400; 1159679Smjleven@sandia.gov vsyscallPage.vgettimeofdayOffset = 0x0; 1166709Svince@csl.cornell.edu 1174786Sgblack@eecs.umich.edu // Set up stack. On X86_64 Linux, stack goes from the top of memory 1184786Sgblack@eecs.umich.edu // downward, less the hole for the kernel address space plus one page 1194786Sgblack@eecs.umich.edu // for undertermined purposes. 1204793Sgblack@eecs.umich.edu stack_base = (Addr)0x7FFFFFFFF000ULL; 1214166Sgblack@eecs.umich.edu 1225956Sgblack@eecs.umich.edu // Set pointer for next thread stack. Reserve 8M for main stack. 1235956Sgblack@eecs.umich.edu next_thread_stack_base = stack_base - (8 * 1024 * 1024); 1245956Sgblack@eecs.umich.edu 12511387Sbrandon.potter@amd.com // "mmap_base" is a function which defines where mmap region starts in 12611387Sbrandon.potter@amd.com // the process address space. 12711387Sbrandon.potter@amd.com // mmap_base: PAGE_ALIGN(TASK_SIZE-MIN_GAP-mmap_rnd()) 12811387Sbrandon.potter@amd.com // TASK_SIZE: (1<<47)-PAGE_SIZE 12911387Sbrandon.potter@amd.com // MIN_GAP: 128*1024*1024+stack_maxrandom_size() 13011387Sbrandon.potter@amd.com // We do not use any address space layout randomization in gem5 13111387Sbrandon.potter@amd.com // therefore the random fields become zero; the smallest gap space was 13211387Sbrandon.potter@amd.com // chosen but gap could potentially be much larger. 13311387Sbrandon.potter@amd.com mmap_end = (Addr)0x7FFFF7FFF000ULL; 1344166Sgblack@eecs.umich.edu} 1354166Sgblack@eecs.umich.edu 1365973Sgblack@eecs.umich.eduvoid 13711877Sbrandon.potter@amd.comI386Process::syscall(int64_t callnum, ThreadContext *tc, Fault *fault) 1385973Sgblack@eecs.umich.edu{ 1397720Sgblack@eecs.umich.edu TheISA::PCState pc = tc->pcState(); 1407720Sgblack@eecs.umich.edu Addr eip = pc.pc(); 1415973Sgblack@eecs.umich.edu if (eip >= vsyscallPage.base && 1425973Sgblack@eecs.umich.edu eip < vsyscallPage.base + vsyscallPage.size) { 1437720Sgblack@eecs.umich.edu pc.npc(vsyscallPage.base + vsyscallPage.vsysexitOffset); 1447720Sgblack@eecs.umich.edu tc->pcState(pc); 1455973Sgblack@eecs.umich.edu } 14611877Sbrandon.potter@amd.com X86Process::syscall(callnum, tc, fault); 1475973Sgblack@eecs.umich.edu} 1485973Sgblack@eecs.umich.edu 1495973Sgblack@eecs.umich.edu 15011851Sbrandon.potter@amd.comI386Process::I386Process(ProcessParams *params, ObjectFile *objFile, 15111851Sbrandon.potter@amd.com SyscallDesc *_syscallDescs, int _numSyscallDescs) 15211851Sbrandon.potter@amd.com : X86Process(params, objFile, _syscallDescs, _numSyscallDescs) 1534166Sgblack@eecs.umich.edu{ 1549026Sgblack@eecs.umich.edu _gdtStart = ULL(0xffffd000); 15510318Sandreas.hansson@arm.com _gdtSize = PageBytes; 1565973Sgblack@eecs.umich.edu 1575973Sgblack@eecs.umich.edu vsyscallPage.base = 0xffffe000ULL; 15810318Sandreas.hansson@arm.com vsyscallPage.size = PageBytes; 1595973Sgblack@eecs.umich.edu vsyscallPage.vsyscallOffset = 0x400; 1605973Sgblack@eecs.umich.edu vsyscallPage.vsysexitOffset = 0x410; 1615973Sgblack@eecs.umich.edu 1629026Sgblack@eecs.umich.edu stack_base = _gdtStart; 1635956Sgblack@eecs.umich.edu 1645956Sgblack@eecs.umich.edu // Set pointer for next thread stack. Reserve 8M for main stack. 1655956Sgblack@eecs.umich.edu next_thread_stack_base = stack_base - (8 * 1024 * 1024); 1665956Sgblack@eecs.umich.edu 16711387Sbrandon.potter@amd.com // "mmap_base" is a function which defines where mmap region starts in 16811387Sbrandon.potter@amd.com // the process address space. 16911387Sbrandon.potter@amd.com // mmap_base: PAGE_ALIGN(TASK_SIZE-MIN_GAP-mmap_rnd()) 17011387Sbrandon.potter@amd.com // TASK_SIZE: 0xC0000000 17111387Sbrandon.potter@amd.com // MIN_GAP: 128*1024*1024+stack_maxrandom_size() 17211387Sbrandon.potter@amd.com // We do not use any address space layout randomization in gem5 17311387Sbrandon.potter@amd.com // therefore the random fields become zero; the smallest gap space was 17411387Sbrandon.potter@amd.com // chosen but gap could potentially be much larger. 17511387Sbrandon.potter@amd.com mmap_end = (Addr)0xB7FFF000ULL; 1765956Sgblack@eecs.umich.edu} 1775956Sgblack@eecs.umich.edu 1785956Sgblack@eecs.umich.eduSyscallDesc* 17911851Sbrandon.potter@amd.comX86Process::getDesc(int callnum) 1805956Sgblack@eecs.umich.edu{ 1815956Sgblack@eecs.umich.edu if (callnum < 0 || callnum >= numSyscallDescs) 1825956Sgblack@eecs.umich.edu return NULL; 1835956Sgblack@eecs.umich.edu return &syscallDescs[callnum]; 1844166Sgblack@eecs.umich.edu} 1854166Sgblack@eecs.umich.edu 1864166Sgblack@eecs.umich.eduvoid 18711851Sbrandon.potter@amd.comX86_64Process::initState() 1884166Sgblack@eecs.umich.edu{ 18911851Sbrandon.potter@amd.com X86Process::initState(); 1905183Ssaidi@eecs.umich.edu 19111884Sbrandon.potter@amd.com argsInit(PageBytes); 1925140Sgblack@eecs.umich.edu 1936709Svince@csl.cornell.edu // Set up the vsyscall page for this process. 1948601Ssteve.reinhardt@amd.com allocateMem(vsyscallPage.base, vsyscallPage.size); 1956709Svince@csl.cornell.edu uint8_t vtimeBlob[] = { 1966709Svince@csl.cornell.edu 0x48,0xc7,0xc0,0xc9,0x00,0x00,0x00, // mov $0xc9,%rax 1976709Svince@csl.cornell.edu 0x0f,0x05, // syscall 1986709Svince@csl.cornell.edu 0xc3 // retq 1996709Svince@csl.cornell.edu }; 2008852Sandreas.hansson@arm.com initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vtimeOffset, 2016709Svince@csl.cornell.edu vtimeBlob, sizeof(vtimeBlob)); 2026709Svince@csl.cornell.edu 2036709Svince@csl.cornell.edu uint8_t vgettimeofdayBlob[] = { 2046709Svince@csl.cornell.edu 0x48,0xc7,0xc0,0x60,0x00,0x00,0x00, // mov $0x60,%rax 2056709Svince@csl.cornell.edu 0x0f,0x05, // syscall 2066709Svince@csl.cornell.edu 0xc3 // retq 2076709Svince@csl.cornell.edu }; 2088852Sandreas.hansson@arm.com initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vgettimeofdayOffset, 2096709Svince@csl.cornell.edu vgettimeofdayBlob, sizeof(vgettimeofdayBlob)); 2106709Svince@csl.cornell.edu 21110554Salexandru.dutu@amd.com if (kvmInSE) { 21210554Salexandru.dutu@amd.com PortProxy physProxy = system->physProxy; 2135140Sgblack@eecs.umich.edu 21410554Salexandru.dutu@amd.com /* 21510554Salexandru.dutu@amd.com * Set up the gdt. 21610554Salexandru.dutu@amd.com */ 21710554Salexandru.dutu@amd.com uint8_t numGDTEntries = 0; 21810554Salexandru.dutu@amd.com uint64_t nullDescriptor = 0; 21910554Salexandru.dutu@amd.com physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8, 22010554Salexandru.dutu@amd.com (uint8_t *)(&nullDescriptor), 8); 22110554Salexandru.dutu@amd.com numGDTEntries++; 2225140Sgblack@eecs.umich.edu 22310554Salexandru.dutu@amd.com SegDescriptor initDesc = 0; 22410554Salexandru.dutu@amd.com initDesc.type.codeOrData = 0; // code or data type 22510554Salexandru.dutu@amd.com initDesc.type.c = 0; // conforming 22610554Salexandru.dutu@amd.com initDesc.type.r = 1; // readable 22710554Salexandru.dutu@amd.com initDesc.dpl = 0; // privilege 22810554Salexandru.dutu@amd.com initDesc.p = 1; // present 22910554Salexandru.dutu@amd.com initDesc.l = 1; // longmode - 64 bit 23010554Salexandru.dutu@amd.com initDesc.d = 0; // operand size 23110554Salexandru.dutu@amd.com initDesc.g = 1; // granularity 23210554Salexandru.dutu@amd.com initDesc.s = 1; // system segment 23310554Salexandru.dutu@amd.com initDesc.limitHigh = 0xFFFF; 23410554Salexandru.dutu@amd.com initDesc.limitLow = 0xF; 23510554Salexandru.dutu@amd.com initDesc.baseHigh = 0x0; 23610554Salexandru.dutu@amd.com initDesc.baseLow = 0x0; 23710554Salexandru.dutu@amd.com 23810554Salexandru.dutu@amd.com //64 bit code segment 23910554Salexandru.dutu@amd.com SegDescriptor csLowPLDesc = initDesc; 24010554Salexandru.dutu@amd.com csLowPLDesc.type.codeOrData = 1; 24110554Salexandru.dutu@amd.com csLowPLDesc.dpl = 0; 24210554Salexandru.dutu@amd.com uint64_t csLowPLDescVal = csLowPLDesc; 24310554Salexandru.dutu@amd.com physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8, 24410554Salexandru.dutu@amd.com (uint8_t *)(&csLowPLDescVal), 8); 24510554Salexandru.dutu@amd.com 24610554Salexandru.dutu@amd.com numGDTEntries++; 24710554Salexandru.dutu@amd.com 24810554Salexandru.dutu@amd.com SegSelector csLowPL = 0; 24910554Salexandru.dutu@amd.com csLowPL.si = numGDTEntries - 1; 25010554Salexandru.dutu@amd.com csLowPL.rpl = 0; 25110554Salexandru.dutu@amd.com 25210554Salexandru.dutu@amd.com //64 bit data segment 25310554Salexandru.dutu@amd.com SegDescriptor dsLowPLDesc = initDesc; 25410554Salexandru.dutu@amd.com dsLowPLDesc.type.codeOrData = 0; 25510554Salexandru.dutu@amd.com dsLowPLDesc.dpl = 0; 25610554Salexandru.dutu@amd.com uint64_t dsLowPLDescVal = dsLowPLDesc; 25710554Salexandru.dutu@amd.com physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8, 25810554Salexandru.dutu@amd.com (uint8_t *)(&dsLowPLDescVal), 8); 25910554Salexandru.dutu@amd.com 26010554Salexandru.dutu@amd.com numGDTEntries++; 26110554Salexandru.dutu@amd.com 26210554Salexandru.dutu@amd.com SegSelector dsLowPL = 0; 26310554Salexandru.dutu@amd.com dsLowPL.si = numGDTEntries - 1; 26410554Salexandru.dutu@amd.com dsLowPL.rpl = 0; 26510554Salexandru.dutu@amd.com 26610554Salexandru.dutu@amd.com //64 bit data segment 26710554Salexandru.dutu@amd.com SegDescriptor dsDesc = initDesc; 26810554Salexandru.dutu@amd.com dsDesc.type.codeOrData = 0; 26910554Salexandru.dutu@amd.com dsDesc.dpl = 3; 27010554Salexandru.dutu@amd.com uint64_t dsDescVal = dsDesc; 27110554Salexandru.dutu@amd.com physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8, 27210554Salexandru.dutu@amd.com (uint8_t *)(&dsDescVal), 8); 27310554Salexandru.dutu@amd.com 27410554Salexandru.dutu@amd.com numGDTEntries++; 27510554Salexandru.dutu@amd.com 27610554Salexandru.dutu@amd.com SegSelector ds = 0; 27710554Salexandru.dutu@amd.com ds.si = numGDTEntries - 1; 27810554Salexandru.dutu@amd.com ds.rpl = 3; 27910554Salexandru.dutu@amd.com 28010554Salexandru.dutu@amd.com //64 bit code segment 28110554Salexandru.dutu@amd.com SegDescriptor csDesc = initDesc; 28210554Salexandru.dutu@amd.com csDesc.type.codeOrData = 1; 28310554Salexandru.dutu@amd.com csDesc.dpl = 3; 28410554Salexandru.dutu@amd.com uint64_t csDescVal = csDesc; 28510554Salexandru.dutu@amd.com physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8, 28610554Salexandru.dutu@amd.com (uint8_t *)(&csDescVal), 8); 28710554Salexandru.dutu@amd.com 28810554Salexandru.dutu@amd.com numGDTEntries++; 28910554Salexandru.dutu@amd.com 29010554Salexandru.dutu@amd.com SegSelector cs = 0; 29110554Salexandru.dutu@amd.com cs.si = numGDTEntries - 1; 29210554Salexandru.dutu@amd.com cs.rpl = 3; 29310554Salexandru.dutu@amd.com 29410554Salexandru.dutu@amd.com SegSelector scall = 0; 29510554Salexandru.dutu@amd.com scall.si = csLowPL.si; 29610554Salexandru.dutu@amd.com scall.rpl = 0; 29710554Salexandru.dutu@amd.com 29810554Salexandru.dutu@amd.com SegSelector sret = 0; 29910554Salexandru.dutu@amd.com sret.si = dsLowPL.si; 30010554Salexandru.dutu@amd.com sret.rpl = 3; 30110554Salexandru.dutu@amd.com 30210554Salexandru.dutu@amd.com /* In long mode the TSS has been extended to 16 Bytes */ 30310554Salexandru.dutu@amd.com TSSlow TSSDescLow = 0; 30410554Salexandru.dutu@amd.com TSSDescLow.type = 0xB; 30510554Salexandru.dutu@amd.com TSSDescLow.dpl = 0; // Privelege level 0 30610554Salexandru.dutu@amd.com TSSDescLow.p = 1; // Present 30710554Salexandru.dutu@amd.com TSSDescLow.g = 1; // Page granularity 30810554Salexandru.dutu@amd.com TSSDescLow.limitHigh = 0xF; 30910554Salexandru.dutu@amd.com TSSDescLow.limitLow = 0xFFFF; 31010590Sgabeblack@google.com TSSDescLow.baseLow = bits(TSSVirtAddr, 23, 0); 31110590Sgabeblack@google.com TSSDescLow.baseHigh = bits(TSSVirtAddr, 31, 24); 31210554Salexandru.dutu@amd.com 31310554Salexandru.dutu@amd.com TSShigh TSSDescHigh = 0; 31410590Sgabeblack@google.com TSSDescHigh.base = bits(TSSVirtAddr, 63, 32); 31510554Salexandru.dutu@amd.com 31610554Salexandru.dutu@amd.com struct TSSDesc { 31710554Salexandru.dutu@amd.com uint64_t low; 31810554Salexandru.dutu@amd.com uint64_t high; 31910554Salexandru.dutu@amd.com } tssDescVal = {TSSDescLow, TSSDescHigh}; 32010554Salexandru.dutu@amd.com 32110554Salexandru.dutu@amd.com physProxy.writeBlob(GDTPhysAddr + numGDTEntries * 8, 32210554Salexandru.dutu@amd.com (uint8_t *)(&tssDescVal), sizeof(tssDescVal)); 32310554Salexandru.dutu@amd.com 32410554Salexandru.dutu@amd.com numGDTEntries++; 32510554Salexandru.dutu@amd.com 32610554Salexandru.dutu@amd.com SegSelector tssSel = 0; 32710554Salexandru.dutu@amd.com tssSel.si = numGDTEntries - 1; 32810554Salexandru.dutu@amd.com 32910590Sgabeblack@google.com uint64_t tss_base_addr = (TSSDescHigh.base << 32) | 33010590Sgabeblack@google.com (TSSDescLow.baseHigh << 24) | 33110590Sgabeblack@google.com TSSDescLow.baseLow; 33210554Salexandru.dutu@amd.com uint64_t tss_limit = TSSDescLow.limitLow | (TSSDescLow.limitHigh << 16); 33310554Salexandru.dutu@amd.com 33410554Salexandru.dutu@amd.com SegAttr tss_attr = 0; 33510554Salexandru.dutu@amd.com 33610554Salexandru.dutu@amd.com tss_attr.type = TSSDescLow.type; 33710554Salexandru.dutu@amd.com tss_attr.dpl = TSSDescLow.dpl; 33810554Salexandru.dutu@amd.com tss_attr.present = TSSDescLow.p; 33910554Salexandru.dutu@amd.com tss_attr.granularity = TSSDescLow.g; 34010554Salexandru.dutu@amd.com tss_attr.unusable = 0; 34110554Salexandru.dutu@amd.com 34210554Salexandru.dutu@amd.com for (int i = 0; i < contextIds.size(); i++) { 34310554Salexandru.dutu@amd.com ThreadContext * tc = system->getThreadContext(contextIds[i]); 34410554Salexandru.dutu@amd.com 34510590Sgabeblack@google.com tc->setMiscReg(MISCREG_CS, cs); 34610590Sgabeblack@google.com tc->setMiscReg(MISCREG_DS, ds); 34710590Sgabeblack@google.com tc->setMiscReg(MISCREG_ES, ds); 34810590Sgabeblack@google.com tc->setMiscReg(MISCREG_FS, ds); 34910590Sgabeblack@google.com tc->setMiscReg(MISCREG_GS, ds); 35010590Sgabeblack@google.com tc->setMiscReg(MISCREG_SS, ds); 35110554Salexandru.dutu@amd.com 35210554Salexandru.dutu@amd.com // LDT 35310554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_TSL, 0); 35410554Salexandru.dutu@amd.com SegAttr tslAttr = 0; 35510554Salexandru.dutu@amd.com tslAttr.present = 1; 35610554Salexandru.dutu@amd.com tslAttr.type = 2; 35710554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr); 35810554Salexandru.dutu@amd.com 35910554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr); 36010554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1); 36110554Salexandru.dutu@amd.com 36210590Sgabeblack@google.com tc->setMiscReg(MISCREG_TR, tssSel); 36310590Sgabeblack@google.com tc->setMiscReg(MISCREG_TR_BASE, tss_base_addr); 36410590Sgabeblack@google.com tc->setMiscReg(MISCREG_TR_EFF_BASE, 0); 36510590Sgabeblack@google.com tc->setMiscReg(MISCREG_TR_LIMIT, tss_limit); 36610590Sgabeblack@google.com tc->setMiscReg(MISCREG_TR_ATTR, tss_attr); 36710554Salexandru.dutu@amd.com 36810554Salexandru.dutu@amd.com //Start using longmode segments. 36910554Salexandru.dutu@amd.com installSegDesc(tc, SEGMENT_REG_CS, csDesc, true); 37010554Salexandru.dutu@amd.com installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true); 37110554Salexandru.dutu@amd.com installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true); 37210554Salexandru.dutu@amd.com installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true); 37310554Salexandru.dutu@amd.com installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true); 37410554Salexandru.dutu@amd.com installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true); 37510554Salexandru.dutu@amd.com 37610554Salexandru.dutu@amd.com Efer efer = 0; 37710554Salexandru.dutu@amd.com efer.sce = 1; // Enable system call extensions. 37810554Salexandru.dutu@amd.com efer.lme = 1; // Enable long mode. 37910554Salexandru.dutu@amd.com efer.lma = 1; // Activate long mode. 38010554Salexandru.dutu@amd.com efer.nxe = 0; // Enable nx support. 38110554Salexandru.dutu@amd.com efer.svme = 1; // Enable svm support for now. 38210554Salexandru.dutu@amd.com efer.ffxsr = 0; // Turn on fast fxsave and fxrstor. 38310554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_EFER, efer); 38410554Salexandru.dutu@amd.com 38510554Salexandru.dutu@amd.com //Set up the registers that describe the operating mode. 38610554Salexandru.dutu@amd.com CR0 cr0 = 0; 38710554Salexandru.dutu@amd.com cr0.pg = 1; // Turn on paging. 38810554Salexandru.dutu@amd.com cr0.cd = 0; // Don't disable caching. 38910554Salexandru.dutu@amd.com cr0.nw = 0; // This is bit is defined to be ignored. 39010554Salexandru.dutu@amd.com cr0.am = 1; // No alignment checking 39110554Salexandru.dutu@amd.com cr0.wp = 1; // Supervisor mode can write read only pages 39210554Salexandru.dutu@amd.com cr0.ne = 1; 39310554Salexandru.dutu@amd.com cr0.et = 1; // This should always be 1 39410554Salexandru.dutu@amd.com cr0.ts = 0; // We don't do task switching, so causing fp exceptions 39510554Salexandru.dutu@amd.com // would be pointless. 39610554Salexandru.dutu@amd.com cr0.em = 0; // Allow x87 instructions to execute natively. 39710554Salexandru.dutu@amd.com cr0.mp = 1; // This doesn't really matter, but the manual suggests 39810554Salexandru.dutu@amd.com // setting it to one. 39910554Salexandru.dutu@amd.com cr0.pe = 1; // We're definitely in protected mode. 40010554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_CR0, cr0); 40110554Salexandru.dutu@amd.com 40210554Salexandru.dutu@amd.com CR0 cr2 = 0; 40310554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_CR2, cr2); 40410554Salexandru.dutu@amd.com 40510554Salexandru.dutu@amd.com CR3 cr3 = pageTablePhysAddr; 40610554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_CR3, cr3); 40710554Salexandru.dutu@amd.com 40810554Salexandru.dutu@amd.com CR4 cr4 = 0; 40910554Salexandru.dutu@amd.com //Turn on pae. 41010554Salexandru.dutu@amd.com cr4.osxsave = 1; // Enable XSAVE and Proc Extended States 41110554Salexandru.dutu@amd.com cr4.osxmmexcpt = 1; // Operating System Unmasked Exception 41210554Salexandru.dutu@amd.com cr4.osfxsr = 1; // Operating System FXSave/FSRSTOR Support 41310554Salexandru.dutu@amd.com cr4.pce = 0; // Performance-Monitoring Counter Enable 41410554Salexandru.dutu@amd.com cr4.pge = 0; // Page-Global Enable 41510554Salexandru.dutu@amd.com cr4.mce = 0; // Machine Check Enable 41610554Salexandru.dutu@amd.com cr4.pae = 1; // Physical-Address Extension 41710554Salexandru.dutu@amd.com cr4.pse = 0; // Page Size Extensions 41810554Salexandru.dutu@amd.com cr4.de = 0; // Debugging Extensions 41910554Salexandru.dutu@amd.com cr4.tsd = 0; // Time Stamp Disable 42010554Salexandru.dutu@amd.com cr4.pvi = 0; // Protected-Mode Virtual Interrupts 42110554Salexandru.dutu@amd.com cr4.vme = 0; // Virtual-8086 Mode Extensions 42210554Salexandru.dutu@amd.com 42310554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_CR4, cr4); 42410554Salexandru.dutu@amd.com 42510554Salexandru.dutu@amd.com CR4 cr8 = 0; 42610554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_CR8, cr8); 42710554Salexandru.dutu@amd.com 42810554Salexandru.dutu@amd.com const Addr PageMapLevel4 = pageTablePhysAddr; 42910554Salexandru.dutu@amd.com //Point to the page tables. 43010554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_CR3, PageMapLevel4); 43110554Salexandru.dutu@amd.com 43210554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_MXCSR, 0x1f80); 43310554Salexandru.dutu@amd.com 43410554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_APIC_BASE, 0xfee00900); 43510554Salexandru.dutu@amd.com 43610590Sgabeblack@google.com tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr); 43710590Sgabeblack@google.com tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff); 43810554Salexandru.dutu@amd.com 43910590Sgabeblack@google.com tc->setMiscReg(MISCREG_IDTR_BASE, IDTVirtAddr); 44010590Sgabeblack@google.com tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff); 44110554Salexandru.dutu@amd.com 44210554Salexandru.dutu@amd.com /* enabling syscall and sysret */ 44310554Salexandru.dutu@amd.com MiscReg star = ((MiscReg)sret << 48) | ((MiscReg)scall << 32); 44410554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_STAR, star); 44510590Sgabeblack@google.com MiscReg lstar = (MiscReg)syscallCodeVirtAddr; 44610554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_LSTAR, lstar); 44710590Sgabeblack@google.com MiscReg sfmask = (1 << 8) | (1 << 10); // TF | DF 44810554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_SF_MASK, sfmask); 4495140Sgblack@eecs.umich.edu } 4505140Sgblack@eecs.umich.edu 45110590Sgabeblack@google.com /* Set up the content of the TSS and write it to physical memory. */ 4525140Sgblack@eecs.umich.edu 45310554Salexandru.dutu@amd.com struct { 45410554Salexandru.dutu@amd.com uint32_t reserved0; // +00h 45510554Salexandru.dutu@amd.com uint32_t RSP0_low; // +04h 45610554Salexandru.dutu@amd.com uint32_t RSP0_high; // +08h 45710554Salexandru.dutu@amd.com uint32_t RSP1_low; // +0Ch 45810554Salexandru.dutu@amd.com uint32_t RSP1_high; // +10h 45910554Salexandru.dutu@amd.com uint32_t RSP2_low; // +14h 46010554Salexandru.dutu@amd.com uint32_t RSP2_high; // +18h 46110554Salexandru.dutu@amd.com uint32_t reserved1; // +1Ch 46210554Salexandru.dutu@amd.com uint32_t reserved2; // +20h 46310554Salexandru.dutu@amd.com uint32_t IST1_low; // +24h 46410554Salexandru.dutu@amd.com uint32_t IST1_high; // +28h 46510554Salexandru.dutu@amd.com uint32_t IST2_low; // +2Ch 46610554Salexandru.dutu@amd.com uint32_t IST2_high; // +30h 46710554Salexandru.dutu@amd.com uint32_t IST3_low; // +34h 46810554Salexandru.dutu@amd.com uint32_t IST3_high; // +38h 46910554Salexandru.dutu@amd.com uint32_t IST4_low; // +3Ch 47010554Salexandru.dutu@amd.com uint32_t IST4_high; // +40h 47110554Salexandru.dutu@amd.com uint32_t IST5_low; // +44h 47210554Salexandru.dutu@amd.com uint32_t IST5_high; // +48h 47310554Salexandru.dutu@amd.com uint32_t IST6_low; // +4Ch 47410554Salexandru.dutu@amd.com uint32_t IST6_high; // +50h 47510554Salexandru.dutu@amd.com uint32_t IST7_low; // +54h 47610554Salexandru.dutu@amd.com uint32_t IST7_high; // +58h 47710554Salexandru.dutu@amd.com uint32_t reserved3; // +5Ch 47810554Salexandru.dutu@amd.com uint32_t reserved4; // +60h 47910554Salexandru.dutu@amd.com uint16_t reserved5; // +64h 48010554Salexandru.dutu@amd.com uint16_t IO_MapBase; // +66h 48110554Salexandru.dutu@amd.com } tss; 4825140Sgblack@eecs.umich.edu 48310554Salexandru.dutu@amd.com /** setting Interrupt Stack Table */ 48410554Salexandru.dutu@amd.com uint64_t IST_start = ISTVirtAddr + PageBytes; 48510590Sgabeblack@google.com tss.IST1_low = IST_start; 48610590Sgabeblack@google.com tss.IST1_high = IST_start >> 32; 48710554Salexandru.dutu@amd.com tss.RSP0_low = tss.IST1_low; 48810554Salexandru.dutu@amd.com tss.RSP0_high = tss.IST1_high; 48910554Salexandru.dutu@amd.com tss.RSP1_low = tss.IST1_low; 49010554Salexandru.dutu@amd.com tss.RSP1_high = tss.IST1_high; 49110554Salexandru.dutu@amd.com tss.RSP2_low = tss.IST1_low; 49210554Salexandru.dutu@amd.com tss.RSP2_high = tss.IST1_high; 49310554Salexandru.dutu@amd.com physProxy.writeBlob(TSSPhysAddr, (uint8_t *)(&tss), sizeof(tss)); 4946140Sgblack@eecs.umich.edu 49510554Salexandru.dutu@amd.com /* Setting IDT gates */ 49610554Salexandru.dutu@amd.com GateDescriptorLow PFGateLow = 0; 49710590Sgabeblack@google.com PFGateLow.offsetHigh = bits(PFHandlerVirtAddr, 31, 16); 49810590Sgabeblack@google.com PFGateLow.offsetLow = bits(PFHandlerVirtAddr, 15, 0); 49910590Sgabeblack@google.com PFGateLow.selector = csLowPL; 50010554Salexandru.dutu@amd.com PFGateLow.p = 1; 50110554Salexandru.dutu@amd.com PFGateLow.dpl = 0; 50210554Salexandru.dutu@amd.com PFGateLow.type = 0xe; // gate interrupt type 50310554Salexandru.dutu@amd.com PFGateLow.IST = 0; // setting IST to 0 and using RSP0 5046609Sgblack@eecs.umich.edu 50510554Salexandru.dutu@amd.com GateDescriptorHigh PFGateHigh = 0; 50610590Sgabeblack@google.com PFGateHigh.offset = bits(PFHandlerVirtAddr, 63, 32); 50710554Salexandru.dutu@amd.com 50810554Salexandru.dutu@amd.com struct { 50910554Salexandru.dutu@amd.com uint64_t low; 51010554Salexandru.dutu@amd.com uint64_t high; 51110554Salexandru.dutu@amd.com } PFGate = {PFGateLow, PFGateHigh}; 51210554Salexandru.dutu@amd.com 51310554Salexandru.dutu@amd.com physProxy.writeBlob(IDTPhysAddr + 0xE0, 51410554Salexandru.dutu@amd.com (uint8_t *)(&PFGate), sizeof(PFGate)); 51510554Salexandru.dutu@amd.com 51610590Sgabeblack@google.com /* System call handler */ 51710554Salexandru.dutu@amd.com uint8_t syscallBlob[] = { 51810590Sgabeblack@google.com // mov %rax, (0xffffc90000005600) 51910590Sgabeblack@google.com 0x48, 0xa3, 0x00, 0x60, 0x00, 52010590Sgabeblack@google.com 0x00, 0x00, 0xc9, 0xff, 0xff, 52110590Sgabeblack@google.com // sysret 52210590Sgabeblack@google.com 0x48, 0x0f, 0x07 52310554Salexandru.dutu@amd.com }; 52410554Salexandru.dutu@amd.com 52510554Salexandru.dutu@amd.com physProxy.writeBlob(syscallCodePhysAddr, 52610554Salexandru.dutu@amd.com syscallBlob, sizeof(syscallBlob)); 52710554Salexandru.dutu@amd.com 52810554Salexandru.dutu@amd.com /** Page fault handler */ 52910554Salexandru.dutu@amd.com uint8_t faultBlob[] = { 53010590Sgabeblack@google.com // mov %rax, (0xffffc90000005700) 53110590Sgabeblack@google.com 0x48, 0xa3, 0x00, 0x61, 0x00, 53210590Sgabeblack@google.com 0x00, 0x00, 0xc9, 0xff, 0xff, 53310590Sgabeblack@google.com // add $0x8, %rsp # skip error 53410590Sgabeblack@google.com 0x48, 0x83, 0xc4, 0x08, 53510590Sgabeblack@google.com // iretq 53610590Sgabeblack@google.com 0x48, 0xcf 53710554Salexandru.dutu@amd.com }; 53810554Salexandru.dutu@amd.com 53910554Salexandru.dutu@amd.com physProxy.writeBlob(PFHandlerPhysAddr, faultBlob, sizeof(faultBlob)); 54010554Salexandru.dutu@amd.com 54110554Salexandru.dutu@amd.com MultiLevelPageTable<PageTableOps> *pt = 54210554Salexandru.dutu@amd.com dynamic_cast<MultiLevelPageTable<PageTableOps> *>(pTable); 54310554Salexandru.dutu@amd.com 54410554Salexandru.dutu@amd.com /* Syscall handler */ 54510554Salexandru.dutu@amd.com pt->map(syscallCodeVirtAddr, syscallCodePhysAddr, PageBytes, false); 54610554Salexandru.dutu@amd.com /* GDT */ 54710554Salexandru.dutu@amd.com pt->map(GDTVirtAddr, GDTPhysAddr, PageBytes, false); 54810554Salexandru.dutu@amd.com /* IDT */ 54910554Salexandru.dutu@amd.com pt->map(IDTVirtAddr, IDTPhysAddr, PageBytes, false); 55010554Salexandru.dutu@amd.com /* TSS */ 55110554Salexandru.dutu@amd.com pt->map(TSSVirtAddr, TSSPhysAddr, PageBytes, false); 55210554Salexandru.dutu@amd.com /* IST */ 55310554Salexandru.dutu@amd.com pt->map(ISTVirtAddr, ISTPhysAddr, PageBytes, false); 55410554Salexandru.dutu@amd.com /* PF handler */ 55510554Salexandru.dutu@amd.com pt->map(PFHandlerVirtAddr, PFHandlerPhysAddr, PageBytes, false); 55610554Salexandru.dutu@amd.com /* MMIO region for m5ops */ 55710554Salexandru.dutu@amd.com pt->map(MMIORegionVirtAddr, MMIORegionPhysAddr, 16*PageBytes, false); 55810554Salexandru.dutu@amd.com } else { 55910554Salexandru.dutu@amd.com for (int i = 0; i < contextIds.size(); i++) { 56010554Salexandru.dutu@amd.com ThreadContext * tc = system->getThreadContext(contextIds[i]); 56110554Salexandru.dutu@amd.com 56210554Salexandru.dutu@amd.com SegAttr dataAttr = 0; 56310554Salexandru.dutu@amd.com dataAttr.dpl = 3; 56410554Salexandru.dutu@amd.com dataAttr.unusable = 0; 56510554Salexandru.dutu@amd.com dataAttr.defaultSize = 1; 56610554Salexandru.dutu@amd.com dataAttr.longMode = 1; 56710554Salexandru.dutu@amd.com dataAttr.avl = 0; 56810554Salexandru.dutu@amd.com dataAttr.granularity = 1; 56910554Salexandru.dutu@amd.com dataAttr.present = 1; 57010554Salexandru.dutu@amd.com dataAttr.type = 3; 57110554Salexandru.dutu@amd.com dataAttr.writable = 1; 57210554Salexandru.dutu@amd.com dataAttr.readable = 1; 57310554Salexandru.dutu@amd.com dataAttr.expandDown = 0; 57410554Salexandru.dutu@amd.com dataAttr.system = 1; 57510554Salexandru.dutu@amd.com 57610554Salexandru.dutu@amd.com //Initialize the segment registers. 57711321Ssteve.reinhardt@amd.com for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) { 57810554Salexandru.dutu@amd.com tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0); 57910554Salexandru.dutu@amd.com tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0); 58010554Salexandru.dutu@amd.com tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr); 58110554Salexandru.dutu@amd.com } 58210554Salexandru.dutu@amd.com 58310554Salexandru.dutu@amd.com SegAttr csAttr = 0; 58410554Salexandru.dutu@amd.com csAttr.dpl = 3; 58510554Salexandru.dutu@amd.com csAttr.unusable = 0; 58610554Salexandru.dutu@amd.com csAttr.defaultSize = 0; 58710554Salexandru.dutu@amd.com csAttr.longMode = 1; 58810554Salexandru.dutu@amd.com csAttr.avl = 0; 58910554Salexandru.dutu@amd.com csAttr.granularity = 1; 59010554Salexandru.dutu@amd.com csAttr.present = 1; 59110554Salexandru.dutu@amd.com csAttr.type = 10; 59210554Salexandru.dutu@amd.com csAttr.writable = 0; 59310554Salexandru.dutu@amd.com csAttr.readable = 1; 59410554Salexandru.dutu@amd.com csAttr.expandDown = 0; 59510554Salexandru.dutu@amd.com csAttr.system = 1; 59610554Salexandru.dutu@amd.com 59710554Salexandru.dutu@amd.com tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr); 59810554Salexandru.dutu@amd.com 59910554Salexandru.dutu@amd.com Efer efer = 0; 60010554Salexandru.dutu@amd.com efer.sce = 1; // Enable system call extensions. 60110554Salexandru.dutu@amd.com efer.lme = 1; // Enable long mode. 60210554Salexandru.dutu@amd.com efer.lma = 1; // Activate long mode. 60310554Salexandru.dutu@amd.com efer.nxe = 1; // Enable nx support. 60410554Salexandru.dutu@amd.com efer.svme = 0; // Disable svm support for now. It isn't implemented. 60510554Salexandru.dutu@amd.com efer.ffxsr = 1; // Turn on fast fxsave and fxrstor. 60610554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_EFER, efer); 60710554Salexandru.dutu@amd.com 60810554Salexandru.dutu@amd.com //Set up the registers that describe the operating mode. 60910554Salexandru.dutu@amd.com CR0 cr0 = 0; 61010554Salexandru.dutu@amd.com cr0.pg = 1; // Turn on paging. 61110554Salexandru.dutu@amd.com cr0.cd = 0; // Don't disable caching. 61210554Salexandru.dutu@amd.com cr0.nw = 0; // This is bit is defined to be ignored. 61310554Salexandru.dutu@amd.com cr0.am = 0; // No alignment checking 61410554Salexandru.dutu@amd.com cr0.wp = 0; // Supervisor mode can write read only pages 61510554Salexandru.dutu@amd.com cr0.ne = 1; 61610554Salexandru.dutu@amd.com cr0.et = 1; // This should always be 1 61710554Salexandru.dutu@amd.com cr0.ts = 0; // We don't do task switching, so causing fp exceptions 61810554Salexandru.dutu@amd.com // would be pointless. 61910554Salexandru.dutu@amd.com cr0.em = 0; // Allow x87 instructions to execute natively. 62010554Salexandru.dutu@amd.com cr0.mp = 1; // This doesn't really matter, but the manual suggests 62110554Salexandru.dutu@amd.com // setting it to one. 62210554Salexandru.dutu@amd.com cr0.pe = 1; // We're definitely in protected mode. 62310554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_CR0, cr0); 62410554Salexandru.dutu@amd.com 62510554Salexandru.dutu@amd.com tc->setMiscReg(MISCREG_MXCSR, 0x1f80); 62610554Salexandru.dutu@amd.com } 6275140Sgblack@eecs.umich.edu } 6284166Sgblack@eecs.umich.edu} 6294166Sgblack@eecs.umich.edu 6304166Sgblack@eecs.umich.eduvoid 63111851Sbrandon.potter@amd.comI386Process::initState() 6324166Sgblack@eecs.umich.edu{ 63311851Sbrandon.potter@amd.com X86Process::initState(); 6345956Sgblack@eecs.umich.edu 63511884Sbrandon.potter@amd.com argsInit(PageBytes); 6365956Sgblack@eecs.umich.edu 63711320Ssteve.reinhardt@amd.com /* 6385962Sgblack@eecs.umich.edu * Set up a GDT for this process. The whole GDT wouldn't really be for 6395962Sgblack@eecs.umich.edu * this process, but the only parts we care about are. 6405962Sgblack@eecs.umich.edu */ 6418601Ssteve.reinhardt@amd.com allocateMem(_gdtStart, _gdtSize); 6425962Sgblack@eecs.umich.edu uint64_t zero = 0; 6435962Sgblack@eecs.umich.edu assert(_gdtSize % sizeof(zero) == 0); 6445962Sgblack@eecs.umich.edu for (Addr gdtCurrent = _gdtStart; 6455962Sgblack@eecs.umich.edu gdtCurrent < _gdtStart + _gdtSize; gdtCurrent += sizeof(zero)) { 6468852Sandreas.hansson@arm.com initVirtMem.write(gdtCurrent, zero); 6475962Sgblack@eecs.umich.edu } 6485962Sgblack@eecs.umich.edu 6495973Sgblack@eecs.umich.edu // Set up the vsyscall page for this process. 6508601Ssteve.reinhardt@amd.com allocateMem(vsyscallPage.base, vsyscallPage.size); 6515973Sgblack@eecs.umich.edu uint8_t vsyscallBlob[] = { 6525973Sgblack@eecs.umich.edu 0x51, // push %ecx 6535973Sgblack@eecs.umich.edu 0x52, // push %edp 6545973Sgblack@eecs.umich.edu 0x55, // push %ebp 6555973Sgblack@eecs.umich.edu 0x89, 0xe5, // mov %esp, %ebp 6565973Sgblack@eecs.umich.edu 0x0f, 0x34 // sysenter 6575973Sgblack@eecs.umich.edu }; 6588852Sandreas.hansson@arm.com initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vsyscallOffset, 6595973Sgblack@eecs.umich.edu vsyscallBlob, sizeof(vsyscallBlob)); 6605973Sgblack@eecs.umich.edu 6615973Sgblack@eecs.umich.edu uint8_t vsysexitBlob[] = { 6625973Sgblack@eecs.umich.edu 0x5d, // pop %ebp 6635973Sgblack@eecs.umich.edu 0x5a, // pop %edx 6645973Sgblack@eecs.umich.edu 0x59, // pop %ecx 6655973Sgblack@eecs.umich.edu 0xc3 // ret 6665973Sgblack@eecs.umich.edu }; 6678852Sandreas.hansson@arm.com initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vsysexitOffset, 6685973Sgblack@eecs.umich.edu vsysexitBlob, sizeof(vsysexitBlob)); 6695973Sgblack@eecs.umich.edu 6705956Sgblack@eecs.umich.edu for (int i = 0; i < contextIds.size(); i++) { 6715956Sgblack@eecs.umich.edu ThreadContext * tc = system->getThreadContext(contextIds[i]); 6725956Sgblack@eecs.umich.edu 6735956Sgblack@eecs.umich.edu SegAttr dataAttr = 0; 6746222Sgblack@eecs.umich.edu dataAttr.dpl = 3; 6756222Sgblack@eecs.umich.edu dataAttr.unusable = 0; 6766222Sgblack@eecs.umich.edu dataAttr.defaultSize = 1; 6776222Sgblack@eecs.umich.edu dataAttr.longMode = 0; 6786222Sgblack@eecs.umich.edu dataAttr.avl = 0; 6796222Sgblack@eecs.umich.edu dataAttr.granularity = 1; 6806222Sgblack@eecs.umich.edu dataAttr.present = 1; 6816222Sgblack@eecs.umich.edu dataAttr.type = 3; 6825956Sgblack@eecs.umich.edu dataAttr.writable = 1; 6835956Sgblack@eecs.umich.edu dataAttr.readable = 1; 6845956Sgblack@eecs.umich.edu dataAttr.expandDown = 0; 6856222Sgblack@eecs.umich.edu dataAttr.system = 1; 6865956Sgblack@eecs.umich.edu 6875956Sgblack@eecs.umich.edu //Initialize the segment registers. 68811321Ssteve.reinhardt@amd.com for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) { 6895956Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0); 6905956Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0); 6915956Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr); 6925956Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_SEG_SEL(seg), 0xB); 6935959Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_SEG_LIMIT(seg), (uint32_t)(-1)); 6945956Sgblack@eecs.umich.edu } 6955956Sgblack@eecs.umich.edu 6965956Sgblack@eecs.umich.edu SegAttr csAttr = 0; 6976222Sgblack@eecs.umich.edu csAttr.dpl = 3; 6986222Sgblack@eecs.umich.edu csAttr.unusable = 0; 6996222Sgblack@eecs.umich.edu csAttr.defaultSize = 1; 7006222Sgblack@eecs.umich.edu csAttr.longMode = 0; 7016222Sgblack@eecs.umich.edu csAttr.avl = 0; 7026222Sgblack@eecs.umich.edu csAttr.granularity = 1; 7036222Sgblack@eecs.umich.edu csAttr.present = 1; 7046222Sgblack@eecs.umich.edu csAttr.type = 0xa; 7055956Sgblack@eecs.umich.edu csAttr.writable = 0; 7065956Sgblack@eecs.umich.edu csAttr.readable = 1; 7075956Sgblack@eecs.umich.edu csAttr.expandDown = 0; 7086222Sgblack@eecs.umich.edu csAttr.system = 1; 7095956Sgblack@eecs.umich.edu 7105956Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr); 7115956Sgblack@eecs.umich.edu 7125962Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TSG_BASE, _gdtStart); 7135962Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TSG_EFF_BASE, _gdtStart); 7145962Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TSG_LIMIT, _gdtStart + _gdtSize - 1); 7155962Sgblack@eecs.umich.edu 7165963Sgblack@eecs.umich.edu // Set the LDT selector to 0 to deactivate it. 7175963Sgblack@eecs.umich.edu tc->setMiscRegNoEffect(MISCREG_TSL, 0); 7185963Sgblack@eecs.umich.edu 7196140Sgblack@eecs.umich.edu Efer efer = 0; 7206140Sgblack@eecs.umich.edu efer.sce = 1; // Enable system call extensions. 7216140Sgblack@eecs.umich.edu efer.lme = 1; // Enable long mode. 7226140Sgblack@eecs.umich.edu efer.lma = 0; // Deactivate long mode. 7236140Sgblack@eecs.umich.edu efer.nxe = 1; // Enable nx support. 7246140Sgblack@eecs.umich.edu efer.svme = 0; // Disable svm support for now. It isn't implemented. 7256140Sgblack@eecs.umich.edu efer.ffxsr = 1; // Turn on fast fxsave and fxrstor. 7266140Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_EFER, efer); 7276140Sgblack@eecs.umich.edu 7285956Sgblack@eecs.umich.edu //Set up the registers that describe the operating mode. 7295956Sgblack@eecs.umich.edu CR0 cr0 = 0; 7305956Sgblack@eecs.umich.edu cr0.pg = 1; // Turn on paging. 7315956Sgblack@eecs.umich.edu cr0.cd = 0; // Don't disable caching. 7325956Sgblack@eecs.umich.edu cr0.nw = 0; // This is bit is defined to be ignored. 7335956Sgblack@eecs.umich.edu cr0.am = 0; // No alignment checking 7345956Sgblack@eecs.umich.edu cr0.wp = 0; // Supervisor mode can write read only pages 7355956Sgblack@eecs.umich.edu cr0.ne = 1; 7365956Sgblack@eecs.umich.edu cr0.et = 1; // This should always be 1 7375956Sgblack@eecs.umich.edu cr0.ts = 0; // We don't do task switching, so causing fp exceptions 7385956Sgblack@eecs.umich.edu // would be pointless. 7395956Sgblack@eecs.umich.edu cr0.em = 0; // Allow x87 instructions to execute natively. 7405956Sgblack@eecs.umich.edu cr0.mp = 1; // This doesn't really matter, but the manual suggests 7415956Sgblack@eecs.umich.edu // setting it to one. 7425956Sgblack@eecs.umich.edu cr0.pe = 1; // We're definitely in protected mode. 7435956Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CR0, cr0); 7446609Sgblack@eecs.umich.edu 7456609Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_MXCSR, 0x1f80); 7465956Sgblack@eecs.umich.edu } 7475956Sgblack@eecs.umich.edu} 7485956Sgblack@eecs.umich.edu 7495956Sgblack@eecs.umich.edutemplate<class IntType> 7505956Sgblack@eecs.umich.eduvoid 75111851Sbrandon.potter@amd.comX86Process::argsInit(int pageSize, 75211884Sbrandon.potter@amd.com std::vector<AuxVector<IntType> > extraAuxvs) 7535956Sgblack@eecs.umich.edu{ 7545956Sgblack@eecs.umich.edu int intSize = sizeof(IntType); 7555956Sgblack@eecs.umich.edu 7565956Sgblack@eecs.umich.edu typedef AuxVector<IntType> auxv_t; 7575973Sgblack@eecs.umich.edu std::vector<auxv_t> auxv = extraAuxvs; 7585758Shsul@eecs.umich.edu 7594166Sgblack@eecs.umich.edu string filename; 76011321Ssteve.reinhardt@amd.com if (argv.size() < 1) 7614166Sgblack@eecs.umich.edu filename = ""; 7624166Sgblack@eecs.umich.edu else 7634166Sgblack@eecs.umich.edu filename = argv[0]; 7644166Sgblack@eecs.umich.edu 7654793Sgblack@eecs.umich.edu //We want 16 byte alignment 7664849Sgblack@eecs.umich.edu uint64_t align = 16; 7674166Sgblack@eecs.umich.edu 76811389Sbrandon.potter@amd.com // Patch the ld_bias for dynamic executables. 76911389Sbrandon.potter@amd.com updateBias(); 77011389Sbrandon.potter@amd.com 7714166Sgblack@eecs.umich.edu // load object file into target memory 7724166Sgblack@eecs.umich.edu objFile->loadSections(initVirtMem); 7734166Sgblack@eecs.umich.edu 7744793Sgblack@eecs.umich.edu enum X86CpuFeature { 7754793Sgblack@eecs.umich.edu X86_OnboardFPU = 1 << 0, 7764793Sgblack@eecs.umich.edu X86_VirtualModeExtensions = 1 << 1, 7774793Sgblack@eecs.umich.edu X86_DebuggingExtensions = 1 << 2, 7784793Sgblack@eecs.umich.edu X86_PageSizeExtensions = 1 << 3, 7794777Sgblack@eecs.umich.edu 7804793Sgblack@eecs.umich.edu X86_TimeStampCounter = 1 << 4, 7814793Sgblack@eecs.umich.edu X86_ModelSpecificRegisters = 1 << 5, 7824793Sgblack@eecs.umich.edu X86_PhysicalAddressExtensions = 1 << 6, 7834793Sgblack@eecs.umich.edu X86_MachineCheckExtensions = 1 << 7, 7844777Sgblack@eecs.umich.edu 7854793Sgblack@eecs.umich.edu X86_CMPXCHG8Instruction = 1 << 8, 7864793Sgblack@eecs.umich.edu X86_OnboardAPIC = 1 << 9, 7874793Sgblack@eecs.umich.edu X86_SYSENTER_SYSEXIT = 1 << 11, 7884793Sgblack@eecs.umich.edu 7894793Sgblack@eecs.umich.edu X86_MemoryTypeRangeRegisters = 1 << 12, 7904793Sgblack@eecs.umich.edu X86_PageGlobalEnable = 1 << 13, 7914793Sgblack@eecs.umich.edu X86_MachineCheckArchitecture = 1 << 14, 7924793Sgblack@eecs.umich.edu X86_CMOVInstruction = 1 << 15, 7934793Sgblack@eecs.umich.edu 7944793Sgblack@eecs.umich.edu X86_PageAttributeTable = 1 << 16, 7954793Sgblack@eecs.umich.edu X86_36BitPSEs = 1 << 17, 7964793Sgblack@eecs.umich.edu X86_ProcessorSerialNumber = 1 << 18, 7974793Sgblack@eecs.umich.edu X86_CLFLUSHInstruction = 1 << 19, 7984793Sgblack@eecs.umich.edu 7994793Sgblack@eecs.umich.edu X86_DebugTraceStore = 1 << 21, 8004793Sgblack@eecs.umich.edu X86_ACPIViaMSR = 1 << 22, 8014793Sgblack@eecs.umich.edu X86_MultimediaExtensions = 1 << 23, 8024793Sgblack@eecs.umich.edu 8034793Sgblack@eecs.umich.edu X86_FXSAVE_FXRSTOR = 1 << 24, 8044793Sgblack@eecs.umich.edu X86_StreamingSIMDExtensions = 1 << 25, 8054793Sgblack@eecs.umich.edu X86_StreamingSIMDExtensions2 = 1 << 26, 8064793Sgblack@eecs.umich.edu X86_CPUSelfSnoop = 1 << 27, 8074793Sgblack@eecs.umich.edu 8084793Sgblack@eecs.umich.edu X86_HyperThreading = 1 << 28, 8094793Sgblack@eecs.umich.edu X86_AutomaticClockControl = 1 << 29, 8104793Sgblack@eecs.umich.edu X86_IA64Processor = 1 << 30 8114166Sgblack@eecs.umich.edu }; 8124166Sgblack@eecs.umich.edu 81311389Sbrandon.potter@amd.com // Setup the auxiliary vectors. These will already have endian 81411389Sbrandon.potter@amd.com // conversion. Auxiliary vectors are loaded only for elf formatted 81511389Sbrandon.potter@amd.com // executables; the auxv is responsible for passing information from 81611389Sbrandon.potter@amd.com // the OS to the interpreter. 8174166Sgblack@eecs.umich.edu ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile); 81810590Sgabeblack@google.com if (elfObject) { 8194793Sgblack@eecs.umich.edu uint64_t features = 8204793Sgblack@eecs.umich.edu X86_OnboardFPU | 8214793Sgblack@eecs.umich.edu X86_VirtualModeExtensions | 8224793Sgblack@eecs.umich.edu X86_DebuggingExtensions | 8234793Sgblack@eecs.umich.edu X86_PageSizeExtensions | 8244793Sgblack@eecs.umich.edu X86_TimeStampCounter | 8254793Sgblack@eecs.umich.edu X86_ModelSpecificRegisters | 8264793Sgblack@eecs.umich.edu X86_PhysicalAddressExtensions | 8274793Sgblack@eecs.umich.edu X86_MachineCheckExtensions | 8284793Sgblack@eecs.umich.edu X86_CMPXCHG8Instruction | 8294793Sgblack@eecs.umich.edu X86_OnboardAPIC | 8304793Sgblack@eecs.umich.edu X86_SYSENTER_SYSEXIT | 8314793Sgblack@eecs.umich.edu X86_MemoryTypeRangeRegisters | 8324793Sgblack@eecs.umich.edu X86_PageGlobalEnable | 8334793Sgblack@eecs.umich.edu X86_MachineCheckArchitecture | 8344793Sgblack@eecs.umich.edu X86_CMOVInstruction | 8354793Sgblack@eecs.umich.edu X86_PageAttributeTable | 8364793Sgblack@eecs.umich.edu X86_36BitPSEs | 8374793Sgblack@eecs.umich.edu// X86_ProcessorSerialNumber | 8384793Sgblack@eecs.umich.edu X86_CLFLUSHInstruction | 8394793Sgblack@eecs.umich.edu// X86_DebugTraceStore | 8404793Sgblack@eecs.umich.edu// X86_ACPIViaMSR | 8414793Sgblack@eecs.umich.edu X86_MultimediaExtensions | 8424793Sgblack@eecs.umich.edu X86_FXSAVE_FXRSTOR | 8434793Sgblack@eecs.umich.edu X86_StreamingSIMDExtensions | 8444793Sgblack@eecs.umich.edu X86_StreamingSIMDExtensions2 | 8454793Sgblack@eecs.umich.edu// X86_CPUSelfSnoop | 8464793Sgblack@eecs.umich.edu// X86_HyperThreading | 8474793Sgblack@eecs.umich.edu// X86_AutomaticClockControl | 8484793Sgblack@eecs.umich.edu// X86_IA64Processor | 8494793Sgblack@eecs.umich.edu 0; 8504793Sgblack@eecs.umich.edu 8514166Sgblack@eecs.umich.edu //Bits which describe the system hardware capabilities 8524777Sgblack@eecs.umich.edu //XXX Figure out what these should be 8534793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_HWCAP, features)); 8544166Sgblack@eecs.umich.edu //The system page size 85510318Sandreas.hansson@arm.com auxv.push_back(auxv_t(M5_AT_PAGESZ, X86ISA::PageBytes)); 8564166Sgblack@eecs.umich.edu //Frequency at which times() increments 8576363Sgblack@eecs.umich.edu //Defined to be 100 in the kernel source. 8584793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_CLKTCK, 100)); 85911389Sbrandon.potter@amd.com // This is the virtual address of the program header tables if they 86011389Sbrandon.potter@amd.com // appear in the executable image. 8614793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable())); 8624166Sgblack@eecs.umich.edu // This is the size of a program header entry from the elf file. 8634793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHENT, elfObject->programHeaderSize())); 8644166Sgblack@eecs.umich.edu // This is the number of program headers from the original elf file. 8654793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PHNUM, elfObject->programHeaderCount())); 86611389Sbrandon.potter@amd.com // This is the base address of the ELF interpreter; it should be 86711389Sbrandon.potter@amd.com // zero for static executables or contain the base address for 86811389Sbrandon.potter@amd.com // dynamic executables. 86911389Sbrandon.potter@amd.com auxv.push_back(auxv_t(M5_AT_BASE, getBias())); 8704777Sgblack@eecs.umich.edu //XXX Figure out what this should be. 8714793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_FLAGS, 0)); 8724166Sgblack@eecs.umich.edu //The entry point to the program 8734793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_ENTRY, objFile->entryPoint())); 8744166Sgblack@eecs.umich.edu //Different user and group IDs 8754793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_UID, uid())); 8764793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_EUID, euid())); 8774793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_GID, gid())); 8784793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_EGID, egid())); 8794166Sgblack@eecs.umich.edu //Whether to enable "secure mode" in the executable 8804793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_SECURE, 0)); 8817073Sgblack@eecs.umich.edu //The address of 16 "random" bytes. 8827073Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_RANDOM, 0)); 8837073Sgblack@eecs.umich.edu //The name of the program 8847073Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_EXECFN, 0)); 8857073Sgblack@eecs.umich.edu //The platform string 8864793Sgblack@eecs.umich.edu auxv.push_back(auxv_t(M5_AT_PLATFORM, 0)); 8874166Sgblack@eecs.umich.edu } 8884166Sgblack@eecs.umich.edu 8894166Sgblack@eecs.umich.edu //Figure out how big the initial stack needs to be 8904166Sgblack@eecs.umich.edu 8914849Sgblack@eecs.umich.edu // A sentry NULL void pointer at the top of the stack. 8924849Sgblack@eecs.umich.edu int sentry_size = intSize; 8934166Sgblack@eecs.umich.edu 8944166Sgblack@eecs.umich.edu //This is the name of the file which is present on the initial stack 8954166Sgblack@eecs.umich.edu //It's purpose is to let the user space linker examine the original file. 8964847Sgblack@eecs.umich.edu int file_name_size = filename.size() + 1; 8974793Sgblack@eecs.umich.edu 8987073Sgblack@eecs.umich.edu const int numRandomBytes = 16; 8997073Sgblack@eecs.umich.edu int aux_data_size = numRandomBytes; 9007073Sgblack@eecs.umich.edu 9014793Sgblack@eecs.umich.edu string platform = "x86_64"; 9027073Sgblack@eecs.umich.edu aux_data_size += platform.size() + 1; 9034166Sgblack@eecs.umich.edu 9044166Sgblack@eecs.umich.edu int env_data_size = 0; 90510590Sgabeblack@google.com for (int i = 0; i < envp.size(); ++i) 9064847Sgblack@eecs.umich.edu env_data_size += envp[i].size() + 1; 9074166Sgblack@eecs.umich.edu int arg_data_size = 0; 90810590Sgabeblack@google.com for (int i = 0; i < argv.size(); ++i) 9094847Sgblack@eecs.umich.edu arg_data_size += argv[i].size() + 1; 9104166Sgblack@eecs.umich.edu 9114166Sgblack@eecs.umich.edu //The info_block needs to be padded so it's size is a multiple of the 9124166Sgblack@eecs.umich.edu //alignment mask. Also, it appears that there needs to be at least some 9134166Sgblack@eecs.umich.edu //padding, so if the size is already a multiple, we need to increase it 9144166Sgblack@eecs.umich.edu //anyway. 9154849Sgblack@eecs.umich.edu int base_info_block_size = 9164849Sgblack@eecs.umich.edu sentry_size + file_name_size + env_data_size + arg_data_size; 9174166Sgblack@eecs.umich.edu 9184849Sgblack@eecs.umich.edu int info_block_size = roundUp(base_info_block_size, align); 9194849Sgblack@eecs.umich.edu 9204849Sgblack@eecs.umich.edu int info_block_padding = info_block_size - base_info_block_size; 9214166Sgblack@eecs.umich.edu 9224166Sgblack@eecs.umich.edu //Each auxilliary vector is two 8 byte words 9234166Sgblack@eecs.umich.edu int aux_array_size = intSize * 2 * (auxv.size() + 1); 9244166Sgblack@eecs.umich.edu 9254166Sgblack@eecs.umich.edu int envp_array_size = intSize * (envp.size() + 1); 9264166Sgblack@eecs.umich.edu int argv_array_size = intSize * (argv.size() + 1); 9274166Sgblack@eecs.umich.edu 9284166Sgblack@eecs.umich.edu int argc_size = intSize; 9294166Sgblack@eecs.umich.edu 9304849Sgblack@eecs.umich.edu //Figure out the size of the contents of the actual initial frame 9314849Sgblack@eecs.umich.edu int frame_size = 9324166Sgblack@eecs.umich.edu aux_array_size + 9334166Sgblack@eecs.umich.edu envp_array_size + 9344166Sgblack@eecs.umich.edu argv_array_size + 9354607Sgblack@eecs.umich.edu argc_size; 9364166Sgblack@eecs.umich.edu 9374849Sgblack@eecs.umich.edu //There needs to be padding after the auxiliary vector data so that the 9384849Sgblack@eecs.umich.edu //very bottom of the stack is aligned properly. 9394849Sgblack@eecs.umich.edu int partial_size = frame_size + aux_data_size; 9404849Sgblack@eecs.umich.edu int aligned_partial_size = roundUp(partial_size, align); 9414849Sgblack@eecs.umich.edu int aux_padding = aligned_partial_size - partial_size; 9424849Sgblack@eecs.umich.edu 9434849Sgblack@eecs.umich.edu int space_needed = 9444849Sgblack@eecs.umich.edu info_block_size + 9454849Sgblack@eecs.umich.edu aux_data_size + 9464849Sgblack@eecs.umich.edu aux_padding + 9474849Sgblack@eecs.umich.edu frame_size; 9484849Sgblack@eecs.umich.edu 9494166Sgblack@eecs.umich.edu stack_min = stack_base - space_needed; 9504849Sgblack@eecs.umich.edu stack_min = roundDown(stack_min, align); 95110554Salexandru.dutu@amd.com stack_size = roundUp(stack_base - stack_min, pageSize); 9524166Sgblack@eecs.umich.edu 9534166Sgblack@eecs.umich.edu // map memory 95410554Salexandru.dutu@amd.com Addr stack_end = roundDown(stack_base - stack_size, pageSize); 95510554Salexandru.dutu@amd.com 95610554Salexandru.dutu@amd.com DPRINTF(Stack, "Mapping the stack: 0x%x %dB\n", stack_end, stack_size); 95710554Salexandru.dutu@amd.com allocateMem(stack_end, stack_size); 9584166Sgblack@eecs.umich.edu 9594166Sgblack@eecs.umich.edu // map out initial stack contents 9605956Sgblack@eecs.umich.edu IntType sentry_base = stack_base - sentry_size; 9615956Sgblack@eecs.umich.edu IntType file_name_base = sentry_base - file_name_size; 9625956Sgblack@eecs.umich.edu IntType env_data_base = file_name_base - env_data_size; 9635956Sgblack@eecs.umich.edu IntType arg_data_base = env_data_base - arg_data_size; 9645956Sgblack@eecs.umich.edu IntType aux_data_base = arg_data_base - info_block_padding - aux_data_size; 9655956Sgblack@eecs.umich.edu IntType auxv_array_base = aux_data_base - aux_array_size - aux_padding; 9665956Sgblack@eecs.umich.edu IntType envp_array_base = auxv_array_base - envp_array_size; 9675956Sgblack@eecs.umich.edu IntType argv_array_base = envp_array_base - argv_array_size; 9685956Sgblack@eecs.umich.edu IntType argc_base = argv_array_base - argc_size; 9694166Sgblack@eecs.umich.edu 9705941Sgblack@eecs.umich.edu DPRINTF(Stack, "The addresses of items on the initial stack:\n"); 9715941Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - file name\n", file_name_base); 9725941Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - env data\n", env_data_base); 9735941Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - arg data\n", arg_data_base); 9745941Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - aux data\n", aux_data_base); 9755941Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base); 9765941Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - envp array\n", envp_array_base); 9775941Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - argv array\n", argv_array_base); 9785941Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - argc \n", argc_base); 9795941Sgblack@eecs.umich.edu DPRINTF(Stack, "0x%x - stack min\n", stack_min); 9804166Sgblack@eecs.umich.edu 9814166Sgblack@eecs.umich.edu // write contents to stack 9824166Sgblack@eecs.umich.edu 9834166Sgblack@eecs.umich.edu // figure out argc 9845956Sgblack@eecs.umich.edu IntType argc = argv.size(); 9855956Sgblack@eecs.umich.edu IntType guestArgc = X86ISA::htog(argc); 9864166Sgblack@eecs.umich.edu 9874849Sgblack@eecs.umich.edu //Write out the sentry void * 9885956Sgblack@eecs.umich.edu IntType sentry_NULL = 0; 9898852Sandreas.hansson@arm.com initVirtMem.writeBlob(sentry_base, 9904849Sgblack@eecs.umich.edu (uint8_t*)&sentry_NULL, sentry_size); 9914166Sgblack@eecs.umich.edu 9924166Sgblack@eecs.umich.edu //Write the file name 9938852Sandreas.hansson@arm.com initVirtMem.writeString(file_name_base, filename.c_str()); 9944166Sgblack@eecs.umich.edu 9957073Sgblack@eecs.umich.edu //Fix up the aux vectors which point to data 9967073Sgblack@eecs.umich.edu assert(auxv[auxv.size() - 3].a_type == M5_AT_RANDOM); 9977073Sgblack@eecs.umich.edu auxv[auxv.size() - 3].a_val = aux_data_base; 9987073Sgblack@eecs.umich.edu assert(auxv[auxv.size() - 2].a_type == M5_AT_EXECFN); 9997073Sgblack@eecs.umich.edu auxv[auxv.size() - 2].a_val = argv_array_base; 10007073Sgblack@eecs.umich.edu assert(auxv[auxv.size() - 1].a_type == M5_AT_PLATFORM); 10017073Sgblack@eecs.umich.edu auxv[auxv.size() - 1].a_val = aux_data_base + numRandomBytes; 10024793Sgblack@eecs.umich.edu 10034166Sgblack@eecs.umich.edu //Copy the aux stuff 100410590Sgabeblack@google.com for (int x = 0; x < auxv.size(); x++) { 10058852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + x * 2 * intSize, 10064166Sgblack@eecs.umich.edu (uint8_t*)&(auxv[x].a_type), intSize); 10078852Sandreas.hansson@arm.com initVirtMem.writeBlob(auxv_array_base + (x * 2 + 1) * intSize, 10084166Sgblack@eecs.umich.edu (uint8_t*)&(auxv[x].a_val), intSize); 10094166Sgblack@eecs.umich.edu } 10104166Sgblack@eecs.umich.edu //Write out the terminating zeroed auxilliary vector 10114166Sgblack@eecs.umich.edu const uint64_t zero = 0; 101211326Ssteve.reinhardt@amd.com initVirtMem.writeBlob(auxv_array_base + auxv.size() * 2 * intSize, 101311326Ssteve.reinhardt@amd.com (uint8_t*)&zero, intSize); 101411326Ssteve.reinhardt@amd.com initVirtMem.writeBlob(auxv_array_base + (auxv.size() * 2 + 1) * intSize, 101511326Ssteve.reinhardt@amd.com (uint8_t*)&zero, intSize); 10164166Sgblack@eecs.umich.edu 10178852Sandreas.hansson@arm.com initVirtMem.writeString(aux_data_base, platform.c_str()); 10184793Sgblack@eecs.umich.edu 10194166Sgblack@eecs.umich.edu copyStringArray(envp, envp_array_base, env_data_base, initVirtMem); 10204166Sgblack@eecs.umich.edu copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem); 10214166Sgblack@eecs.umich.edu 10228852Sandreas.hansson@arm.com initVirtMem.writeBlob(argc_base, (uint8_t*)&guestArgc, intSize); 10234166Sgblack@eecs.umich.edu 10245713Shsul@eecs.umich.edu ThreadContext *tc = system->getThreadContext(contextIds[0]); 10254793Sgblack@eecs.umich.edu //Set the stack pointer register 10265713Shsul@eecs.umich.edu tc->setIntReg(StackPointerReg, stack_min); 10274166Sgblack@eecs.umich.edu 10285246Sgblack@eecs.umich.edu // There doesn't need to be any segment base added in since we're dealing 10295246Sgblack@eecs.umich.edu // with the flat segmentation model. 103011389Sbrandon.potter@amd.com tc->pcState(getStartPC()); 10314166Sgblack@eecs.umich.edu 10324166Sgblack@eecs.umich.edu //Align the "stack_min" to a page boundary. 10334166Sgblack@eecs.umich.edu stack_min = roundDown(stack_min, pageSize); 10344166Sgblack@eecs.umich.edu} 10355956Sgblack@eecs.umich.edu 10365956Sgblack@eecs.umich.eduvoid 103711884Sbrandon.potter@amd.comX86_64Process::argsInit(int pageSize) 10385956Sgblack@eecs.umich.edu{ 10395973Sgblack@eecs.umich.edu std::vector<AuxVector<uint64_t> > extraAuxvs; 10407073Sgblack@eecs.umich.edu extraAuxvs.push_back(AuxVector<uint64_t>(M5_AT_SYSINFO_EHDR, 10417073Sgblack@eecs.umich.edu vsyscallPage.base)); 104211851Sbrandon.potter@amd.com X86Process::argsInit<uint64_t>(pageSize, extraAuxvs); 10435956Sgblack@eecs.umich.edu} 10445956Sgblack@eecs.umich.edu 10455956Sgblack@eecs.umich.eduvoid 104611884Sbrandon.potter@amd.comI386Process::argsInit(int pageSize) 10475956Sgblack@eecs.umich.edu{ 10485973Sgblack@eecs.umich.edu std::vector<AuxVector<uint32_t> > extraAuxvs; 10495973Sgblack@eecs.umich.edu //Tell the binary where the vsyscall part of the vsyscall page is. 10507073Sgblack@eecs.umich.edu extraAuxvs.push_back(AuxVector<uint32_t>(M5_AT_SYSINFO, 10515973Sgblack@eecs.umich.edu vsyscallPage.base + vsyscallPage.vsyscallOffset)); 10527073Sgblack@eecs.umich.edu extraAuxvs.push_back(AuxVector<uint32_t>(M5_AT_SYSINFO_EHDR, 10537073Sgblack@eecs.umich.edu vsyscallPage.base)); 105411851Sbrandon.potter@amd.com X86Process::argsInit<uint32_t>(pageSize, extraAuxvs); 10555956Sgblack@eecs.umich.edu} 10565958Sgblack@eecs.umich.edu 10575958Sgblack@eecs.umich.eduvoid 105811851Sbrandon.potter@amd.comX86Process::setSyscallReturn(ThreadContext *tc, SyscallReturn retval) 10595958Sgblack@eecs.umich.edu{ 106010223Ssteve.reinhardt@amd.com tc->setIntReg(INTREG_RAX, retval.encodedValue()); 10615958Sgblack@eecs.umich.edu} 10625958Sgblack@eecs.umich.edu 10635958Sgblack@eecs.umich.eduX86ISA::IntReg 106411851Sbrandon.potter@amd.comX86_64Process::getSyscallArg(ThreadContext *tc, int &i) 10655958Sgblack@eecs.umich.edu{ 10665958Sgblack@eecs.umich.edu assert(i < NumArgumentRegs); 10676701Sgblack@eecs.umich.edu return tc->readIntReg(ArgumentReg[i++]); 10685958Sgblack@eecs.umich.edu} 10695958Sgblack@eecs.umich.edu 10705958Sgblack@eecs.umich.eduvoid 107111851Sbrandon.potter@amd.comX86_64Process::setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val) 10725958Sgblack@eecs.umich.edu{ 10735958Sgblack@eecs.umich.edu assert(i < NumArgumentRegs); 10745958Sgblack@eecs.umich.edu return tc->setIntReg(ArgumentReg[i], val); 10755958Sgblack@eecs.umich.edu} 10765958Sgblack@eecs.umich.edu 10775958Sgblack@eecs.umich.eduX86ISA::IntReg 107811851Sbrandon.potter@amd.comI386Process::getSyscallArg(ThreadContext *tc, int &i) 10795958Sgblack@eecs.umich.edu{ 10805959Sgblack@eecs.umich.edu assert(i < NumArgumentRegs32); 10816701Sgblack@eecs.umich.edu return tc->readIntReg(ArgumentReg32[i++]); 10826701Sgblack@eecs.umich.edu} 10836701Sgblack@eecs.umich.edu 10846701Sgblack@eecs.umich.eduX86ISA::IntReg 108511851Sbrandon.potter@amd.comI386Process::getSyscallArg(ThreadContext *tc, int &i, int width) 10866701Sgblack@eecs.umich.edu{ 10876701Sgblack@eecs.umich.edu assert(width == 32 || width == 64); 10886701Sgblack@eecs.umich.edu assert(i < NumArgumentRegs); 10896701Sgblack@eecs.umich.edu uint64_t retVal = tc->readIntReg(ArgumentReg32[i++]) & mask(32); 10906701Sgblack@eecs.umich.edu if (width == 64) 10916701Sgblack@eecs.umich.edu retVal |= ((uint64_t)tc->readIntReg(ArgumentReg[i++]) << 32); 10926701Sgblack@eecs.umich.edu return retVal; 10935958Sgblack@eecs.umich.edu} 10945958Sgblack@eecs.umich.edu 10955958Sgblack@eecs.umich.eduvoid 109611851Sbrandon.potter@amd.comI386Process::setSyscallArg(ThreadContext *tc, int i, X86ISA::IntReg val) 10975958Sgblack@eecs.umich.edu{ 10985959Sgblack@eecs.umich.edu assert(i < NumArgumentRegs); 10995959Sgblack@eecs.umich.edu return tc->setIntReg(ArgumentReg[i], val); 11005958Sgblack@eecs.umich.edu} 1101