xref: /gem5/src/arch/x86/mmapped_ipr.hh

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 * Authors: Gabe Black
 */

#ifndef __ARCH_X86_MMAPEDIPR_HH__
#define __ARCH_X86_MMAPEDIPR_HH__

/**
 * @file
 *
 * ISA-specific helper functions for memory mapped IPR accesses.
 */

#include "arch/x86/miscregs.hh"
#include "config/full_system.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "mem/packet.hh"

namespace X86ISA
{
    inline Tick
    handleIprRead(ThreadContext *xc, Packet *pkt)
    {
#if !FULL_SYSTEM
        panic("Shouldn't have a memory mapped register in SE\n");
#else
        Addr offset = pkt->getAddr() & mask(3);
        MiscRegIndex index = (MiscRegIndex)(pkt->getAddr() / sizeof(MiscReg));
        MiscReg data = htog(xc->readMiscReg(index));
        // Make sure we don't trot off the end of data.
        assert(offset + pkt->getSize() <= sizeof(MiscReg));
        pkt->setData(((uint8_t *)&data) + offset);
#endif
        return xc->getCpuPtr()->ticks(1);
    }

    inline Tick
    handleIprWrite(ThreadContext *xc, Packet *pkt)
    {
#if !FULL_SYSTEM
        panic("Shouldn't have a memory mapped register in SE\n");
#else
        Addr offset = pkt->getAddr() & mask(3);
        MiscRegIndex index = (MiscRegIndex)(pkt->getAddr() / sizeof(MiscReg));
        MiscReg data = htog(xc->readMiscRegNoEffect(index));
        // Make sure we don't trot off the end of data.
        assert(offset + pkt->getSize() <= sizeof(MiscReg));
        pkt->writeData(((uint8_t *)&data) + offset);
        xc->setMiscReg(index, gtoh(data));
#endif
        return xc->getCpuPtr()->ticks(1);
    }
};

#endif // __ARCH_X86_MMAPEDIPR_HH__