mmapped_ipr.hh revision 4152
12292SN/A/*
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422292SN/A *
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548232Snate@binkert.org *
558232Snate@binkert.org * Authors: Gabe Black
568232Snate@binkert.org */
576221Snate@binkert.org
582292SN/A#ifndef __ARCH_X86_MMAPEDIPR_HH__
596221Snate@binkert.org#define __ARCH_X86_MMAPEDIPR_HH__
605529Snate@binkert.org
612292SN/A/**
625529Snate@binkert.org * @file
638707Sandreas.hansson@arm.com *
6413560Snikos.nikoleris@arm.com * ISA-specific helper functions for memory mapped IPR accesses.
654329Sktlim@umich.edu */
664329Sktlim@umich.edu
6713472Srekai.gonzalezalberquilla@arm.com#include "config/full_system.hh"
6813472Srekai.gonzalezalberquilla@arm.com#include "cpu/thread_context.hh"
6913472Srekai.gonzalezalberquilla@arm.com#include "mem/packet.hh"
7013472Srekai.gonzalezalberquilla@arm.com
7110333Smitch.hayenga@arm.comnamespace X86ISA
722292SN/A{
739868Sjthestness@gmail.com    inline Tick
749868Sjthestness@gmail.com    handleIprRead(ThreadContext *xc, Packet *pkt)
752292SN/A    {
762292SN/A#if !FULL_SYSTEM
772292SN/A        panic("Shouldn't have a memory mapped register in SE\n");
782292SN/A#endif
792292SN/A    }
8013560Snikos.nikoleris@arm.com
812292SN/A    inline Tick
8213560Snikos.nikoleris@arm.com    handleIprWrite(ThreadContext *xc, Packet *pkt)
832292SN/A    {
848346Sksewell@umich.edu#if !FULL_SYSTEM
852292SN/A        panic("Shouldn't have a memory mapped register in SE\n");
8613560Snikos.nikoleris@arm.com#endif
872292SN/A    }
882292SN/A};
892292SN/A
902292SN/A#endif // __ARCH_X86_MMAPEDIPR_HH__
912292SN/A