mmapped_ipr.hh revision 4152
16145Snate@binkert.org/*
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556145Snate@binkert.org * Authors: Gabe Black
568259SBrad.Beckmann@amd.com */
577054Snate@binkert.org
586145Snate@binkert.org#ifndef __ARCH_X86_MMAPEDIPR_HH__
596145Snate@binkert.org#define __ARCH_X86_MMAPEDIPR_HH__
609499Snilay@cs.wisc.edu
619230Snilay@cs.wisc.edu/**
629465Snilay@cs.wisc.edu * @file
639230Snilay@cs.wisc.edu *
646145Snate@binkert.org * ISA-specific helper functions for memory mapped IPR accesses.
658259SBrad.Beckmann@amd.com */
667054Snate@binkert.org
676145Snate@binkert.org#include "config/full_system.hh"
686145Snate@binkert.org#include "cpu/thread_context.hh"
697054Snate@binkert.org#include "mem/packet.hh"
709499Snilay@cs.wisc.edu
719499Snilay@cs.wisc.edunamespace X86ISA
726145Snate@binkert.org{
737054Snate@binkert.org    inline Tick
747054Snate@binkert.org    handleIprRead(ThreadContext *xc, Packet *pkt)
756145Snate@binkert.org    {
767832Snate@binkert.org#if !FULL_SYSTEM
777054Snate@binkert.org        panic("Shouldn't have a memory mapped register in SE\n");
787054Snate@binkert.org#endif
798259SBrad.Beckmann@amd.com    }
806145Snate@binkert.org
817054Snate@binkert.org    inline Tick
826145Snate@binkert.org    handleIprWrite(ThreadContext *xc, Packet *pkt)
839863Snilay@cs.wisc.edu    {
846145Snate@binkert.org#if !FULL_SYSTEM
856145Snate@binkert.org        panic("Shouldn't have a memory mapped register in SE\n");
867054Snate@binkert.org#endif
877454Snate@binkert.org    }
889508Snilay@cs.wisc.edu};
896145Snate@binkert.org
907054Snate@binkert.org#endif // __ARCH_X86_MMAPEDIPR_HH__
917054Snate@binkert.org