mmapped_ipr.hh revision 13613
12SN/A/*
21762SN/A * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
35502Snate@binkert.org * All rights reserved.
42SN/A *
52SN/A * The license below extends only to copyright in the software and shall
62SN/A * not be construed as granting a license to any other intellectual
72SN/A * property including but not limited to intellectual property relating
82SN/A * to a hardware implementation of the functionality of the software
92SN/A * licensed hereunder.  You may use the software subject to the license
102SN/A * terms below provided that you ensure that this notice is replicated
112SN/A * unmodified and in its entirety in all distributions of the software,
122SN/A * modified or unmodified, in source code or in binary form.
132SN/A *
142SN/A * Redistribution and use in source and binary forms, with or without
152SN/A * modification, are permitted provided that the following conditions are
162SN/A * met: redistributions of source code must retain the above copyright
172SN/A * notice, this list of conditions and the following disclaimer;
182SN/A * redistributions in binary form must reproduce the above copyright
192SN/A * notice, this list of conditions and the following disclaimer in the
202SN/A * documentation and/or other materials provided with the distribution;
212SN/A * neither the name of the copyright holders nor the names of its
222SN/A * contributors may be used to endorse or promote products derived from
232SN/A * this software without specific prior written permission.
242SN/A *
252SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
262SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
272SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
282665Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
292665Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
302665Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
312665Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
322SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
332SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
345501Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
352SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
362SN/A *
372SN/A * Authors: Gabe Black
382SN/A */
395502Snate@binkert.org
405501Snate@binkert.org#ifndef __ARCH_X86_MMAPPEDIPR_HH__
415501Snate@binkert.org#define __ARCH_X86_MMAPPEDIPR_HH__
421717SN/A
435501Snate@binkert.org/**
4456SN/A * @file
452SN/A *
462SN/A * ISA-specific helper functions for memory mapped IPR accesses.
472SN/A */
482SN/A
492SN/A#include "arch/generic/mmapped_ipr.hh"
502SN/A#include "arch/x86/regs/misc.hh"
512SN/A#include "cpu/base.hh"
522SN/A#include "cpu/thread_context.hh"
532SN/A#include "mem/packet.hh"
545605Snate@binkert.org
552SN/Anamespace X86ISA
564017Sstever@eecs.umich.edu{
574016Sstever@eecs.umich.edu    inline Cycles
584017Sstever@eecs.umich.edu    handleIprRead(ThreadContext *xc, Packet *pkt)
594016Sstever@eecs.umich.edu    {
605768Snate@binkert.org        if (GenericISA::isGenericIprAccess(pkt)) {
615768Snate@binkert.org            return GenericISA::handleGenericIprRead(xc, pkt);
625774Snate@binkert.org        } else {
635768Snate@binkert.org            Addr offset = pkt->getAddr() & mask(3);
645768Snate@binkert.org            MiscRegIndex index = (MiscRegIndex)(
655768Snate@binkert.org                pkt->getAddr() / sizeof(RegVal));
665768Snate@binkert.org            RegVal data = htog(xc->readMiscReg(index));
675768Snate@binkert.org            // Make sure we don't trot off the end of data.
685768Snate@binkert.org            assert(offset + pkt->getSize() <= sizeof(RegVal));
695768Snate@binkert.org            pkt->setData(((uint8_t *)&data) + offset);
705768Snate@binkert.org            return Cycles(1);
715768Snate@binkert.org        }
725768Snate@binkert.org    }
735768Snate@binkert.org
745768Snate@binkert.org    inline Cycles
755768Snate@binkert.org    handleIprWrite(ThreadContext *xc, Packet *pkt)
765602Snate@binkert.org    {
775602Snate@binkert.org        if (GenericISA::isGenericIprAccess(pkt)) {
785502Snate@binkert.org            return GenericISA::handleGenericIprWrite(xc, pkt);
795503Snate@binkert.org        } else {
805502Snate@binkert.org            Addr offset = pkt->getAddr() & mask(3);
815502Snate@binkert.org            MiscRegIndex index = (MiscRegIndex)(
825502Snate@binkert.org                pkt->getAddr() / sizeof(RegVal));
835502Snate@binkert.org            RegVal data = htog(xc->readMiscRegNoEffect(index));
845502Snate@binkert.org            // Make sure we don't trot off the end of data.
855503Snate@binkert.org            assert(offset + pkt->getSize() <= sizeof(RegVal));
865502Snate@binkert.org            pkt->writeData(((uint8_t *)&data) + offset);
875502Snate@binkert.org            xc->setMiscReg(index, gtoh(data));
885502Snate@binkert.org            return Cycles(1);
895502Snate@binkert.org        }
905503Snate@binkert.org    }
915503Snate@binkert.org}
925503Snate@binkert.org
935502Snate@binkert.org#endif // __ARCH_X86_MMAPPEDIPR_HH__
945503Snate@binkert.org