memhelpers.hh revision 11328:9512d2e25f14 
1/*
2 * Copyright (c) 2011 Google
3 * Copyright (c) 2015 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 */
31
32#ifndef __ARCH_X86_MEMHELPERS_HH__
33#define __ARCH_X86_MEMHELPERS_HH__
34
35#include <array>
36
37#include "base/types.hh"
38#include "sim/byteswap.hh"
39#include "sim/insttracer.hh"
40
41namespace X86ISA
42{
43
44/// Initiate a read from memory in timing mode.
45template <class XC>
46Fault
47initiateMemRead(XC *xc, Trace::InstRecord *traceData, Addr addr,
48                unsigned dataSize, unsigned flags)
49{
50    return xc->initiateMemRead(addr, dataSize, flags);
51}
52
53static void
54getMem(PacketPtr pkt, uint64_t &mem, unsigned dataSize,
55       Trace::InstRecord *traceData)
56{
57    switch (dataSize) {
58      case 1:
59        mem = pkt->get<uint8_t>();
60        break;
61      case 2:
62        mem = pkt->get<uint16_t>();
63        break;
64      case 4:
65        mem = pkt->get<uint32_t>();
66        break;
67      case 8:
68        mem = pkt->get<uint64_t>();
69        break;
70      default:
71        panic("Unhandled size in getMem.\n");
72    }
73    if (traceData)
74        traceData->setData(mem);
75}
76
77
78template <size_t N>
79void
80getMem(PacketPtr pkt, std::array<uint64_t, N> &mem, unsigned dataSize,
81       Trace::InstRecord *traceData)
82{
83    assert(dataSize >= 8);
84    assert((dataSize % 8) == 0);
85
86    int num_words = dataSize / 8;
87    assert(num_words <= N);
88
89    auto pkt_data = pkt->getConstPtr<const uint64_t>();
90    for (int i = 0; i < num_words; ++i)
91        mem[i] = gtoh(pkt_data[i]);
92
93    // traceData record only has space for 64 bits, so we just record
94    // the first qword
95    if (traceData)
96        traceData->setData(mem[0]);
97}
98
99
100template <class XC>
101Fault
102readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, uint64_t &mem,
103        unsigned dataSize, unsigned flags)
104{
105    memset(&mem, 0, sizeof(mem));
106    Fault fault = xc->readMem(addr, (uint8_t *)&mem, dataSize, flags);
107    if (fault == NoFault) {
108        // If LE to LE, this is a nop, if LE to BE, the actual data ends up
109        // in the right place because the LSBs where at the low addresses on
110        // access. This doesn't work for BE guests.
111        mem = gtoh(mem);
112        if (traceData)
113            traceData->setData(mem);
114    }
115    return fault;
116}
117
118template <class XC, size_t N>
119Fault
120readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr,
121              std::array<uint64_t, N> &mem, unsigned dataSize,
122              unsigned flags)
123{
124    assert(dataSize >= 8);
125    assert((dataSize % 8) == 0);
126
127    Fault fault = xc->readMem(addr, (uint8_t *)&mem, dataSize, flags);
128
129    if (fault == NoFault) {
130        int num_words = dataSize / 8;
131        assert(num_words <= N);
132
133        for (int i = 0; i < num_words; ++i)
134            mem[i] = gtoh(mem[i]);
135
136        if (traceData)
137            traceData->setData(mem[0]);
138    }
139    return fault;
140}
141
142template <class XC>
143Fault
144writeMemTiming(XC *xc, Trace::InstRecord *traceData, uint64_t mem,
145        unsigned dataSize, Addr addr, unsigned flags, uint64_t *res)
146{
147    if (traceData) {
148        traceData->setData(mem);
149    }
150    mem = TheISA::htog(mem);
151    return xc->writeMem((uint8_t *)&mem, dataSize, addr, flags, res);
152}
153
154template <class XC, size_t N>
155Fault
156writeMemTiming(XC *xc, Trace::InstRecord *traceData,
157               std::array<uint64_t, N> &mem, unsigned dataSize,
158               Addr addr, unsigned flags, uint64_t *res)
159{
160    assert(dataSize >= 8);
161    assert((dataSize % 8) == 0);
162
163    if (traceData) {
164        traceData->setData(mem[0]);
165    }
166
167    int num_words = dataSize / 8;
168    assert(num_words <= N);
169
170    for (int i = 0; i < num_words; ++i)
171        mem[i] = htog(mem[i]);
172
173    return xc->writeMem((uint8_t *)&mem, dataSize, addr, flags, res);
174}
175
176template <class XC>
177Fault
178writeMemAtomic(XC *xc, Trace::InstRecord *traceData, uint64_t mem,
179        unsigned dataSize, Addr addr, unsigned flags, uint64_t *res)
180{
181    if (traceData) {
182        traceData->setData(mem);
183    }
184    uint64_t host_mem = TheISA::htog(mem);
185    Fault fault =
186          xc->writeMem((uint8_t *)&host_mem, dataSize, addr, flags, res);
187    if (fault == NoFault && res != NULL) {
188        *res = gtoh(*res);
189    }
190    return fault;
191}
192
193template <class XC, size_t N>
194Fault
195writeMemAtomic(XC *xc, Trace::InstRecord *traceData,
196               std::array<uint64_t, N> &mem, unsigned dataSize,
197               Addr addr, unsigned flags, uint64_t *res)
198{
199    if (traceData) {
200        traceData->setData(mem[0]);
201    }
202
203    int num_words = dataSize / 8;
204    assert(num_words <= N);
205
206    for (int i = 0; i < num_words; ++i)
207        mem[i] = htog(mem[i]);
208
209    Fault fault = xc->writeMem((uint8_t *)&mem, dataSize, addr, flags, res);
210
211    if (fault == NoFault && res != NULL) {
212        *res = gtoh(*res);
213    }
214
215    return fault;
216}
217
218}
219
220#endif
221