isa_traits.hh revision 5086
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IN NO EVENT SHALL THE COPYRIGHT 474309Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 484309Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 494309Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 504309Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 514309Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 524309Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 534309Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 544309Sgblack@eecs.umich.edu * 554309Sgblack@eecs.umich.edu * Authors: Gabe Black 564309Sgblack@eecs.umich.edu */ 574309Sgblack@eecs.umich.edu 584309Sgblack@eecs.umich.edu#ifndef __ARCH_X86_ISATRAITS_HH__ 594309Sgblack@eecs.umich.edu#define __ARCH_X86_ISATRAITS_HH__ 604309Sgblack@eecs.umich.edu 614309Sgblack@eecs.umich.edu#include "arch/x86/intregs.hh" 624309Sgblack@eecs.umich.edu#include "arch/x86/types.hh" 634309Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh" 644309Sgblack@eecs.umich.edu#include "sim/host.hh" 654309Sgblack@eecs.umich.edu 664309Sgblack@eecs.umich.educlass StaticInstPtr; 674309Sgblack@eecs.umich.edu 684309Sgblack@eecs.umich.edunamespace LittleEndianGuest {} 694309Sgblack@eecs.umich.edu 704323Sgblack@eecs.umich.edunamespace X86ISA 714323Sgblack@eecs.umich.edu{ 724323Sgblack@eecs.umich.edu //This makes sure the little endian version of certain functions 734323Sgblack@eecs.umich.edu //are used. 744323Sgblack@eecs.umich.edu using namespace LittleEndianGuest; 754323Sgblack@eecs.umich.edu 764323Sgblack@eecs.umich.edu // X86 does not have a delay slot 774323Sgblack@eecs.umich.edu#define ISA_HAS_DELAY_SLOT 0 784323Sgblack@eecs.umich.edu 794323Sgblack@eecs.umich.edu // X86 NOP (XCHG rAX, rAX) 804323Sgblack@eecs.umich.edu //XXX This needs to be set to an intermediate instruction struct 814323Sgblack@eecs.umich.edu //which encodes this instruction 824309Sgblack@eecs.umich.edu 834309Sgblack@eecs.umich.edu // These enumerate all the registers for dependence tracking. 844309Sgblack@eecs.umich.edu enum DependenceTags { 854309Sgblack@eecs.umich.edu //There are 16 microcode registers at the moment. This is an 864309Sgblack@eecs.umich.edu //unusually large constant to make sure there isn't overflow. 874309Sgblack@eecs.umich.edu FP_Base_DepTag = 128, 884309Sgblack@eecs.umich.edu Ctrl_Base_DepTag = 894323Sgblack@eecs.umich.edu FP_Base_DepTag + 904309Sgblack@eecs.umich.edu //mmx/x87 registers 914323Sgblack@eecs.umich.edu 8 + 924323Sgblack@eecs.umich.edu //xmm registers 934323Sgblack@eecs.umich.edu 16 + 944309Sgblack@eecs.umich.edu //The indices that are mapped over the fp stack 954323Sgblack@eecs.umich.edu 8 964323Sgblack@eecs.umich.edu }; 974323Sgblack@eecs.umich.edu 984323Sgblack@eecs.umich.edu // semantically meaningful register indices 994323Sgblack@eecs.umich.edu //There is no such register in X86 1004323Sgblack@eecs.umich.edu const int ZeroReg = NUM_INTREGS; 1014323Sgblack@eecs.umich.edu const int StackPointerReg = INTREG_RSP; 1024323Sgblack@eecs.umich.edu //X86 doesn't seem to have a link register 1034323Sgblack@eecs.umich.edu const int ReturnAddressReg = 0; 1044309Sgblack@eecs.umich.edu const int ReturnValueReg = INTREG_RAX; 1054309Sgblack@eecs.umich.edu const int FramePointerReg = INTREG_RBP; 1064309Sgblack@eecs.umich.edu const int ArgumentReg[] = { 1074309Sgblack@eecs.umich.edu INTREG_RDI, 1084309Sgblack@eecs.umich.edu INTREG_RSI, 1094309Sgblack@eecs.umich.edu INTREG_RDX, 1104309Sgblack@eecs.umich.edu //This argument register is r10 for syscalls and rcx for C. 1114309Sgblack@eecs.umich.edu INTREG_R10W, 1124309Sgblack@eecs.umich.edu //INTREG_RCX, 1134309Sgblack@eecs.umich.edu INTREG_R8W, 1144309Sgblack@eecs.umich.edu INTREG_R9W 1154309Sgblack@eecs.umich.edu }; 1164309Sgblack@eecs.umich.edu const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int); 1174309Sgblack@eecs.umich.edu 1184309Sgblack@eecs.umich.edu // Some OS syscalls use a second register (rdx) to return a second 1194309Sgblack@eecs.umich.edu // value 1204309Sgblack@eecs.umich.edu const int SyscallPseudoReturnReg = INTREG_RDX; 1214309Sgblack@eecs.umich.edu 1224309Sgblack@eecs.umich.edu //XXX These numbers are bogus 1234309Sgblack@eecs.umich.edu const int MaxInstSrcRegs = 10; 1244309Sgblack@eecs.umich.edu const int MaxInstDestRegs = 10; 1254309Sgblack@eecs.umich.edu 1264309Sgblack@eecs.umich.edu //4k. This value is not constant on x86. 1274309Sgblack@eecs.umich.edu const int LogVMPageSize = 12; 1284309Sgblack@eecs.umich.edu const int VMPageSize = (1 << LogVMPageSize); 1294309Sgblack@eecs.umich.edu 1304309Sgblack@eecs.umich.edu const int PageShift = 13; 1314309Sgblack@eecs.umich.edu const int PageBytes = 1ULL << PageShift; 1324309Sgblack@eecs.umich.edu 1334309Sgblack@eecs.umich.edu const int BranchPredAddrShiftAmt = 0; 1344309Sgblack@eecs.umich.edu 1354323Sgblack@eecs.umich.edu StaticInstPtr decodeInst(ExtMachInst); 1364323Sgblack@eecs.umich.edu 1374309Sgblack@eecs.umich.edu const Addr LoadAddrMask = ULL(0xffffffffff); 1384309Sgblack@eecs.umich.edu}; 1394309Sgblack@eecs.umich.edu 1404309Sgblack@eecs.umich.edu#endif // __ARCH_X86_ISATRAITS_HH__ 1414309Sgblack@eecs.umich.edu