isa_traits.hh revision 5063:8eb72b1bd3c6
12SN/A/* 21762SN/A * Copyright (c) 2007 The Hewlett-Packard Development Company 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use of this software in source and binary forms, 62SN/A * with or without modification, are permitted provided that the 72SN/A * following conditions are met: 82SN/A * 92SN/A * The software must be used only for Non-Commercial Use which means any 102SN/A * use which is NOT directed to receiving any direct monetary 112SN/A * compensation for, or commercial advantage from such use. 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IN NO EVENT SHALL THE COPYRIGHT 472SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 4856SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 492361SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 501354SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 5156SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 522SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 532SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 542SN/A * 551354SN/A * Authors: Gabe Black 561354SN/A */ 571354SN/A 581354SN/A#ifndef __ARCH_X86_ISATRAITS_HH__ 591354SN/A#define __ARCH_X86_ISATRAITS_HH__ 601354SN/A 611354SN/A#include "arch/x86/intregs.hh" 621354SN/A#include "arch/x86/types.hh" 631354SN/A#include "arch/x86/x86_traits.hh" 641354SN/A 651354SN/Aclass StaticInstPtr; 661354SN/A 671354SN/Anamespace LittleEndianGuest {} 682SN/A 692SN/Anamespace X86ISA 702SN/A{ 712SN/A //This makes sure the little endian version of certain functions 722SN/A //are used. 73395SN/A using namespace LittleEndianGuest; 742SN/A 752SN/A // X86 does not have a delay slot 762SN/A#define ISA_HAS_DELAY_SLOT 0 772SN/A 784016Sstever@eecs.umich.edu // X86 NOP (XCHG rAX, rAX) 794016Sstever@eecs.umich.edu //XXX This needs to be set to an intermediate instruction struct 804016Sstever@eecs.umich.edu //which encodes this instruction 814016Sstever@eecs.umich.edu 824016Sstever@eecs.umich.edu // These enumerate all the registers for dependence tracking. 834016Sstever@eecs.umich.edu enum DependenceTags { 844016Sstever@eecs.umich.edu //There are 16 microcode registers at the moment. This is an 854016Sstever@eecs.umich.edu //unusually large constant to make sure there isn't overflow. 864016Sstever@eecs.umich.edu FP_Base_DepTag = 128, 874016Sstever@eecs.umich.edu Ctrl_Base_DepTag = 884016Sstever@eecs.umich.edu FP_Base_DepTag + 894016Sstever@eecs.umich.edu //mmx/x87 registers 902SN/A 8 + 912SN/A //xmm registers 922SN/A 16 932SN/A }; 942SN/A 952SN/A // semantically meaningful register indices 962SN/A //There is no such register in X86 972SN/A const int ZeroReg = NUM_INTREGS; 982SN/A const int StackPointerReg = INTREG_RSP; 992SN/A //X86 doesn't seem to have a link register 1002SN/A const int ReturnAddressReg = 0; 1012SN/A const int ReturnValueReg = INTREG_RAX; 1022SN/A const int FramePointerReg = INTREG_RBP; 1032SN/A const int ArgumentReg[] = { 1042SN/A INTREG_RDI, 105237SN/A INTREG_RSI, 1062667Sstever@eecs.umich.edu INTREG_RDX, 1072667Sstever@eecs.umich.edu //This argument register is r10 for syscalls and rcx for C. 1082SN/A INTREG_R10W, 1092SN/A //INTREG_RCX, 1102SN/A INTREG_R8W, 1112SN/A INTREG_R9W 1122SN/A }; 1132SN/A const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int); 1142SN/A 1152SN/A // Some OS syscalls use a second register (rdx) to return a second 1162SN/A // value 1172SN/A const int SyscallPseudoReturnReg = INTREG_RDX; 1182SN/A 1192SN/A //XXX These numbers are bogus 1202SN/A const int MaxInstSrcRegs = 10; 1212SN/A const int MaxInstDestRegs = 10; 1222SN/A 1232SN/A //4k. This value is not constant on x86. 1242SN/A const int LogVMPageSize = 12; 1252SN/A const int VMPageSize = (1 << LogVMPageSize); 1262SN/A 1272SN/A const int PageShift = 13; 1282SN/A const int PageBytes = 1ULL << PageShift; 1292SN/A 130396SN/A const int BranchPredAddrShiftAmt = 0; 131396SN/A 132396SN/A StaticInstPtr decodeInst(ExtMachInst); 133396SN/A}; 134396SN/A 1353329Sstever@eecs.umich.edu#endif // __ARCH_X86_ISATRAITS_HH__ 1363329Sstever@eecs.umich.edu