isa_traits.hh revision 5152
1545SN/A/* 22512SN/A * Copyright (c) 2007 The Hewlett-Packard Development Company 3545SN/A * All rights reserved. 4545SN/A * 5545SN/A * Redistribution and use of this software in source and binary forms, 6545SN/A * with or without modification, are permitted provided that the 7545SN/A * following conditions are met: 8545SN/A * 9545SN/A * The software must be used only for Non-Commercial Use which means any 10545SN/A * use which is NOT directed to receiving any direct monetary 11545SN/A * compensation for, or commercial advantage from such use. Illustrative 12545SN/A * examples of non-commercial use are academic research, personal study, 13545SN/A * teaching, education and corporate research & development. 14545SN/A * Illustrative examples of commercial use are distributing products for 15545SN/A * commercial advantage and providing services using the software for 16545SN/A * commercial advantage. 17545SN/A * 18545SN/A * If you wish to use this software or functionality therein that may be 19545SN/A * covered by patents for commercial use, please contact: 20545SN/A * Director of Intellectual Property Licensing 21545SN/A * Office of Strategy and Technology 22545SN/A * Hewlett-Packard Company 23545SN/A * 1501 Page Mill Road 24545SN/A * Palo Alto, California 94304 25545SN/A * 26545SN/A * Redistributions of source code must retain the above copyright notice, 272665Ssaidi@eecs.umich.edu * this list of conditions and the following disclaimer. Redistributions 282665Ssaidi@eecs.umich.edu * in binary form must reproduce the above copyright notice, this list of 292665Ssaidi@eecs.umich.edu * conditions and the following disclaimer in the documentation and/or 30545SN/A * other materials provided with the distribution. Neither the name of 31545SN/A * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 323090Sstever@eecs.umich.edu * contributors may be used to endorse or promote products derived from 332657Ssaidi@eecs.umich.edu * this software without specific prior written permission. No right of 34545SN/A * sublicense is granted herewith. Derivatives of the software and 35679SN/A * output created using the software may be prepared, but only for 362901Ssaidi@eecs.umich.edu * Non-Commercial Uses. Derivatives of the software may be shared with 37545SN/A * others provided: (i) the others agree to abide by the list of 382489SN/A * conditions herein which includes the Non-Commercial Use restrictions; 392901Ssaidi@eecs.umich.edu * and (ii) such Derivatives of the software include the above copyright 403401Sktlim@umich.edu * notice to acknowledge the contribution from this software where 412489SN/A * applicable, this list of conditions and the disclaimer below. 422489SN/A * 432489SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 442489SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 453349Sbinkertn@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 462489SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 473091Sstever@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 482489SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 492489SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 502489SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 512521SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 522489SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 532521SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 542521SN/A * 552489SN/A * Authors: Gabe Black 562489SN/A */ 572489SN/A 58545SN/A#ifndef __ARCH_X86_ISATRAITS_HH__ 59545SN/A#define __ARCH_X86_ISATRAITS_HH__ 602384SN/A 612489SN/A#include "arch/x86/intregs.hh" 62545SN/A#include "arch/x86/types.hh" 63545SN/A#include "arch/x86/x86_traits.hh" 642542SN/A#include "sim/host.hh" 652541SN/A 662541SN/Aclass StaticInstPtr; 672541SN/A 682541SN/Anamespace LittleEndianGuest {} 692541SN/A 702541SN/Anamespace X86ISA 712541SN/A{ 722901Ssaidi@eecs.umich.edu //This makes sure the little endian version of certain functions 732901Ssaidi@eecs.umich.edu //are used. 742901Ssaidi@eecs.umich.edu using namespace LittleEndianGuest; 752901Ssaidi@eecs.umich.edu 762901Ssaidi@eecs.umich.edu // X86 does not have a delay slot 772901Ssaidi@eecs.umich.edu#define ISA_HAS_DELAY_SLOT 0 782901Ssaidi@eecs.umich.edu 792901Ssaidi@eecs.umich.edu // X86 NOP (XCHG rAX, rAX) 802901Ssaidi@eecs.umich.edu //XXX This needs to be set to an intermediate instruction struct 812901Ssaidi@eecs.umich.edu //which encodes this instruction 822901Ssaidi@eecs.umich.edu 832901Ssaidi@eecs.umich.edu // These enumerate all the registers for dependence tracking. 842901Ssaidi@eecs.umich.edu enum DependenceTags { 852539SN/A //There are 16 microcode registers at the moment. This is an 862539SN/A //unusually large constant to make sure there isn't overflow. 872539SN/A FP_Base_DepTag = 128, 882539SN/A Ctrl_Base_DepTag = 892539SN/A FP_Base_DepTag + 902539SN/A //mmx/x87 registers 912539SN/A 8 + 922539SN/A //xmm registers 932489SN/A 16 * 2 + 942901Ssaidi@eecs.umich.edu //The microcode fp registers 953401Sktlim@umich.edu 8 + 964435Ssaidi@eecs.umich.edu //The indices that are mapped over the fp stack 974435Ssaidi@eecs.umich.edu 8 982489SN/A }; 992489SN/A 1002489SN/A // semantically meaningful register indices 1013349Sbinkertn@umich.edu //There is no such register in X86 1022384SN/A const int ZeroReg = NUM_INTREGS; 1032685Ssaidi@eecs.umich.edu const int StackPointerReg = INTREG_RSP; 1042685Ssaidi@eecs.umich.edu //X86 doesn't seem to have a link register 1052685Ssaidi@eecs.umich.edu const int ReturnAddressReg = 0; 1062685Ssaidi@eecs.umich.edu const int ReturnValueReg = INTREG_RAX; 1072685Ssaidi@eecs.umich.edu const int FramePointerReg = INTREG_RBP; 1084435Ssaidi@eecs.umich.edu const int ArgumentReg[] = { 1094435Ssaidi@eecs.umich.edu INTREG_RDI, 1104435Ssaidi@eecs.umich.edu INTREG_RSI, 1114435Ssaidi@eecs.umich.edu INTREG_RDX, 1124435Ssaidi@eecs.umich.edu //This argument register is r10 for syscalls and rcx for C. 1134435Ssaidi@eecs.umich.edu INTREG_R10W, 1144435Ssaidi@eecs.umich.edu //INTREG_RCX, 1154435Ssaidi@eecs.umich.edu INTREG_R8W, 1164435Ssaidi@eecs.umich.edu INTREG_R9W 1174435Ssaidi@eecs.umich.edu }; 1184435Ssaidi@eecs.umich.edu const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int); 1194435Ssaidi@eecs.umich.edu 1204435Ssaidi@eecs.umich.edu // Some OS syscalls use a second register (rdx) to return a second 1212685Ssaidi@eecs.umich.edu // value 1224435Ssaidi@eecs.umich.edu const int SyscallPseudoReturnReg = INTREG_RDX; 1232685Ssaidi@eecs.umich.edu 1242565SN/A //XXX These numbers are bogus 1254435Ssaidi@eecs.umich.edu const int MaxInstSrcRegs = 10; 1264435Ssaidi@eecs.umich.edu const int MaxInstDestRegs = 10; 1274435Ssaidi@eecs.umich.edu 1284435Ssaidi@eecs.umich.edu //4k. This value is not constant on x86. 1292641Sstever@eecs.umich.edu const int LogVMPageSize = 12; 1302685Ssaidi@eecs.umich.edu const int VMPageSize = (1 << LogVMPageSize); 1312685Ssaidi@eecs.umich.edu 1322685Ssaidi@eecs.umich.edu const int PageShift = 12; 1332657Ssaidi@eecs.umich.edu const int PageBytes = 1ULL << PageShift; 1342685Ssaidi@eecs.umich.edu 1352685Ssaidi@eecs.umich.edu const int BranchPredAddrShiftAmt = 0; 1364435Ssaidi@eecs.umich.edu 1372685Ssaidi@eecs.umich.edu StaticInstPtr decodeInst(ExtMachInst); 1382685Ssaidi@eecs.umich.edu 1392685Ssaidi@eecs.umich.edu const Addr LoadAddrMask = ULL(-1); 1402685Ssaidi@eecs.umich.edu}; 1412630SN/A 1422630SN/A#endif // __ARCH_X86_ISATRAITS_HH__ 1432901Ssaidi@eecs.umich.edu