isa_traits.hh revision 5082
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554120Sgblack@eecs.umich.edu * Authors: Gabe Black
564120Sgblack@eecs.umich.edu */
574120Sgblack@eecs.umich.edu
584120Sgblack@eecs.umich.edu#ifndef __ARCH_X86_ISATRAITS_HH__
594120Sgblack@eecs.umich.edu#define __ARCH_X86_ISATRAITS_HH__
604120Sgblack@eecs.umich.edu
614166Sgblack@eecs.umich.edu#include "arch/x86/intregs.hh"
624141Sgblack@eecs.umich.edu#include "arch/x86/types.hh"
634136Sgblack@eecs.umich.edu#include "arch/x86/x86_traits.hh"
644136Sgblack@eecs.umich.edu
654141Sgblack@eecs.umich.educlass StaticInstPtr;
664141Sgblack@eecs.umich.edu
674121Sgblack@eecs.umich.edunamespace LittleEndianGuest {}
684120Sgblack@eecs.umich.edu
694120Sgblack@eecs.umich.edunamespace X86ISA
704120Sgblack@eecs.umich.edu{
714121Sgblack@eecs.umich.edu    //This makes sure the little endian version of certain functions
724121Sgblack@eecs.umich.edu    //are used.
734121Sgblack@eecs.umich.edu    using namespace LittleEndianGuest;
744121Sgblack@eecs.umich.edu
754121Sgblack@eecs.umich.edu    // X86 does not have a delay slot
764121Sgblack@eecs.umich.edu#define ISA_HAS_DELAY_SLOT 0
774121Sgblack@eecs.umich.edu
784121Sgblack@eecs.umich.edu    // X86 NOP (XCHG rAX, rAX)
794121Sgblack@eecs.umich.edu    //XXX This needs to be set to an intermediate instruction struct
804121Sgblack@eecs.umich.edu    //which encodes this instruction
814121Sgblack@eecs.umich.edu
824121Sgblack@eecs.umich.edu    // These enumerate all the registers for dependence tracking.
834121Sgblack@eecs.umich.edu    enum DependenceTags {
845063Sgblack@eecs.umich.edu        //There are 16 microcode registers at the moment. This is an
855063Sgblack@eecs.umich.edu        //unusually large constant to make sure there isn't overflow.
865063Sgblack@eecs.umich.edu        FP_Base_DepTag = 128,
874121Sgblack@eecs.umich.edu        Ctrl_Base_DepTag =
884121Sgblack@eecs.umich.edu            FP_Base_DepTag +
894121Sgblack@eecs.umich.edu            //mmx/x87 registers
904121Sgblack@eecs.umich.edu            8 +
914121Sgblack@eecs.umich.edu            //xmm registers
925082Sgblack@eecs.umich.edu            16 +
935082Sgblack@eecs.umich.edu            //The indices that are mapped over the fp stack
945082Sgblack@eecs.umich.edu            8
954121Sgblack@eecs.umich.edu    };
964121Sgblack@eecs.umich.edu
974121Sgblack@eecs.umich.edu    // semantically meaningful register indices
984121Sgblack@eecs.umich.edu    //There is no such register in X86
994587Sgblack@eecs.umich.edu    const int ZeroReg = NUM_INTREGS;
1004166Sgblack@eecs.umich.edu    const int StackPointerReg = INTREG_RSP;
1014121Sgblack@eecs.umich.edu    //X86 doesn't seem to have a link register
1024121Sgblack@eecs.umich.edu    const int ReturnAddressReg = 0;
1034166Sgblack@eecs.umich.edu    const int ReturnValueReg = INTREG_RAX;
1044166Sgblack@eecs.umich.edu    const int FramePointerReg = INTREG_RBP;
1054772Sgblack@eecs.umich.edu    const int ArgumentReg[] = {
1064772Sgblack@eecs.umich.edu        INTREG_RDI,
1074772Sgblack@eecs.umich.edu        INTREG_RSI,
1084772Sgblack@eecs.umich.edu        INTREG_RDX,
1094772Sgblack@eecs.umich.edu        //This argument register is r10 for syscalls and rcx for C.
1104772Sgblack@eecs.umich.edu        INTREG_R10W,
1114772Sgblack@eecs.umich.edu        //INTREG_RCX,
1124772Sgblack@eecs.umich.edu        INTREG_R8W,
1134772Sgblack@eecs.umich.edu        INTREG_R9W
1144772Sgblack@eecs.umich.edu    };
1154772Sgblack@eecs.umich.edu    const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
1164121Sgblack@eecs.umich.edu
1174121Sgblack@eecs.umich.edu    // Some OS syscalls use a second register (rdx) to return a second
1184121Sgblack@eecs.umich.edu    // value
1194166Sgblack@eecs.umich.edu    const int SyscallPseudoReturnReg = INTREG_RDX;
1204121Sgblack@eecs.umich.edu
1214121Sgblack@eecs.umich.edu    //XXX These numbers are bogus
1224121Sgblack@eecs.umich.edu    const int MaxInstSrcRegs = 10;
1234121Sgblack@eecs.umich.edu    const int MaxInstDestRegs = 10;
1244121Sgblack@eecs.umich.edu
1254121Sgblack@eecs.umich.edu    //4k. This value is not constant on x86.
1264141Sgblack@eecs.umich.edu    const int LogVMPageSize = 12;
1274141Sgblack@eecs.umich.edu    const int VMPageSize = (1 << LogVMPageSize);
1284141Sgblack@eecs.umich.edu
1294141Sgblack@eecs.umich.edu    const int PageShift = 13;
1304141Sgblack@eecs.umich.edu    const int PageBytes = 1ULL << PageShift;
1314121Sgblack@eecs.umich.edu
1324121Sgblack@eecs.umich.edu    const int BranchPredAddrShiftAmt = 0;
1334141Sgblack@eecs.umich.edu
1344141Sgblack@eecs.umich.edu    StaticInstPtr decodeInst(ExtMachInst);
1354120Sgblack@eecs.umich.edu};
1364120Sgblack@eecs.umich.edu
1374120Sgblack@eecs.umich.edu#endif // __ARCH_X86_ISATRAITS_HH__
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