operands.isa revision 8500:5bae9eee9482
12810SN/A// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 212724Snikos.nikoleris@arm.com// All rights reserved. 38856Sandreas.hansson@arm.com// 48856Sandreas.hansson@arm.com// The license below extends only to copyright in the software and shall 58856Sandreas.hansson@arm.com// not be construed as granting a license to any other intellectual 68856Sandreas.hansson@arm.com// property including but not limited to intellectual property relating 78856Sandreas.hansson@arm.com// to a hardware implementation of the functionality of the software 88856Sandreas.hansson@arm.com// licensed hereunder. You may use the software subject to the license 98856Sandreas.hansson@arm.com// terms below provided that you ensure that this notice is replicated 108856Sandreas.hansson@arm.com// unmodified and in its entirety in all distributions of the software, 118856Sandreas.hansson@arm.com// modified or unmodified, in source code or in binary form. 128856Sandreas.hansson@arm.com// 138856Sandreas.hansson@arm.com// Copyright (c) 2007 The Regents of The University of Michigan 142810SN/A// All rights reserved. 152810SN/A// 162810SN/A// Redistribution and use in source and binary forms, with or without 172810SN/A// modification, are permitted provided that the following conditions are 182810SN/A// met: redistributions of source code must retain the above copyright 192810SN/A// notice, this list of conditions and the following disclaimer; 202810SN/A// redistributions in binary form must reproduce the above copyright 212810SN/A// notice, this list of conditions and the following disclaimer in the 222810SN/A// documentation and/or other materials provided with the distribution; 232810SN/A// neither the name of the copyright holders nor the names of its 242810SN/A// contributors may be used to endorse or promote products derived from 252810SN/A// this software without specific prior written permission. 262810SN/A// 272810SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 282810SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 292810SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 302810SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 312810SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 322810SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 332810SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 342810SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 352810SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 362810SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 372810SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 382810SN/A// 392810SN/A// Authors: Gabe Black 402810SN/A 4112724Snikos.nikoleris@arm.comdef operand_types {{ 422810SN/A 'sb' : 'int8_t', 432810SN/A 'ub' : 'uint8_t', 442810SN/A 'sw' : 'int16_t', 452810SN/A 'uw' : 'uint16_t', 462810SN/A 'sdw' : 'int32_t', 472810SN/A 'udw' : 'uint32_t', 482810SN/A 'sqw' : 'int64_t', 4911486Snikos.nikoleris@arm.com 'uqw' : 'uint64_t', 5011486Snikos.nikoleris@arm.com 'sf' : 'float', 5112724Snikos.nikoleris@arm.com 'df' : 'double', 5212724Snikos.nikoleris@arm.com}}; 538232Snate@binkert.org 5412724Snikos.nikoleris@arm.comlet {{ 5513222Sodanrc@yahoo.com.br def foldInt(idx, foldBit, id): 5612724Snikos.nikoleris@arm.com return ('IntReg', 'uqw', 'INTREG_FOLDED(%s, %s)' % (idx, foldBit), 5711486Snikos.nikoleris@arm.com 'IsInteger', id) 5812724Snikos.nikoleris@arm.com def intReg(idx, id): 5912724Snikos.nikoleris@arm.com return ('IntReg', 'uqw', idx, 'IsInteger', id) 6012724Snikos.nikoleris@arm.com def impIntReg(idx, id): 6113352Snikos.nikoleris@arm.com return ('IntReg', 'uqw', 'INTREG_IMPLICIT(%s)' % idx, 'IsInteger', id) 6212724Snikos.nikoleris@arm.com def floatReg(idx, id): 6312724Snikos.nikoleris@arm.com return ('FloatReg', 'df', idx, 'IsFloating', id) 6412724Snikos.nikoleris@arm.com def controlReg(idx, id, ctype = 'uqw'): 6512724Snikos.nikoleris@arm.com return ('ControlReg', ctype, idx, 662810SN/A (None, None, ['IsSerializeAfter', 672810SN/A 'IsSerializing', 682810SN/A 'IsNonSpeculative']), 698856Sandreas.hansson@arm.com id) 708856Sandreas.hansson@arm.com def squashCheckReg(idx, id, check, ctype = 'uqw'): 718856Sandreas.hansson@arm.com return ('ControlReg', ctype, idx, 728922Swilliam.wang@arm.com (None, None, ['((%s) ? ' % check+ \ 7312084Sspwilson2@wisc.edu 'IsSquashAfter : IsSerializeAfter)', 7412084Sspwilson2@wisc.edu 'IsSerializing', 758856Sandreas.hansson@arm.com 'IsNonSpeculative']), 768856Sandreas.hansson@arm.com id) 774475SN/A def squashCReg(idx, id, ctype = 'uqw'): 7811053Sandreas.hansson@arm.com return squashCheckReg(idx, id, 'true', ctype) 795034SN/A def squashCSReg(idx, id, ctype = 'uqw'): 8012724Snikos.nikoleris@arm.com return squashCheckReg(idx, id, 'dest == SEGMENT_REG_CS', ctype) 8112724Snikos.nikoleris@arm.com def squashCR0Reg(idx, id, ctype = 'uqw'): 8211377Sandreas.hansson@arm.com return squashCheckReg(idx, id, 'dest == 0', ctype) 8311377Sandreas.hansson@arm.com}}; 8412724Snikos.nikoleris@arm.com 8512724Snikos.nikoleris@arm.comdef operands {{ 8613352Snikos.nikoleris@arm.com 'SrcReg1': foldInt('src1', 'foldOBit', 1), 8712724Snikos.nikoleris@arm.com 'SSrcReg1': intReg('src1', 1), 8812724Snikos.nikoleris@arm.com 'SrcReg2': foldInt('src2', 'foldOBit', 2), 8912724Snikos.nikoleris@arm.com 'SSrcReg2': intReg('src2', 1), 9012724Snikos.nikoleris@arm.com 'Index': foldInt('index', 'foldABit', 3), 9112724Snikos.nikoleris@arm.com 'Base': foldInt('base', 'foldABit', 4), 9211053Sandreas.hansson@arm.com 'DestReg': foldInt('dest', 'foldOBit', 5), 9311722Ssophiane.senni@gmail.com 'SDestReg': intReg('dest', 5), 9411722Ssophiane.senni@gmail.com 'Data': foldInt('data', 'foldOBit', 6), 9511722Ssophiane.senni@gmail.com 'ProdLow': impIntReg(0, 7), 9611722Ssophiane.senni@gmail.com 'ProdHi': impIntReg(1, 8), 979263Smrinmoy.ghosh@arm.com 'Quotient': impIntReg(2, 9), 9813418Sodanrc@yahoo.com.br 'Remainder': impIntReg(3, 10), 995034SN/A 'Divisor': impIntReg(4, 11), 10011331Sandreas.hansson@arm.com 'DoubleBits': impIntReg(5, 11), 10112724Snikos.nikoleris@arm.com 'Rax': intReg('(INTREG_RAX)', 12), 10210884Sandreas.hansson@arm.com 'Rbx': intReg('(INTREG_RBX)', 13), 1034626SN/A 'Rcx': intReg('(INTREG_RCX)', 14), 10410360Sandreas.hansson@arm.com 'Rdx': intReg('(INTREG_RDX)', 15), 10511484Snikos.nikoleris@arm.com 'Rsp': intReg('(INTREG_RSP)', 16), 1065034SN/A 'Rbp': intReg('(INTREG_RBP)', 17), 1078883SAli.Saidi@ARM.com 'Rsi': intReg('(INTREG_RSI)', 18), 1088833Sdam.sunwoo@arm.com 'Rdi': intReg('(INTREG_RDI)', 19), 1094458SN/A 'FpSrcReg1': floatReg('src1', 20), 11011377Sandreas.hansson@arm.com 'FpSrcReg2': floatReg('src2', 21), 11111377Sandreas.hansson@arm.com 'FpDestReg': floatReg('dest', 22), 11211377Sandreas.hansson@arm.com 'FpData': floatReg('data', 23), 11311377Sandreas.hansson@arm.com 'RIP': ('PCState', 'uqw', 'pc', 11411377Sandreas.hansson@arm.com (None, None, 'IsControl'), 50), 11511377Sandreas.hansson@arm.com 'NRIP': ('PCState', 'uqw', 'npc', 11611331Sandreas.hansson@arm.com (None, None, 'IsControl'), 50), 11711331Sandreas.hansson@arm.com 'nuIP': ('PCState', 'uqw', 'nupc', 11812724Snikos.nikoleris@arm.com (None, None, 'IsControl'), 50), 11912843Srmk35@cl.cam.ac.uk # This holds the condition code portion of the flag register. The 12012724Snikos.nikoleris@arm.com # nccFlagBits version holds the rest. 12113419Sodanrc@yahoo.com.br 'ccFlagBits': intReg('INTREG_PSEUDO(0)', 60), 12212724Snikos.nikoleris@arm.com # These register should needs to be more protected so that later 12312724Snikos.nikoleris@arm.com # instructions don't map their indexes with an old value. 12412724Snikos.nikoleris@arm.com 'nccFlagBits': controlReg('MISCREG_RFLAGS', 61), 12512724Snikos.nikoleris@arm.com 'TOP': controlReg('MISCREG_X87_TOP', 62, ctype='ub'), 12612724Snikos.nikoleris@arm.com # The segment base as used by memory instructions. 12712724Snikos.nikoleris@arm.com 'SegBase': controlReg('MISCREG_SEG_EFF_BASE(segment)', 70), 12812724Snikos.nikoleris@arm.com 1292810SN/A # Operands to get and set registers indexed by the operands of the 1302810SN/A # original instruction. 1313013SN/A 'ControlDest': squashCR0Reg('MISCREG_CR(dest)', 100), 1328856Sandreas.hansson@arm.com 'ControlSrc1': controlReg('MISCREG_CR(src1)', 101), 1332810SN/A 'DebugDest': controlReg('MISCREG_DR(dest)', 102), 1343013SN/A 'DebugSrc1': controlReg('MISCREG_DR(src1)', 103), 13510714Sandreas.hansson@arm.com 'SegBaseDest': squashCSReg('MISCREG_SEG_BASE(dest)', 104), 1362810SN/A 'SegBaseSrc1': controlReg('MISCREG_SEG_BASE(src1)', 105), 1379614Srene.dejong@arm.com 'SegLimitDest': squashCSReg('MISCREG_SEG_LIMIT(dest)', 106), 1389614Srene.dejong@arm.com 'SegLimitSrc1': controlReg('MISCREG_SEG_LIMIT(src1)', 107), 1399614Srene.dejong@arm.com 'SegSelDest': controlReg('MISCREG_SEG_SEL(dest)', 108), 14010345SCurtis.Dunham@arm.com 'SegSelSrc1': controlReg('MISCREG_SEG_SEL(src1)', 109), 14110714Sandreas.hansson@arm.com 'SegAttrDest': squashCSReg('MISCREG_SEG_ATTR(dest)', 110), 14210345SCurtis.Dunham@arm.com 'SegAttrSrc1': controlReg('MISCREG_SEG_ATTR(src1)', 111), 1439614Srene.dejong@arm.com 1442810SN/A # Operands to access specific control registers directly. 1452810SN/A 'EferOp': squashCReg('MISCREG_EFER', 200), 1462810SN/A 'CR4Op': controlReg('MISCREG_CR4', 201), 1478856Sandreas.hansson@arm.com 'DR7Op': controlReg('MISCREG_DR7', 202), 1482810SN/A 'LDTRBase': controlReg('MISCREG_TSL_BASE', 203), 1493013SN/A 'LDTRLimit': controlReg('MISCREG_TSL_LIMIT', 204), 15010714Sandreas.hansson@arm.com 'LDTRSel': controlReg('MISCREG_TSL', 205), 1513013SN/A 'GDTRBase': controlReg('MISCREG_TSG_BASE', 206), 1528856Sandreas.hansson@arm.com 'GDTRLimit': controlReg('MISCREG_TSG_LIMIT', 207), 15310714Sandreas.hansson@arm.com 'CSBase': squashCReg('MISCREG_CS_EFF_BASE', 208), 1548922Swilliam.wang@arm.com 'CSAttr': squashCReg('MISCREG_CS_ATTR', 209), 1552897SN/A 'MiscRegDest': controlReg('dest', 210), 1562810SN/A 'MiscRegSrc1': controlReg('src1', 211), 1572810SN/A 'TscOp': controlReg('MISCREG_TSC', 212), 15810344Sandreas.hansson@arm.com 'M5Reg': squashCReg('MISCREG_M5_REG', 213), 15910344Sandreas.hansson@arm.com 'Mem': ('Mem', 'uqw', None, \ 16010344Sandreas.hansson@arm.com ('IsMemRef', 'IsLoad', 'IsStore'), 300) 16110714Sandreas.hansson@arm.com}}; 16210344Sandreas.hansson@arm.com