operands.isa revision 11328:9512d2e25f14
16145Snate@binkert.org// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 26239Snate@binkert.org// Copyright (c) 2015 Advanced Micro Devices, Inc. 36239Snate@binkert.org// All rights reserved. 46145Snate@binkert.org// 56239Snate@binkert.org// The license below extends only to copyright in the software and shall 66239Snate@binkert.org// not be construed as granting a license to any other intellectual 76239Snate@binkert.org// property including but not limited to intellectual property relating 86239Snate@binkert.org// to a hardware implementation of the functionality of the software 96239Snate@binkert.org// licensed hereunder. You may use the software subject to the license 106239Snate@binkert.org// terms below provided that you ensure that this notice is replicated 116239Snate@binkert.org// unmodified and in its entirety in all distributions of the software, 126239Snate@binkert.org// modified or unmodified, in source code or in binary form. 136239Snate@binkert.org// 146239Snate@binkert.org// Copyright (c) 2007 The Regents of The University of Michigan 156145Snate@binkert.org// Copyright (c) 2012 Mark D. Hill and David A. Wood 166239Snate@binkert.org// Copyright (c) 2012-2013 Advanced Micro Devices, Inc. 176239Snate@binkert.org// All rights reserved. 186239Snate@binkert.org// 196239Snate@binkert.org// Redistribution and use in source and binary forms, with or without 206239Snate@binkert.org// modification, are permitted provided that the following conditions are 216239Snate@binkert.org// met: redistributions of source code must retain the above copyright 226239Snate@binkert.org// notice, this list of conditions and the following disclaimer; 236239Snate@binkert.org// redistributions in binary form must reproduce the above copyright 246239Snate@binkert.org// notice, this list of conditions and the following disclaimer in the 256239Snate@binkert.org// documentation and/or other materials provided with the distribution; 266239Snate@binkert.org// neither the name of the copyright holders nor the names of its 276145Snate@binkert.org// contributors may be used to endorse or promote products derived from 286145Snate@binkert.org// this software without specific prior written permission. 297039Snate@binkert.org// 307039Snate@binkert.org// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 316145Snate@binkert.org// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 328091Snilay@cs.wisc.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 336145Snate@binkert.org// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 347002Snate@binkert.org// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 357002Snate@binkert.org// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 368608Snilay@cs.wisc.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 376145Snate@binkert.org// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 386145Snate@binkert.org// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 396145Snate@binkert.org// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 406145Snate@binkert.org// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 416145Snate@binkert.org// 426145Snate@binkert.org// Authors: Gabe Black 436145Snate@binkert.org 447039Snate@binkert.orgdef operand_types {{ 457039Snate@binkert.org 'sb' : 'int8_t', 467039Snate@binkert.org 'ub' : 'uint8_t', 477039Snate@binkert.org 'sw' : 'int16_t', 487039Snate@binkert.org 'uw' : 'uint16_t', 497039Snate@binkert.org 'sdw' : 'int32_t', 506145Snate@binkert.org 'udw' : 'uint32_t', 517039Snate@binkert.org 'sqw' : 'int64_t', 527039Snate@binkert.org 'uqw' : 'uint64_t', 537039Snate@binkert.org 'u2qw' : 'std::array<uint64_t, 2>', 547039Snate@binkert.org 'sf' : 'float', 556145Snate@binkert.org 'df' : 'double', 567039Snate@binkert.org}}; 577039Snate@binkert.org 586145Snate@binkert.orglet {{ 597039Snate@binkert.org def foldInt(idx, foldBit, id): 607039Snate@binkert.org return ('IntReg', 'uqw', 'INTREG_FOLDED(%s, %s)' % (idx, foldBit), 617039Snate@binkert.org 'IsInteger', id) 627039Snate@binkert.org def intReg(idx, id): 637039Snate@binkert.org return ('IntReg', 'uqw', idx, 'IsInteger', id) 647039Snate@binkert.org def impIntReg(idx, id): 657039Snate@binkert.org return ('IntReg', 'uqw', 'INTREG_IMPLICIT(%s)' % idx, 'IsInteger', id) 667039Snate@binkert.org def floatReg(idx, id): 676145Snate@binkert.org return ('FloatReg', 'df', idx, 'IsFloating', id) 688091Snilay@cs.wisc.edu def ccReg(idx, id): 698091Snilay@cs.wisc.edu return ('CCReg', 'uqw', idx, 'IsCC', id) 708091Snilay@cs.wisc.edu def controlReg(idx, id, ctype = 'uqw'): 718091Snilay@cs.wisc.edu return ('ControlReg', ctype, idx, 726145Snate@binkert.org (None, None, ['IsSerializeAfter', 737039Snate@binkert.org 'IsSerializing', 747039Snate@binkert.org 'IsNonSpeculative']), 756145Snate@binkert.org id) 767039Snate@binkert.org def squashCheckReg(idx, id, check, ctype = 'uqw'): 776145Snate@binkert.org return ('ControlReg', ctype, idx, 787055Snate@binkert.org (None, None, ['((%s) ? ' % check+ \ 797055Snate@binkert.org 'IsSquashAfter : IsSerializeAfter)', 807055Snate@binkert.org 'IsSerializing', 816145Snate@binkert.org 'IsNonSpeculative']), 827039Snate@binkert.org id) 837039Snate@binkert.org def squashCReg(idx, id, ctype = 'uqw'): 847039Snate@binkert.org return squashCheckReg(idx, id, 'true', ctype) 857039Snate@binkert.org def squashCSReg(idx, id, ctype = 'uqw'): 867039Snate@binkert.org return squashCheckReg(idx, id, 'dest == SEGMENT_REG_CS', ctype) 877039Snate@binkert.org def squashCR0Reg(idx, id, ctype = 'uqw'): 887039Snate@binkert.org return squashCheckReg(idx, id, 'dest == 0', ctype) 897039Snate@binkert.org}}; 907039Snate@binkert.org 917039Snate@binkert.orgdef operands {{ 926145Snate@binkert.org 'SrcReg1': foldInt('src1', 'foldOBit', 1), 936145Snate@binkert.org 'SSrcReg1': intReg('src1', 1), 947039Snate@binkert.org 'SrcReg2': foldInt('src2', 'foldOBit', 2), 957039Snate@binkert.org 'SSrcReg2': intReg('src2', 1), 966145Snate@binkert.org 'Index': foldInt('index', 'foldABit', 3), 977039Snate@binkert.org 'Base': foldInt('base', 'foldABit', 4), 987039Snate@binkert.org 'DestReg': foldInt('dest', 'foldOBit', 5), 997039Snate@binkert.org 'SDestReg': intReg('dest', 5), 1006145Snate@binkert.org 'Data': foldInt('data', 'foldOBit', 6), 1016145Snate@binkert.org 'ProdLow': impIntReg(0, 7), 1027039Snate@binkert.org 'ProdHi': impIntReg(1, 8), 1037039Snate@binkert.org 'Quotient': impIntReg(2, 9), 1046145Snate@binkert.org 'Remainder': impIntReg(3, 10), 1057039Snate@binkert.org 'Divisor': impIntReg(4, 11), 1066145Snate@binkert.org 'DoubleBits': impIntReg(5, 11), 1076145Snate@binkert.org 'Rax': intReg('(INTREG_RAX)', 12), 1087055Snate@binkert.org 'Rbx': intReg('(INTREG_RBX)', 13), 1097055Snate@binkert.org 'Rcx': intReg('(INTREG_RCX)', 14), 1106145Snate@binkert.org 'Rdx': intReg('(INTREG_RDX)', 15), 1117039Snate@binkert.org 'Rsp': intReg('(INTREG_RSP)', 16), 1127055Snate@binkert.org 'Rbp': intReg('(INTREG_RBP)', 17), 1137039Snate@binkert.org 'Rsi': intReg('(INTREG_RSI)', 18), 1146145Snate@binkert.org 'Rdi': intReg('(INTREG_RDI)', 19), 1156145Snate@binkert.org 'FpSrcReg1': floatReg('src1', 20), 1167039Snate@binkert.org 'FpSrcReg2': floatReg('src2', 21), 1177039Snate@binkert.org 'FpDestReg': floatReg('dest', 22), 1186145Snate@binkert.org 'FpData': floatReg('data', 23), 1197039Snate@binkert.org 'RIP': ('PCState', 'uqw', 'pc', 1206145Snate@binkert.org (None, None, 'IsControl'), 50), 1216145Snate@binkert.org 'NRIP': ('PCState', 'uqw', 'npc', 1227039Snate@binkert.org (None, None, 'IsControl'), 50), 1237039Snate@binkert.org 'nuIP': ('PCState', 'uqw', 'nupc', 1246145Snate@binkert.org (None, None, 'IsControl'), 50), 1257039Snate@binkert.org # These registers hold the condition code portion of the flag 1267039Snate@binkert.org # register. The nccFlagBits version holds the rest. 1276145Snate@binkert.org 'ccFlagBits': ccReg('(CCREG_ZAPS)', 60), 1287039Snate@binkert.org 'cfofBits': ccReg('(CCREG_CFOF)', 61), 1297039Snate@binkert.org 'dfBit': ccReg('(CCREG_DF)', 62), 1307039Snate@binkert.org 'ecfBit': ccReg('(CCREG_ECF)', 63), 1317039Snate@binkert.org 'ezfBit': ccReg('(CCREG_EZF)', 64), 1327039Snate@binkert.org 1337039Snate@binkert.org # These Pred registers are to be used where reading the portions of 1347039Snate@binkert.org # condition code registers is possibly optional, depending on how the 1357039Snate@binkert.org # check evaluates. There are two checks being specified, one tests if 1367039Snate@binkert.org # a register needs to be read, the other tests whether the register 1377039Snate@binkert.org # needs to be written to. It is unlikely that these would need to be 1387039Snate@binkert.org # used in the actual operation of the instruction. It is expected 1397039Snate@binkert.org # that these are used only in the flag code. 1407039Snate@binkert.org 1417039Snate@binkert.org # Rationale behind the checks: at times, we need to partially update 1427039Snate@binkert.org # the condition code bits in a register. So we read the register even 1436145Snate@binkert.org # in the case when the all the bits will be written, or none of the 1446145Snate@binkert.org # bits will be written. The read predicate checks if any of the bits 1457027SBrad.Beckmann@amd.com # would be retained, the write predicate checks if any of the bits 1467039Snate@binkert.org # are being written. 1477039Snate@binkert.org 1487027SBrad.Beckmann@amd.com 'PredccFlagBits': ('CCReg', 'uqw', '(CCREG_ZAPS)', 'IsCC', 1497027SBrad.Beckmann@amd.com 60, None, None, '''(((ext & (PFBit | AFBit | ZFBit | SFBit 1507027SBrad.Beckmann@amd.com )) != (PFBit | AFBit | ZFBit | SFBit )) && 1517054Snate@binkert.org ((ext & (PFBit | AFBit | ZFBit | SFBit )) != 0))''', 1527027SBrad.Beckmann@amd.com '((ext & (PFBit | AFBit | ZFBit | SFBit )) != 0)'), 1537027SBrad.Beckmann@amd.com 'PredcfofBits': ('CCReg', 'uqw', '(CCREG_CFOF)', 'IsCC', 1547027SBrad.Beckmann@amd.com 61, None, None, '''(((ext & CFBit) == 0 || 1557027SBrad.Beckmann@amd.com (ext & OFBit) == 0) && ((ext & (CFBit | OFBit)) != 0))''', 1567027SBrad.Beckmann@amd.com '((ext & (CFBit | OFBit)) != 0)'), 1577027SBrad.Beckmann@amd.com 'PreddfBit': ('CCReg', 'uqw', '(CCREG_DF)', 'IsCC', 1587027SBrad.Beckmann@amd.com 62, None, None, '(false)', '((ext & DFBit) != 0)'), 1597027SBrad.Beckmann@amd.com 'PredecfBit': ('CCReg', 'uqw', '(CCREG_ECF)', 'IsCC', 1607027SBrad.Beckmann@amd.com 63, None, None, '(false)', '((ext & ECFBit) != 0)'), 1617027SBrad.Beckmann@amd.com 'PredezfBit': ('CCReg', 'uqw', '(CCREG_EZF)', 'IsCC', 1627027SBrad.Beckmann@amd.com 64, None, None, '(false)', '((ext & EZFBit) != 0)'), 1637027SBrad.Beckmann@amd.com 1647027SBrad.Beckmann@amd.com # These register should needs to be more protected so that later 1657027SBrad.Beckmann@amd.com # instructions don't map their indexes with an old value. 1667027SBrad.Beckmann@amd.com 'nccFlagBits': controlReg('MISCREG_RFLAGS', 65), 1677563SBrad.Beckmann@amd.com 1687027SBrad.Beckmann@amd.com # Registers related to the state of x87 floating point unit. 1697027SBrad.Beckmann@amd.com 'TOP': controlReg('MISCREG_X87_TOP', 66, ctype='ub'), 1707027SBrad.Beckmann@amd.com 'FSW': controlReg('MISCREG_FSW', 67, ctype='uw'), 1717027SBrad.Beckmann@amd.com 'FTW': controlReg('MISCREG_FTW', 68, ctype='uw'), 1727039Snate@binkert.org 'FCW': controlReg('MISCREG_FCW', 69, ctype='uw'), 1737039Snate@binkert.org 1746145Snate@binkert.org # The segment base as used by memory instructions. 1756145Snate@binkert.org 'SegBase': controlReg('MISCREG_SEG_EFF_BASE(segment)', 70), 1766145Snate@binkert.org 1776145Snate@binkert.org # Operands to get and set registers indexed by the operands of the 1787039Snate@binkert.org # original instruction. 1796145Snate@binkert.org 'ControlDest': squashCR0Reg('MISCREG_CR(dest)', 100), 1807039Snate@binkert.org 'ControlSrc1': controlReg('MISCREG_CR(src1)', 101), 1816145Snate@binkert.org 'DebugDest': controlReg('MISCREG_DR(dest)', 102), 1826145Snate@binkert.org 'DebugSrc1': controlReg('MISCREG_DR(src1)', 103), 1836145Snate@binkert.org 'SegBaseDest': squashCSReg('MISCREG_SEG_BASE(dest)', 104), 1846145Snate@binkert.org 'SegBaseSrc1': controlReg('MISCREG_SEG_BASE(src1)', 105), 1857039Snate@binkert.org 'SegLimitDest': squashCSReg('MISCREG_SEG_LIMIT(dest)', 106), 1867039Snate@binkert.org 'SegLimitSrc1': controlReg('MISCREG_SEG_LIMIT(src1)', 107), 1876145Snate@binkert.org 'SegSelDest': controlReg('MISCREG_SEG_SEL(dest)', 108), 1887039Snate@binkert.org 'SegSelSrc1': controlReg('MISCREG_SEG_SEL(src1)', 109), 1896145Snate@binkert.org 'SegAttrDest': squashCSReg('MISCREG_SEG_ATTR(dest)', 110), 1907039Snate@binkert.org 'SegAttrSrc1': controlReg('MISCREG_SEG_ATTR(src1)', 111), 1917039Snate@binkert.org 1927039Snate@binkert.org # Operands to access specific control registers directly. 1937039Snate@binkert.org 'EferOp': squashCReg('MISCREG_EFER', 200), 1947039Snate@binkert.org 'CR4Op': controlReg('MISCREG_CR4', 201), 1957039Snate@binkert.org 'DR7Op': controlReg('MISCREG_DR7', 202), 1966145Snate@binkert.org 'LDTRBase': controlReg('MISCREG_TSL_BASE', 203), 1976145Snate@binkert.org 'LDTRLimit': controlReg('MISCREG_TSL_LIMIT', 204), 1987039Snate@binkert.org 'LDTRSel': controlReg('MISCREG_TSL', 205), 1997039Snate@binkert.org 'GDTRBase': controlReg('MISCREG_TSG_BASE', 206), 2006145Snate@binkert.org 'GDTRLimit': controlReg('MISCREG_TSG_LIMIT', 207), 2017039Snate@binkert.org 'CSBase': squashCReg('MISCREG_CS_EFF_BASE', 208), 2026145Snate@binkert.org 'CSAttr': squashCReg('MISCREG_CS_ATTR', 209), 2036145Snate@binkert.org 'MiscRegDest': controlReg('dest', 210), 2046145Snate@binkert.org 'MiscRegSrc1': controlReg('src1', 211), 2057002Snate@binkert.org 'TscOp': controlReg('MISCREG_TSC', 212), 2067039Snate@binkert.org 'M5Reg': squashCReg('MISCREG_M5_REG', 213), 2077039Snate@binkert.org 'Mem': ('Mem', 'uqw', None, \ 2087039Snate@binkert.org ('IsMemRef', 'IsLoad', 'IsStore'), 300) 2097039Snate@binkert.org}}; 2107039Snate@binkert.org