xref: /gem5/src/arch/x86/isa/operands.isa

// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
// All rights reserved.
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder.  You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Copyright (c) 2007 The Regents of The University of Michigan
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Gabe Black

def operand_types {{
    'sb' : 'int8_t',
    'ub' : 'uint8_t',
    'sw' : 'int16_t',
    'uw' : 'uint16_t',
    'sdw' : 'int32_t',
    'udw' : 'uint32_t',
    'sqw' : 'int64_t',
    'uqw' : 'uint64_t',
    'sf' : 'float',
    'df' : 'double',
}};

let {{
    def foldInt(idx, foldBit, id):
        return ('IntReg', 'uqw', 'INTREG_FOLDED(%s, %s)' % (idx, foldBit),
                'IsInteger', id)
    def intReg(idx, id):
        return ('IntReg', 'uqw', idx, 'IsInteger', id)
    def impIntReg(idx, id):
        return ('IntReg', 'uqw', 'INTREG_IMPLICIT(%s)' % idx, 'IsInteger', id)
    def floatReg(idx, id):
        return ('FloatReg', 'df', idx, 'IsFloating', id)
    def controlReg(idx, id, ctype = 'uqw'):
        return ('ControlReg', ctype, idx,
                (None, None, ['IsSerializeAfter',
                              'IsSerializing',
                              'IsNonSpeculative']),
                id)
    def squashCheckReg(idx, id, check, ctype = 'uqw'):
        return ('ControlReg', ctype, idx,
                (None, None, ['((%s) ? ' % check+ \
                                'IsSquashAfter : IsSerializeAfter)',
                              'IsSerializing',
                              'IsNonSpeculative']),
                id)
    def squashCReg(idx, id, ctype = 'uqw'):
        return squashCheckReg(idx, id, 'true', ctype)
    def squashCSReg(idx, id, ctype = 'uqw'):
        return squashCheckReg(idx, id, 'dest == SEGMENT_REG_CS', ctype)
    def squashCR0Reg(idx, id, ctype = 'uqw'):
        return squashCheckReg(idx, id, 'dest == 0', ctype)
}};

def operands {{
        'SrcReg1':       foldInt('src1', 'foldOBit', 1),
        'SSrcReg1':      intReg('src1', 1),
        'SrcReg2':       foldInt('src2', 'foldOBit', 2),
        'SSrcReg2':      intReg('src2', 1),
        'Index':         foldInt('index', 'foldABit', 3),
        'Base':          foldInt('base', 'foldABit', 4),
        'DestReg':       foldInt('dest', 'foldOBit', 5),
        'SDestReg':      intReg('dest', 5),
        'Data':          foldInt('data', 'foldOBit', 6),
        'ProdLow':       impIntReg(0, 7),
        'ProdHi':        impIntReg(1, 8),
        'Quotient':      impIntReg(2, 9),
        'Remainder':     impIntReg(3, 10),
        'Divisor':       impIntReg(4, 11),
        'DoubleBits':    impIntReg(5, 11),
        'Rax':           intReg('(INTREG_RAX)', 12),
        'Rbx':           intReg('(INTREG_RBX)', 13),
        'Rcx':           intReg('(INTREG_RCX)', 14),
        'Rdx':           intReg('(INTREG_RDX)', 15),
        'Rsp':           intReg('(INTREG_RSP)', 16),
        'Rbp':           intReg('(INTREG_RBP)', 17),
        'Rsi':           intReg('(INTREG_RSI)', 18),
        'Rdi':           intReg('(INTREG_RDI)', 19),
        'FpSrcReg1':     floatReg('src1', 20),
        'FpSrcReg2':     floatReg('src2', 21),
        'FpDestReg':     floatReg('dest', 22),
        'FpData':        floatReg('data', 23),
        'RIP':           ('PCState', 'uqw', 'pc',
                          (None, None, 'IsControl'), 50),
        'NRIP':          ('PCState', 'uqw', 'npc',
                          (None, None, 'IsControl'), 50),
        'nuIP':          ('PCState', 'uqw', 'nupc',
                          (None, None, 'IsControl'), 50),
        # These registers hold the condition code portion of the flag
        # register. The nccFlagBits version holds the rest.
        'ccFlagBits':    intReg('INTREG_PSEUDO(0)', 60),
        'cfofBits':      intReg('INTREG_PSEUDO(1)', 61),
        'dfBit':         intReg('INTREG_PSEUDO(2)', 62),
        'ecfBit':        intReg('INTREG_PSEUDO(3)', 63),
        'ezfBit':        intReg('INTREG_PSEUDO(4)', 64),

        # These Pred registers are to be used where reading the portions of
        # condition code registers is possibly optional, depending on how the
        # check evaluates. There are two checks being specified, one tests if
        # a register needs to be read, the other tests whether the register
        # needs to be written to. It is unlikely that these would need to be
        # used in the actual operation of the instruction. It is expected
        # that these are used only in the flag code.

        # Rationale behind the checks: at times, we need to partially update
        # the condition code bits in a register. So we read the register even
        # in the case when the all the bits will be written, or none of the
        # bits will be written. The read predicate checks if any of the bits
        # would be retained, the write predicate checks if any of the bits
        # are being written.

        'PredccFlagBits': ('IntReg', 'uqw', 'INTREG_PSEUDO(0)', 'IsInteger',
                60, None, None, '''(((ext & (PFBit | AFBit | ZFBit | SFBit
                )) != (PFBit | AFBit | ZFBit | SFBit )) &&
                ((ext & (PFBit | AFBit | ZFBit | SFBit )) != 0))''',
                '((ext & (PFBit | AFBit | ZFBit | SFBit )) != 0)'),
        'PredcfofBits':   ('IntReg', 'uqw', 'INTREG_PSEUDO(1)', 'IsInteger',
                61, None, None, '''(((ext & CFBit) == 0 ||
                (ext & OFBit) == 0) && ((ext & (CFBit | OFBit)) != 0))''',
                '((ext & (CFBit | OFBit)) != 0)'),
        'PreddfBit':   ('IntReg', 'uqw', 'INTREG_PSEUDO(2)', 'IsInteger',
                62, None, None, '(false)', '((ext & DFBit) != 0)'),
        'PredecfBit':   ('IntReg', 'uqw', 'INTREG_PSEUDO(3)', 'IsInteger',
                63, None, None, '(false)', '((ext & ECFBit) != 0)'),
        'PredezfBit':   ('IntReg', 'uqw', 'INTREG_PSEUDO(4)', 'IsInteger',
                64, None, None, '(false)', '((ext & EZFBit) != 0)'),

        # These register should needs to be more protected so that later
        # instructions don't map their indexes with an old value.
        'nccFlagBits':   controlReg('MISCREG_RFLAGS', 65),

        # Registers related to the state of x87 floating point unit.
        'TOP':           controlReg('MISCREG_X87_TOP', 66, ctype='ub'),
        'FSW':           controlReg('MISCREG_FSW', 67, ctype='uw'),

        # The segment base as used by memory instructions.
        'SegBase':       controlReg('MISCREG_SEG_EFF_BASE(segment)', 70),

        # Operands to get and set registers indexed by the operands of the
        # original instruction.
        'ControlDest':   squashCR0Reg('MISCREG_CR(dest)', 100),
        'ControlSrc1':   controlReg('MISCREG_CR(src1)', 101),
        'DebugDest':     controlReg('MISCREG_DR(dest)', 102),
        'DebugSrc1':     controlReg('MISCREG_DR(src1)', 103),
        'SegBaseDest':   squashCSReg('MISCREG_SEG_BASE(dest)', 104),
        'SegBaseSrc1':   controlReg('MISCREG_SEG_BASE(src1)', 105),
        'SegLimitDest':  squashCSReg('MISCREG_SEG_LIMIT(dest)', 106),
        'SegLimitSrc1':  controlReg('MISCREG_SEG_LIMIT(src1)', 107),
        'SegSelDest':    controlReg('MISCREG_SEG_SEL(dest)', 108),
        'SegSelSrc1':    controlReg('MISCREG_SEG_SEL(src1)', 109),
        'SegAttrDest':   squashCSReg('MISCREG_SEG_ATTR(dest)', 110),
        'SegAttrSrc1':   controlReg('MISCREG_SEG_ATTR(src1)', 111),

        # Operands to access specific control registers directly.
        'EferOp':        squashCReg('MISCREG_EFER', 200),
        'CR4Op':         controlReg('MISCREG_CR4', 201),
        'DR7Op':         controlReg('MISCREG_DR7', 202),
        'LDTRBase':      controlReg('MISCREG_TSL_BASE', 203),
        'LDTRLimit':     controlReg('MISCREG_TSL_LIMIT', 204),
        'LDTRSel':       controlReg('MISCREG_TSL', 205),
        'GDTRBase':      controlReg('MISCREG_TSG_BASE', 206),
        'GDTRLimit':     controlReg('MISCREG_TSG_LIMIT', 207),
        'CSBase':        squashCReg('MISCREG_CS_EFF_BASE', 208),
        'CSAttr':        squashCReg('MISCREG_CS_ATTR', 209),
        'MiscRegDest':   controlReg('dest', 210),
        'MiscRegSrc1':   controlReg('src1', 211),
        'TscOp':         controlReg('MISCREG_TSC', 212),
        'M5Reg':         squashCReg('MISCREG_M5_REG', 213),
        'Mem':           ('Mem', 'uqw', None, \
                          ('IsMemRef', 'IsLoad', 'IsStore'), 300)
}};