operands.isa revision 9212
17087Snate@binkert.org// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 27087Snate@binkert.org// All rights reserved. 37087Snate@binkert.org// 47087Snate@binkert.org// The license below extends only to copyright in the software and shall 57087Snate@binkert.org// not be construed as granting a license to any other intellectual 67087Snate@binkert.org// property including but not limited to intellectual property relating 77087Snate@binkert.org// to a hardware implementation of the functionality of the software 87087Snate@binkert.org// licensed hereunder. You may use the software subject to the license 97087Snate@binkert.org// terms below provided that you ensure that this notice is replicated 107087Snate@binkert.org// unmodified and in its entirety in all distributions of the software, 117087Snate@binkert.org// modified or unmodified, in source code or in binary form. 127087Snate@binkert.org// 134158Sgblack@eecs.umich.edu// Copyright (c) 2007 The Regents of The University of Michigan 144158Sgblack@eecs.umich.edu// All rights reserved. 154158Sgblack@eecs.umich.edu// 164158Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 174158Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 184158Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 194158Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 204158Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 214158Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 224158Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 234158Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 244158Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 254158Sgblack@eecs.umich.edu// this software without specific prior written permission. 264158Sgblack@eecs.umich.edu// 274158Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284158Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294158Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304158Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314158Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324158Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334158Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344158Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354158Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364158Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374158Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384158Sgblack@eecs.umich.edu// 394158Sgblack@eecs.umich.edu// Authors: Gabe Black 404158Sgblack@eecs.umich.edu 414158Sgblack@eecs.umich.edudef operand_types {{ 428449Sgblack@eecs.umich.edu 'sb' : 'int8_t', 438449Sgblack@eecs.umich.edu 'ub' : 'uint8_t', 448449Sgblack@eecs.umich.edu 'sw' : 'int16_t', 458449Sgblack@eecs.umich.edu 'uw' : 'uint16_t', 468449Sgblack@eecs.umich.edu 'sdw' : 'int32_t', 478449Sgblack@eecs.umich.edu 'udw' : 'uint32_t', 488449Sgblack@eecs.umich.edu 'sqw' : 'int64_t', 498449Sgblack@eecs.umich.edu 'uqw' : 'uint64_t', 508449Sgblack@eecs.umich.edu 'sf' : 'float', 518449Sgblack@eecs.umich.edu 'df' : 'double', 524158Sgblack@eecs.umich.edu}}; 534158Sgblack@eecs.umich.edu 546360Sgblack@eecs.umich.edulet {{ 556360Sgblack@eecs.umich.edu def foldInt(idx, foldBit, id): 566360Sgblack@eecs.umich.edu return ('IntReg', 'uqw', 'INTREG_FOLDED(%s, %s)' % (idx, foldBit), 576360Sgblack@eecs.umich.edu 'IsInteger', id) 586360Sgblack@eecs.umich.edu def intReg(idx, id): 596360Sgblack@eecs.umich.edu return ('IntReg', 'uqw', idx, 'IsInteger', id) 606360Sgblack@eecs.umich.edu def impIntReg(idx, id): 616360Sgblack@eecs.umich.edu return ('IntReg', 'uqw', 'INTREG_IMPLICIT(%s)' % idx, 'IsInteger', id) 626360Sgblack@eecs.umich.edu def floatReg(idx, id): 636360Sgblack@eecs.umich.edu return ('FloatReg', 'df', idx, 'IsFloating', id) 646360Sgblack@eecs.umich.edu def controlReg(idx, id, ctype = 'uqw'): 656360Sgblack@eecs.umich.edu return ('ControlReg', ctype, idx, 666360Sgblack@eecs.umich.edu (None, None, ['IsSerializeAfter', 676360Sgblack@eecs.umich.edu 'IsSerializing', 686360Sgblack@eecs.umich.edu 'IsNonSpeculative']), 696360Sgblack@eecs.umich.edu id) 708500Sgblack@eecs.umich.edu def squashCheckReg(idx, id, check, ctype = 'uqw'): 718500Sgblack@eecs.umich.edu return ('ControlReg', ctype, idx, 728500Sgblack@eecs.umich.edu (None, None, ['((%s) ? ' % check+ \ 738500Sgblack@eecs.umich.edu 'IsSquashAfter : IsSerializeAfter)', 748500Sgblack@eecs.umich.edu 'IsSerializing', 758500Sgblack@eecs.umich.edu 'IsNonSpeculative']), 768500Sgblack@eecs.umich.edu id) 778500Sgblack@eecs.umich.edu def squashCReg(idx, id, ctype = 'uqw'): 788500Sgblack@eecs.umich.edu return squashCheckReg(idx, id, 'true', ctype) 798500Sgblack@eecs.umich.edu def squashCSReg(idx, id, ctype = 'uqw'): 808500Sgblack@eecs.umich.edu return squashCheckReg(idx, id, 'dest == SEGMENT_REG_CS', ctype) 818500Sgblack@eecs.umich.edu def squashCR0Reg(idx, id, ctype = 'uqw'): 828500Sgblack@eecs.umich.edu return squashCheckReg(idx, id, 'dest == 0', ctype) 836360Sgblack@eecs.umich.edu}}; 846360Sgblack@eecs.umich.edu 854158Sgblack@eecs.umich.edudef operands {{ 866360Sgblack@eecs.umich.edu 'SrcReg1': foldInt('src1', 'foldOBit', 1), 876360Sgblack@eecs.umich.edu 'SSrcReg1': intReg('src1', 1), 886360Sgblack@eecs.umich.edu 'SrcReg2': foldInt('src2', 'foldOBit', 2), 896360Sgblack@eecs.umich.edu 'SSrcReg2': intReg('src2', 1), 906360Sgblack@eecs.umich.edu 'Index': foldInt('index', 'foldABit', 3), 916360Sgblack@eecs.umich.edu 'Base': foldInt('base', 'foldABit', 4), 926360Sgblack@eecs.umich.edu 'DestReg': foldInt('dest', 'foldOBit', 5), 936360Sgblack@eecs.umich.edu 'SDestReg': intReg('dest', 5), 946360Sgblack@eecs.umich.edu 'Data': foldInt('data', 'foldOBit', 6), 956360Sgblack@eecs.umich.edu 'ProdLow': impIntReg(0, 7), 966360Sgblack@eecs.umich.edu 'ProdHi': impIntReg(1, 8), 976360Sgblack@eecs.umich.edu 'Quotient': impIntReg(2, 9), 986360Sgblack@eecs.umich.edu 'Remainder': impIntReg(3, 10), 996360Sgblack@eecs.umich.edu 'Divisor': impIntReg(4, 11), 1006479Sgblack@eecs.umich.edu 'DoubleBits': impIntReg(5, 11), 1016360Sgblack@eecs.umich.edu 'Rax': intReg('(INTREG_RAX)', 12), 1026360Sgblack@eecs.umich.edu 'Rbx': intReg('(INTREG_RBX)', 13), 1036360Sgblack@eecs.umich.edu 'Rcx': intReg('(INTREG_RCX)', 14), 1046360Sgblack@eecs.umich.edu 'Rdx': intReg('(INTREG_RDX)', 15), 1056360Sgblack@eecs.umich.edu 'Rsp': intReg('(INTREG_RSP)', 16), 1066360Sgblack@eecs.umich.edu 'Rbp': intReg('(INTREG_RBP)', 17), 1076360Sgblack@eecs.umich.edu 'Rsi': intReg('(INTREG_RSI)', 18), 1086360Sgblack@eecs.umich.edu 'Rdi': intReg('(INTREG_RDI)', 19), 1096360Sgblack@eecs.umich.edu 'FpSrcReg1': floatReg('src1', 20), 1106360Sgblack@eecs.umich.edu 'FpSrcReg2': floatReg('src2', 21), 1116360Sgblack@eecs.umich.edu 'FpDestReg': floatReg('dest', 22), 1126360Sgblack@eecs.umich.edu 'FpData': floatReg('data', 23), 1137789Sgblack@eecs.umich.edu 'RIP': ('PCState', 'uqw', 'pc', 1147789Sgblack@eecs.umich.edu (None, None, 'IsControl'), 50), 1157789Sgblack@eecs.umich.edu 'NRIP': ('PCState', 'uqw', 'npc', 1167789Sgblack@eecs.umich.edu (None, None, 'IsControl'), 50), 1177789Sgblack@eecs.umich.edu 'nuIP': ('PCState', 'uqw', 'nupc', 1187720Sgblack@eecs.umich.edu (None, None, 'IsControl'), 50), 1199212Snilay@cs.wisc.edu # These registers hold the condition code portion of the flag 1209212Snilay@cs.wisc.edu # register. The nccFlagBits version holds the rest. 1216360Sgblack@eecs.umich.edu 'ccFlagBits': intReg('INTREG_PSEUDO(0)', 60), 1229010Snilay@cs.wisc.edu 'cfofBits': intReg('INTREG_PSEUDO(1)', 61), 1239211Snilay@cs.wisc.edu 'dfBit': intReg('INTREG_PSEUDO(2)', 62), 1249211Snilay@cs.wisc.edu 'ecfBit': intReg('INTREG_PSEUDO(3)', 63), 1259211Snilay@cs.wisc.edu 'ezfBit': intReg('INTREG_PSEUDO(4)', 64), 1269212Snilay@cs.wisc.edu 1279212Snilay@cs.wisc.edu # These Pred registers are to be used where reading the portions of 1289212Snilay@cs.wisc.edu # condition code registers is possibly optional, depending on how the 1299212Snilay@cs.wisc.edu # check evaluates. There are two checks being specified, one tests if 1309212Snilay@cs.wisc.edu # a register needs to be read, the other tests whether the register 1319212Snilay@cs.wisc.edu # needs to be written to. It is unlikely that these would need to be 1329212Snilay@cs.wisc.edu # used in the actual operation of the instruction. It is expected 1339212Snilay@cs.wisc.edu # that these are used only in the flag code. 1349212Snilay@cs.wisc.edu 1359212Snilay@cs.wisc.edu # Rationale behind the checks: at times, we need to partially update 1369212Snilay@cs.wisc.edu # the condition code bits in a register. So we read the register even 1379212Snilay@cs.wisc.edu # in the case when the all the bits will be written, or none of the 1389212Snilay@cs.wisc.edu # bits will be written. The read predicate checks if any of the bits 1399212Snilay@cs.wisc.edu # would be retained, the write predicate checks if any of the bits 1409212Snilay@cs.wisc.edu # are being written. 1419212Snilay@cs.wisc.edu 1429212Snilay@cs.wisc.edu 'PredccFlagBits': ('IntReg', 'uqw', 'INTREG_PSEUDO(0)', 'IsInteger', 1439212Snilay@cs.wisc.edu 60, None, None, '''(((ext & (PFBit | AFBit | ZFBit | SFBit 1449212Snilay@cs.wisc.edu )) != (PFBit | AFBit | ZFBit | SFBit )) && 1459212Snilay@cs.wisc.edu ((ext & (PFBit | AFBit | ZFBit | SFBit )) != 0))''', 1469212Snilay@cs.wisc.edu '((ext & (PFBit | AFBit | ZFBit | SFBit )) != 0)'), 1479212Snilay@cs.wisc.edu 'PredcfofBits': ('IntReg', 'uqw', 'INTREG_PSEUDO(1)', 'IsInteger', 1489212Snilay@cs.wisc.edu 61, None, None, '''(((ext & CFBit) == 0 || 1499212Snilay@cs.wisc.edu (ext & OFBit) == 0) && ((ext & (CFBit | OFBit)) != 0))''', 1509212Snilay@cs.wisc.edu '((ext & (CFBit | OFBit)) != 0)'), 1519212Snilay@cs.wisc.edu 'PreddfBit': ('IntReg', 'uqw', 'INTREG_PSEUDO(2)', 'IsInteger', 1529212Snilay@cs.wisc.edu 62, None, None, '(false)', '((ext & DFBit) != 0)'), 1539212Snilay@cs.wisc.edu 'PredecfBit': ('IntReg', 'uqw', 'INTREG_PSEUDO(3)', 'IsInteger', 1549212Snilay@cs.wisc.edu 63, None, None, '(false)', '((ext & ECFBit) != 0)'), 1559212Snilay@cs.wisc.edu 'PredezfBit': ('IntReg', 'uqw', 'INTREG_PSEUDO(4)', 'IsInteger', 1569212Snilay@cs.wisc.edu 64, None, None, '(false)', '((ext & EZFBit) != 0)'), 1579212Snilay@cs.wisc.edu 1585426Sgblack@eecs.umich.edu # These register should needs to be more protected so that later 1595082Sgblack@eecs.umich.edu # instructions don't map their indexes with an old value. 1609211Snilay@cs.wisc.edu 'nccFlagBits': controlReg('MISCREG_RFLAGS', 65), 1619211Snilay@cs.wisc.edu 'TOP': controlReg('MISCREG_X87_TOP', 66, ctype='ub'), 1625294Sgblack@eecs.umich.edu # The segment base as used by memory instructions. 1636360Sgblack@eecs.umich.edu 'SegBase': controlReg('MISCREG_SEG_EFF_BASE(segment)', 70), 1645290Sgblack@eecs.umich.edu 1655294Sgblack@eecs.umich.edu # Operands to get and set registers indexed by the operands of the 1665294Sgblack@eecs.umich.edu # original instruction. 1678500Sgblack@eecs.umich.edu 'ControlDest': squashCR0Reg('MISCREG_CR(dest)', 100), 1686360Sgblack@eecs.umich.edu 'ControlSrc1': controlReg('MISCREG_CR(src1)', 101), 1696360Sgblack@eecs.umich.edu 'DebugDest': controlReg('MISCREG_DR(dest)', 102), 1706360Sgblack@eecs.umich.edu 'DebugSrc1': controlReg('MISCREG_DR(src1)', 103), 1718500Sgblack@eecs.umich.edu 'SegBaseDest': squashCSReg('MISCREG_SEG_BASE(dest)', 104), 1726360Sgblack@eecs.umich.edu 'SegBaseSrc1': controlReg('MISCREG_SEG_BASE(src1)', 105), 1738500Sgblack@eecs.umich.edu 'SegLimitDest': squashCSReg('MISCREG_SEG_LIMIT(dest)', 106), 1746360Sgblack@eecs.umich.edu 'SegLimitSrc1': controlReg('MISCREG_SEG_LIMIT(src1)', 107), 1756360Sgblack@eecs.umich.edu 'SegSelDest': controlReg('MISCREG_SEG_SEL(dest)', 108), 1766360Sgblack@eecs.umich.edu 'SegSelSrc1': controlReg('MISCREG_SEG_SEL(src1)', 109), 1778500Sgblack@eecs.umich.edu 'SegAttrDest': squashCSReg('MISCREG_SEG_ATTR(dest)', 110), 1786360Sgblack@eecs.umich.edu 'SegAttrSrc1': controlReg('MISCREG_SEG_ATTR(src1)', 111), 1795294Sgblack@eecs.umich.edu 1805294Sgblack@eecs.umich.edu # Operands to access specific control registers directly. 1818500Sgblack@eecs.umich.edu 'EferOp': squashCReg('MISCREG_EFER', 200), 1826360Sgblack@eecs.umich.edu 'CR4Op': controlReg('MISCREG_CR4', 201), 1836360Sgblack@eecs.umich.edu 'DR7Op': controlReg('MISCREG_DR7', 202), 1846360Sgblack@eecs.umich.edu 'LDTRBase': controlReg('MISCREG_TSL_BASE', 203), 1856360Sgblack@eecs.umich.edu 'LDTRLimit': controlReg('MISCREG_TSL_LIMIT', 204), 1866360Sgblack@eecs.umich.edu 'LDTRSel': controlReg('MISCREG_TSL', 205), 1876360Sgblack@eecs.umich.edu 'GDTRBase': controlReg('MISCREG_TSG_BASE', 206), 1886360Sgblack@eecs.umich.edu 'GDTRLimit': controlReg('MISCREG_TSG_LIMIT', 207), 1898500Sgblack@eecs.umich.edu 'CSBase': squashCReg('MISCREG_CS_EFF_BASE', 208), 1908500Sgblack@eecs.umich.edu 'CSAttr': squashCReg('MISCREG_CS_ATTR', 209), 1916360Sgblack@eecs.umich.edu 'MiscRegDest': controlReg('dest', 210), 1926360Sgblack@eecs.umich.edu 'MiscRegSrc1': controlReg('src1', 211), 1936360Sgblack@eecs.umich.edu 'TscOp': controlReg('MISCREG_TSC', 212), 1948500Sgblack@eecs.umich.edu 'M5Reg': squashCReg('MISCREG_M5_REG', 213), 1956360Sgblack@eecs.umich.edu 'Mem': ('Mem', 'uqw', None, \ 1966360Sgblack@eecs.umich.edu ('IsMemRef', 'IsLoad', 'IsStore'), 300) 1974158Sgblack@eecs.umich.edu}}; 198