seqop.isa revision 7789:f455790bcd47
16019Shines@cs.fsu.edu// Copyright (c) 2008 The Hewlett-Packard Development Company 26019Shines@cs.fsu.edu// All rights reserved. 37101Sgblack@eecs.umich.edu// 47101Sgblack@eecs.umich.edu// The license below extends only to copyright in the software and shall 57101Sgblack@eecs.umich.edu// not be construed as granting a license to any other intellectual 67101Sgblack@eecs.umich.edu// property including but not limited to intellectual property relating 77101Sgblack@eecs.umich.edu// to a hardware implementation of the functionality of the software 87101Sgblack@eecs.umich.edu// licensed hereunder. You may use the software subject to the license 97101Sgblack@eecs.umich.edu// terms below provided that you ensure that this notice is replicated 107101Sgblack@eecs.umich.edu// unmodified and in its entirety in all distributions of the software, 117101Sgblack@eecs.umich.edu// modified or unmodified, in source code or in binary form. 127101Sgblack@eecs.umich.edu// 137101Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 147101Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 156019Shines@cs.fsu.edu// met: redistributions of source code must retain the above copyright 166019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer; 176019Shines@cs.fsu.edu// redistributions in binary form must reproduce the above copyright 186019Shines@cs.fsu.edu// notice, this list of conditions and the following disclaimer in the 196019Shines@cs.fsu.edu// documentation and/or other materials provided with the distribution; 206019Shines@cs.fsu.edu// neither the name of the copyright holders nor the names of its 216019Shines@cs.fsu.edu// contributors may be used to endorse or promote products derived from 226019Shines@cs.fsu.edu// this software without specific prior written permission. 236019Shines@cs.fsu.edu// 246019Shines@cs.fsu.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 256019Shines@cs.fsu.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 266019Shines@cs.fsu.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 276019Shines@cs.fsu.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 286019Shines@cs.fsu.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 296019Shines@cs.fsu.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 306019Shines@cs.fsu.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 316019Shines@cs.fsu.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 326019Shines@cs.fsu.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 336019Shines@cs.fsu.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 346019Shines@cs.fsu.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 356019Shines@cs.fsu.edu// 366019Shines@cs.fsu.edu// Authors: Gabe Black 376019Shines@cs.fsu.edu 386019Shines@cs.fsu.eduoutput header {{ 396019Shines@cs.fsu.edu class SeqOpBase : public X86ISA::X86MicroopBase 406019Shines@cs.fsu.edu { 416019Shines@cs.fsu.edu protected: 426019Shines@cs.fsu.edu uint16_t target; 436019Shines@cs.fsu.edu uint8_t cc; 446019Shines@cs.fsu.edu 456019Shines@cs.fsu.edu public: 466019Shines@cs.fsu.edu SeqOpBase(ExtMachInst _machInst, const char * instMnem, 476019Shines@cs.fsu.edu const char * mnemonic, uint64_t setFlags, 486019Shines@cs.fsu.edu uint16_t _target, uint8_t _cc); 496268Sgblack@eecs.umich.edu 506251Sgblack@eecs.umich.edu SeqOpBase(ExtMachInst _machInst, const char * instMnem, 516269Sgblack@eecs.umich.edu const char * mnemonic, 526269Sgblack@eecs.umich.edu uint16_t _target, uint8_t _cc); 536749Sgblack@eecs.umich.edu 547105Sgblack@eecs.umich.edu std::string generateDisassembly(Addr pc, 556251Sgblack@eecs.umich.edu const SymbolTable *symtab) const; 566251Sgblack@eecs.umich.edu }; 576251Sgblack@eecs.umich.edu}}; 587105Sgblack@eecs.umich.edu 597105Sgblack@eecs.umich.edudef template SeqOpDeclare {{ 607105Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 617105Sgblack@eecs.umich.edu { 626251Sgblack@eecs.umich.edu public: 637105Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, const char * instMnem, 646268Sgblack@eecs.umich.edu uint64_t setFlags, uint16_t _target, uint8_t _cc); 656759SAli.Saidi@ARM.com 666251Sgblack@eecs.umich.edu %(BasicExecDeclare)s 677105Sgblack@eecs.umich.edu }; 686251Sgblack@eecs.umich.edu}}; 696019Shines@cs.fsu.edu 706267Sgblack@eecs.umich.edudef template SeqOpExecute {{ 716267Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 726267Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 737101Sgblack@eecs.umich.edu { 747101Sgblack@eecs.umich.edu %(op_decl)s; 757101Sgblack@eecs.umich.edu %(op_rd)s; 766019Shines@cs.fsu.edu if (%(cond_test)s) { 776251Sgblack@eecs.umich.edu %(code)s; 786251Sgblack@eecs.umich.edu } else { 796251Sgblack@eecs.umich.edu %(else_code)s; 806251Sgblack@eecs.umich.edu } 816251Sgblack@eecs.umich.edu %(op_wb)s; 826251Sgblack@eecs.umich.edu return NoFault; 836251Sgblack@eecs.umich.edu } 846019Shines@cs.fsu.edu}}; 856251Sgblack@eecs.umich.edu 866019Shines@cs.fsu.eduoutput decoder {{ 876275Sgblack@eecs.umich.edu inline SeqOpBase::SeqOpBase( 886275Sgblack@eecs.umich.edu ExtMachInst machInst, const char * mnemonic, const char * instMnem, 896275Sgblack@eecs.umich.edu uint64_t setFlags, uint16_t _target, uint8_t _cc) : 906275Sgblack@eecs.umich.edu X86MicroopBase(machInst, mnemonic, instMnem, setFlags, No_OpClass), 916275Sgblack@eecs.umich.edu target(_target), cc(_cc) 926251Sgblack@eecs.umich.edu { 936019Shines@cs.fsu.edu } 946275Sgblack@eecs.umich.edu}}; 956019Shines@cs.fsu.edu 966275Sgblack@eecs.umich.edudef template SeqOpConstructor {{ 976019Shines@cs.fsu.edu inline %(class_name)s::%(class_name)s( 986251Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, 996019Shines@cs.fsu.edu uint64_t setFlags, uint16_t _target, uint8_t _cc) : 1006251Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1016251Sgblack@eecs.umich.edu setFlags, _target, _cc) 1026019Shines@cs.fsu.edu { 1036251Sgblack@eecs.umich.edu %(constructor)s; 1046019Shines@cs.fsu.edu } 1057105Sgblack@eecs.umich.edu}}; 1066019Shines@cs.fsu.edu 1077105Sgblack@eecs.umich.eduoutput decoder {{ 1087105Sgblack@eecs.umich.edu std::string SeqOpBase::generateDisassembly(Addr pc, 1097105Sgblack@eecs.umich.edu const SymbolTable *symtab) const 1106019Shines@cs.fsu.edu { 1116019Shines@cs.fsu.edu std::stringstream response; 1127105Sgblack@eecs.umich.edu 1137105Sgblack@eecs.umich.edu printMnemonic(response, instMnem, mnemonic); 1147105Sgblack@eecs.umich.edu ccprintf(response, "%#x", target); 1156019Shines@cs.fsu.edu 1166019Shines@cs.fsu.edu return response.str(); 1176251Sgblack@eecs.umich.edu } 1186019Shines@cs.fsu.edu}}; 1197106Sgblack@eecs.umich.edu 1207103Sgblack@eecs.umich.edulet {{ 1217103Sgblack@eecs.umich.edu class SeqOp(X86Microop): 1227103Sgblack@eecs.umich.edu def __init__(self, target, flags=None): 1237103Sgblack@eecs.umich.edu self.target = target 1247103Sgblack@eecs.umich.edu if flags: 1257103Sgblack@eecs.umich.edu if not isinstance(flags, (list, tuple)): 1267103Sgblack@eecs.umich.edu raise Exception, "flags must be a list or tuple of flags" 1277103Sgblack@eecs.umich.edu self.cond = " | ".join(flags) 1287103Sgblack@eecs.umich.edu self.className += "Flags" 1297103Sgblack@eecs.umich.edu else: 1307103Sgblack@eecs.umich.edu self.cond = "0" 1317103Sgblack@eecs.umich.edu 1327103Sgblack@eecs.umich.edu def getAllocator(self, microFlags): 1337103Sgblack@eecs.umich.edu allocator = '''new %(class_name)s(machInst, macrocodeBlock, 1347106Sgblack@eecs.umich.edu %(flags)s, %(target)s, %(cc)s)''' % { 1357106Sgblack@eecs.umich.edu "class_name" : self.className, 1367106Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 1377106Sgblack@eecs.umich.edu "target" : self.target, 1387106Sgblack@eecs.umich.edu "cc" : self.cond} 1397106Sgblack@eecs.umich.edu return allocator 1407106Sgblack@eecs.umich.edu 1417106Sgblack@eecs.umich.edu class Br(SeqOp): 1427106Sgblack@eecs.umich.edu className = "MicroBranch" 1437106Sgblack@eecs.umich.edu 1447106Sgblack@eecs.umich.edu def getAllocator(self, microFlags): 1457106Sgblack@eecs.umich.edu if "IsLastMicroop" in microFlags: 1467106Sgblack@eecs.umich.edu microFlags.remove("IsLastMicroop") 1477106Sgblack@eecs.umich.edu if not "IsDelayedCommit" in microFlags: 1487106Sgblack@eecs.umich.edu microFlags.append("IsDelayedCommit") 1497106Sgblack@eecs.umich.edu return super(Br, self).getAllocator(microFlags) 1507106Sgblack@eecs.umich.edu 1517106Sgblack@eecs.umich.edu class Eret(SeqOp): 1527106Sgblack@eecs.umich.edu target = "normalMicroPC(0)" 1537106Sgblack@eecs.umich.edu className = "Eret" 1547106Sgblack@eecs.umich.edu 1557106Sgblack@eecs.umich.edu def __init__(self, flags=None): 1567106Sgblack@eecs.umich.edu if flags: 1577106Sgblack@eecs.umich.edu if not isinstance(flags, (list, tuple)): 1587106Sgblack@eecs.umich.edu raise Exception, "flags must be a list or tuple of flags" 159 self.cond = " | ".join(flags) 160 self.className += "Flags" 161 else: 162 self.cond = "0" 163 164 def getAllocator(self, microFlags): 165 if not "IsLastMicroop" in microFlags: 166 microFlags.append("IsLastMicroop") 167 if "IsDelayedCommit" in microFlags: 168 microFlags.remove("IsDelayedCommit") 169 return super(Eret, self).getAllocator(microFlags) 170 171 iop = InstObjParams("br", "MicroBranchFlags", "SeqOpBase", 172 {"code": "nuIP = target;", 173 "else_code": "nuIP = nuIP;", 174 "cond_test": "checkCondition(ccFlagBits, cc)"}) 175 exec_output += SeqOpExecute.subst(iop) 176 header_output += SeqOpDeclare.subst(iop) 177 decoder_output += SeqOpConstructor.subst(iop) 178 iop = InstObjParams("br", "MicroBranch", "SeqOpBase", 179 {"code": "nuIP = target;", 180 "else_code": "nuIP = nuIP;", 181 "cond_test": "true"}) 182 exec_output += SeqOpExecute.subst(iop) 183 header_output += SeqOpDeclare.subst(iop) 184 decoder_output += SeqOpConstructor.subst(iop) 185 microopClasses["br"] = Br 186 187 iop = InstObjParams("eret", "EretFlags", "SeqOpBase", 188 {"code": "", "else_code": "", 189 "cond_test": "checkCondition(ccFlagBits, cc)"}) 190 exec_output += SeqOpExecute.subst(iop) 191 header_output += SeqOpDeclare.subst(iop) 192 decoder_output += SeqOpConstructor.subst(iop) 193 iop = InstObjParams("eret", "Eret", "SeqOpBase", 194 {"code": "", "else_code": "", 195 "cond_test": "true"}) 196 exec_output += SeqOpExecute.subst(iop) 197 header_output += SeqOpDeclare.subst(iop) 198 decoder_output += SeqOpConstructor.subst(iop) 199 microopClasses["eret"] = Eret 200}}; 201