seqop.isa revision 5692:0d6addcde185
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Neither the name of 30// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 31// contributors may be used to endorse or promote products derived from 32// this software without specific prior written permission. No right of 33// sublicense is granted herewith. Derivatives of the software and 34// output created using the software may be prepared, but only for 35// Non-Commercial Uses. Derivatives of the software may be shared with 36// others provided: (i) the others agree to abide by the list of 37// conditions herein which includes the Non-Commercial Use restrictions; 38// and (ii) such Derivatives of the software include the above copyright 39// notice to acknowledge the contribution from this software where 40// applicable, this list of conditions and the disclaimer below. 41// 42// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 43// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 44// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 45// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 46// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 47// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 48// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 49// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 50// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 51// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 52// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53// 54// Authors: Gabe Black 55 56output header {{ 57 class SeqOpBase : public X86ISA::X86MicroopBase 58 { 59 protected: 60 uint16_t target; 61 uint8_t cc; 62 63 public: 64 SeqOpBase(ExtMachInst _machInst, const char * instMnem, 65 const char * mnemonic, 66 bool isMicro, bool isDelayed, bool isFirst, bool isLast, 67 uint16_t _target, uint8_t _cc); 68 69 SeqOpBase(ExtMachInst _machInst, const char * instMnem, 70 const char * mnemonic, 71 uint16_t _target, uint8_t _cc); 72 73 std::string generateDisassembly(Addr pc, 74 const SymbolTable *symtab) const; 75 }; 76}}; 77 78def template SeqOpDeclare {{ 79 class %(class_name)s : public %(base_class)s 80 { 81 private: 82 void buildMe(); 83 public: 84 %(class_name)s(ExtMachInst _machInst, const char * instMnem, 85 bool isMicro, bool isDelayed, bool isFirst, bool isLast, 86 uint16_t _target, uint8_t _cc); 87 88 %(class_name)s(ExtMachInst _machInst, const char * instMnem, 89 uint16_t _target, uint8_t _cc); 90 91 %(BasicExecDeclare)s 92 }; 93}}; 94 95def template SeqOpExecute {{ 96 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 97 Trace::InstRecord *traceData) const 98 { 99 %(op_decl)s; 100 %(op_rd)s; 101 if (%(cond_test)s) { 102 %(code)s; 103 } else { 104 %(else_code)s; 105 } 106 %(op_wb)s; 107 return NoFault; 108 } 109}}; 110 111output decoder {{ 112 inline SeqOpBase::SeqOpBase( 113 ExtMachInst machInst, const char * mnemonic, const char * instMnem, 114 uint16_t _target, uint8_t _cc) : 115 X86MicroopBase(machInst, mnemonic, instMnem, 116 false, false, false, false, No_OpClass), 117 target(_target), cc(_cc) 118 { 119 } 120 121 inline SeqOpBase::SeqOpBase( 122 ExtMachInst machInst, const char * mnemonic, const char * instMnem, 123 bool isMicro, bool isDelayed, bool isFirst, bool isLast, 124 uint16_t _target, uint8_t _cc) : 125 X86MicroopBase(machInst, mnemonic, instMnem, 126 isMicro, isDelayed, isFirst, isLast, No_OpClass), 127 target(_target), cc(_cc) 128 { 129 } 130}}; 131 132def template SeqOpConstructor {{ 133 134 inline void %(class_name)s::buildMe() 135 { 136 %(constructor)s; 137 } 138 139 inline %(class_name)s::%(class_name)s( 140 ExtMachInst machInst, const char * instMnem, 141 uint16_t _target, uint8_t _cc) : 142 %(base_class)s(machInst, "%(mnemonic)s", instMnem, _target, _cc) 143 { 144 buildMe(); 145 } 146 147 inline %(class_name)s::%(class_name)s( 148 ExtMachInst machInst, const char * instMnem, 149 bool isMicro, bool isDelayed, bool isFirst, bool isLast, 150 uint16_t _target, uint8_t _cc) : 151 %(base_class)s(machInst, "%(mnemonic)s", instMnem, 152 isMicro, isDelayed, isFirst, isLast, _target, _cc) 153 { 154 buildMe(); 155 } 156}}; 157 158output decoder {{ 159 std::string SeqOpBase::generateDisassembly(Addr pc, 160 const SymbolTable *symtab) const 161 { 162 std::stringstream response; 163 164 printMnemonic(response, instMnem, mnemonic); 165 ccprintf(response, "%#x", target); 166 167 return response.str(); 168 } 169}}; 170 171let {{ 172 class SeqOp(X86Microop): 173 def __init__(self, target, flags=None): 174 self.target = target 175 if flags: 176 if not isinstance(flags, (list, tuple)): 177 raise Exception, "flags must be a list or tuple of flags" 178 self.cond = " | ".join(flags) 179 self.className += "Flags" 180 else: 181 self.cond = "0" 182 183 def getAllocator(self, *microFlags): 184 allocator = '''new %(class_name)s(machInst, mnemonic 185 %(flags)s, %(target)s, %(cc)s)''' % { 186 "class_name" : self.className, 187 "flags" : self.microFlagsText(microFlags), 188 "target" : self.target, 189 "cc" : self.cond} 190 return allocator 191 192 class Br(SeqOp): 193 className = "MicroBranch" 194 195 def getAllocator(self, *microFlags): 196 (is_micro, is_delayed, is_first, is_last) = microFlags 197 is_last = False 198 is_delayed = True 199 microFlags = (is_micro, is_delayed, is_first, is_last) 200 return super(Br, self).getAllocator(*microFlags) 201 202 class Eret(SeqOp): 203 target = "normalMicroPC(0)" 204 className = "Eret" 205 206 def __init__(self, flags=None): 207 if flags: 208 if not isinstance(flags, (list, tuple)): 209 raise Exception, "flags must be a list or tuple of flags" 210 self.cond = " | ".join(flags) 211 self.className += "Flags" 212 else: 213 self.cond = "0" 214 215 def getAllocator(self, *microFlags): 216 (is_micro, is_delayed, is_first, is_last) = microFlags 217 is_last = True 218 is_delayed = False 219 microFlags = (is_micro, is_delayed, is_first, is_last) 220 return super(Eret, self).getAllocator(*microFlags) 221 222 iop = InstObjParams("br", "MicroBranchFlags", "SeqOpBase", 223 {"code": "nuIP = target", 224 "else_code": "nuIP = nuIP", 225 "cond_test": "checkCondition(ccFlagBits, cc)"}) 226 exec_output += SeqOpExecute.subst(iop) 227 header_output += SeqOpDeclare.subst(iop) 228 decoder_output += SeqOpConstructor.subst(iop) 229 iop = InstObjParams("br", "MicroBranch", "SeqOpBase", 230 {"code": "nuIP = target", 231 "else_code": "nuIP = nuIP", 232 "cond_test": "true"}) 233 exec_output += SeqOpExecute.subst(iop) 234 header_output += SeqOpDeclare.subst(iop) 235 decoder_output += SeqOpConstructor.subst(iop) 236 microopClasses["br"] = Br 237 238 iop = InstObjParams("eret", "EretFlags", "SeqOpBase", 239 {"code": "", "else_code": "", 240 "cond_test": "checkCondition(ccFlagBits, cc)"}) 241 exec_output += SeqOpExecute.subst(iop) 242 header_output += SeqOpDeclare.subst(iop) 243 decoder_output += SeqOpConstructor.subst(iop) 244 iop = InstObjParams("eret", "Eret", "SeqOpBase", 245 {"code": "", "else_code": "", 246 "cond_test": "true"}) 247 exec_output += SeqOpExecute.subst(iop) 248 header_output += SeqOpDeclare.subst(iop) 249 decoder_output += SeqOpConstructor.subst(iop) 250 microopClasses["eret"] = Eret 251}}; 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