seqop.isa revision 5662 
1// Copyright (c) 2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// Redistribution and use of this software in source and binary forms,
5// with or without modification, are permitted provided that the
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34// output created using the software may be prepared, but only for
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42// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
43// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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53//
54// Authors: Gabe Black
55
56output header {{
57    class SeqOpBase : public X86ISA::X86MicroopBase
58    {
59      protected:
60        uint16_t target;
61        uint8_t cc;
62
63      public:
64        SeqOpBase(ExtMachInst _machInst, const char * instMnem,
65                const char * mnemonic,
66                bool isMicro, bool isDelayed, bool isFirst, bool isLast,
67                uint16_t _target, uint8_t _cc);
68
69        SeqOpBase(ExtMachInst _machInst, const char * instMnem,
70                const char * mnemonic,
71                uint16_t _target, uint8_t _cc);
72
73        std::string generateDisassembly(Addr pc,
74                const SymbolTable *symtab) const;
75    };
76}};
77
78def template SeqOpDeclare {{
79    class %(class_name)s : public %(base_class)s
80    {
81      private:
82        void buildMe();
83      public:
84        %(class_name)s(ExtMachInst _machInst, const char * instMnem,
85                bool isMicro, bool isDelayed, bool isFirst, bool isLast,
86                uint16_t _target, uint8_t _cc);
87
88        %(class_name)s(ExtMachInst _machInst, const char * instMnem,
89                uint16_t _target, uint8_t _cc);
90
91        %(BasicExecDeclare)s
92    };
93}};
94
95def template SeqOpExecute {{
96        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
97                Trace::InstRecord *traceData) const
98        {
99            %(op_decl)s;
100            %(op_rd)s;
101            if (%(cond_test)s) {
102                %(code)s;
103            } else {
104                %(else_code)s;
105            }
106            %(op_wb)s;
107            return NoFault;
108        }
109}};
110
111output decoder {{
112    inline SeqOpBase::SeqOpBase(
113            ExtMachInst machInst, const char * mnemonic, const char * instMnem,
114            uint16_t _target, uint8_t _cc) :
115        X86MicroopBase(machInst, mnemonic, instMnem,
116                false, false, false, false, No_OpClass),
117        target(_target), cc(_cc)
118    {
119    }
120
121    inline SeqOpBase::SeqOpBase(
122            ExtMachInst machInst, const char * mnemonic, const char * instMnem,
123            bool isMicro, bool isDelayed, bool isFirst, bool isLast,
124            uint16_t _target, uint8_t _cc) :
125        X86MicroopBase(machInst, mnemonic, instMnem,
126                isMicro, isDelayed, isFirst, isLast, No_OpClass),
127                target(_target), cc(_cc)
128    {
129    }
130}};
131
132def template SeqOpConstructor {{
133
134    inline void %(class_name)s::buildMe()
135    {
136        %(constructor)s;
137    }
138
139    inline %(class_name)s::%(class_name)s(
140            ExtMachInst machInst, const char * instMnem,
141            uint16_t _target, uint8_t _cc) :
142        %(base_class)s(machInst, "%(mnemonic)s", instMnem, _target, _cc)
143    {
144        buildMe();
145    }
146
147    inline %(class_name)s::%(class_name)s(
148            ExtMachInst machInst, const char * instMnem,
149            bool isMicro, bool isDelayed, bool isFirst, bool isLast,
150            uint16_t _target, uint8_t _cc) :
151        %(base_class)s(machInst, "%(mnemonic)s", instMnem,
152                isMicro, isDelayed, isFirst, isLast, _target, _cc)
153    {
154        buildMe();
155    }
156}};
157
158output decoder {{
159    std::string SeqOpBase::generateDisassembly(Addr pc,
160            const SymbolTable *symtab) const
161    {
162        std::stringstream response;
163
164        printMnemonic(response, instMnem, mnemonic);
165        ccprintf(response, "%#x", target);
166
167        return response.str();
168    }
169}};
170
171let {{
172    class SeqOp(X86Microop):
173        def __init__(self, target, flags=None):
174            self.target = target
175            if flags:
176                if not isinstance(flags, (list, tuple)):
177                    raise Exception, "flags must be a list or tuple of flags"
178                self.cond = " | ".join(flags)
179                self.className += "Flags"
180            else:
181                self.cond = "0"
182
183        def getAllocator(self, *microFlags):
184            allocator = '''new %(class_name)s(machInst, mnemonic
185                    %(flags)s, %(target)s, %(cc)s)''' % {
186                "class_name" : self.className,
187                "flags" : self.microFlagsText(microFlags),
188                "target" : self.target,
189                "cc" : self.cond}
190            return allocator
191
192    class Br(SeqOp):
193        className = "MicroBranch"
194
195        def getAllocator(self, *microFlags):
196            (is_micro, is_delayed, is_first, is_last) = microFlags
197            is_last = False
198            microFlags = (is_micro, is_delayed, is_first, is_last)
199            return super(Br, self).getAllocator(*microFlags)
200
201    iop = InstObjParams("br", "MicroBranchFlags", "SeqOpBase",
202            {"code": "nuIP = target",
203             "else_code": "nuIP = nuIP",
204             "cond_test": "checkCondition(ccFlagBits, cc)"})
205    exec_output += SeqOpExecute.subst(iop)
206    header_output += SeqOpDeclare.subst(iop)
207    decoder_output += SeqOpConstructor.subst(iop)
208    iop = InstObjParams("br", "MicroBranch", "SeqOpBase",
209            {"code": "nuIP = target",
210             "else_code": "nuIP = nuIP",
211             "cond_test": "true"})
212    exec_output += SeqOpExecute.subst(iop)
213    header_output += SeqOpDeclare.subst(iop)
214    decoder_output += SeqOpConstructor.subst(iop)
215    microopClasses["br"] = Br
216}};
217