regop.isa revision 6742:a2a79fe9655d
12SN/A// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 21762SN/A// All rights reserved. 32SN/A// 42SN/A// Redistribution and use of this software in source and binary forms, 52SN/A// with or without modification, are permitted provided that the 62SN/A// following conditions are met: 72SN/A// 82SN/A// The software must be used only for Non-Commercial Use which means any 92SN/A// use which is NOT directed to receiving any direct monetary 102SN/A// compensation for, or commercial advantage from such use. Illustrative 112SN/A// examples of non-commercial use are academic research, personal study, 122SN/A// teaching, education and corporate research & development. 132SN/A// Illustrative examples of commercial use are distributing products for 142SN/A// commercial advantage and providing services using the software for 152SN/A// commercial advantage. 162SN/A// 172SN/A// If you wish to use this software or functionality therein that may be 182SN/A// covered by patents for commercial use, please contact: 192SN/A// Director of Intellectual Property Licensing 202SN/A// Office of Strategy and Technology 212SN/A// Hewlett-Packard Company 222SN/A// 1501 Page Mill Road 232SN/A// Palo Alto, California 94304 242SN/A// 252SN/A// Redistributions of source code must retain the above copyright notice, 262SN/A// this list of conditions and the following disclaimer. Redistributions 272665Ssaidi@eecs.umich.edu// in binary form must reproduce the above copyright notice, this list of 282665Ssaidi@eecs.umich.edu// conditions and the following disclaimer in the documentation and/or 292SN/A// other materials provided with the distribution. Neither the name of 302SN/A// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 312439SN/A// contributors may be used to endorse or promote products derived from 32146SN/A// this software without specific prior written permission. No right of 33146SN/A// sublicense is granted herewith. Derivatives of the software and 34146SN/A// output created using the software may be prepared, but only for 35146SN/A// Non-Commercial Uses. Derivatives of the software may be shared with 36146SN/A// others provided: (i) the others agree to abide by the list of 37146SN/A// conditions herein which includes the Non-Commercial Use restrictions; 381717SN/A// and (ii) such Derivatives of the software include the above copyright 39146SN/A// notice to acknowledge the contribution from this software where 401717SN/A// applicable, this list of conditions and the disclaimer below. 412190SN/A// 422680Sktlim@umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 43146SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 441977SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 451717SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 462623SN/A// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 471717SN/A// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 48146SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 491917SN/A// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 502592SN/A// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 512036SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 52146SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 53146SN/A// 5456SN/A// Authors: Gabe Black 5556SN/A 5656SN/A////////////////////////////////////////////////////////////////////////// 57695SN/A// 582SN/A// RegOp Microop templates 591858SN/A// 6056SN/A////////////////////////////////////////////////////////////////////////// 61146SN/A 622171SN/Adef template MicroRegOpExecute {{ 632170SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 642170SN/A Trace::InstRecord *traceData) const 65146SN/A { 662462SN/A Fault fault = NoFault; 67146SN/A 682SN/A DPRINTF(X86, "The data size is %d\n", dataSize); 692SN/A %(op_decl)s; 702449SN/A %(op_rd)s; 711355SN/A 722623SN/A if(%(cond_check)s) 732623SN/A { 74224SN/A %(code)s; 751858SN/A %(flag_code)s; 762518SN/A } 772420SN/A else 782519SN/A { 792520SN/A %(else_code)s; 802420SN/A } 812SN/A 822680Sktlim@umich.edu //Write the resulting state to the execution context 832672Sktlim@umich.edu if(fault == NoFault) 842680Sktlim@umich.edu { 852SN/A %(op_wb)s; 862SN/A } 87334SN/A return fault; 88140SN/A } 89334SN/A}}; 902SN/A 912SN/Adef template MicroRegOpImmExecute {{ 922SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 932680Sktlim@umich.edu Trace::InstRecord *traceData) const 942SN/A { 952SN/A Fault fault = NoFault; 962623SN/A 972SN/A %(op_decl)s; 982SN/A %(op_rd)s; 992SN/A 100180SN/A if(%(cond_check)s) 1012623SN/A { 102393SN/A %(code)s; 103393SN/A %(flag_code)s; 104393SN/A } 105393SN/A else 106384SN/A { 107384SN/A %(else_code)s; 108393SN/A } 1092623SN/A 110393SN/A //Write the resulting state to the execution context 111393SN/A if(fault == NoFault) 112393SN/A { 113393SN/A %(op_wb)s; 114384SN/A } 115189SN/A return fault; 116189SN/A } 1172623SN/A}}; 1182SN/A 119729SN/Adef template MicroRegOpDeclare {{ 120334SN/A class %(class_name)s : public %(base_class)s 1212SN/A { 1222SN/A protected: 1232SN/A void buildMe(); 1242SN/A 1252SN/A public: 1262SN/A %(class_name)s(ExtMachInst _machInst, 1272SN/A const char * instMnem, 1282SN/A bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1292SN/A InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1302SN/A uint8_t _dataSize, uint16_t _ext); 1312SN/A 1322SN/A %(class_name)s(ExtMachInst _machInst, 1331001SN/A const char * instMnem, 1341001SN/A InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1351001SN/A uint8_t _dataSize, uint16_t _ext); 1361001SN/A 1371001SN/A %(BasicExecDeclare)s 1382SN/A }; 1392SN/A}}; 1402SN/A 1412SN/Adef template MicroRegOpImmDeclare {{ 1422SN/A 1432SN/A class %(class_name)s : public %(base_class)s 1442SN/A { 1452SN/A protected: 1462SN/A void buildMe(); 1472SN/A 1482SN/A public: 1492SN/A %(class_name)s(ExtMachInst _machInst, 1502SN/A const char * instMnem, 1512SN/A bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1522SN/A InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 1532SN/A uint8_t _dataSize, uint16_t _ext); 1542SN/A 1552390SN/A %(class_name)s(ExtMachInst _machInst, 1562390SN/A const char * instMnem, 1572390SN/A InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 1582390SN/A uint8_t _dataSize, uint16_t _ext); 1592390SN/A 1602390SN/A %(BasicExecDeclare)s 1612390SN/A }; 1622390SN/A}}; 1632390SN/A 1642390SN/Adef template MicroRegOpConstructor {{ 1652390SN/A 1662390SN/A inline void %(class_name)s::buildMe() 167385SN/A { 1682SN/A %(constructor)s; 1692SN/A } 1702SN/A 1712623SN/A inline %(class_name)s::%(class_name)s( 172334SN/A ExtMachInst machInst, const char * instMnem, 173334SN/A InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1742623SN/A uint8_t _dataSize, uint16_t _ext) : 175334SN/A %(base_class)s(machInst, "%(mnemonic)s", instMnem, 176334SN/A false, false, false, false, 177334SN/A _src1, _src2, _dest, _dataSize, _ext, 1782623SN/A %(op_class)s) 1792SN/A { 180921SN/A buildMe(); 181224SN/A } 182237SN/A 1832190SN/A inline %(class_name)s::%(class_name)s( 1842SN/A ExtMachInst machInst, const char * instMnem, 1852SN/A bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1862SN/A InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 1872623SN/A uint8_t _dataSize, uint16_t _ext) : 1882SN/A %(base_class)s(machInst, "%(mnemonic)s", instMnem, 189921SN/A isMicro, isDelayed, isFirst, isLast, 190224SN/A _src1, _src2, _dest, _dataSize, _ext, 1912190SN/A %(op_class)s) 1922SN/A { 1932SN/A buildMe(); 1942SN/A } 1952SN/A}}; 1962SN/A 1972SN/Adef template MicroRegOpImmConstructor {{ 1982SN/A 199595SN/A inline void %(class_name)s::buildMe() 2002623SN/A { 201595SN/A %(constructor)s; 2022390SN/A } 2031080SN/A 2041080SN/A inline %(class_name)s::%(class_name)s( 2051080SN/A ExtMachInst machInst, const char * instMnem, 2061080SN/A InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 2071080SN/A uint8_t _dataSize, uint16_t _ext) : 2081080SN/A %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2091080SN/A false, false, false, false, 2101121SN/A _src1, _imm8, _dest, _dataSize, _ext, 2112107SN/A %(op_class)s) 2121089SN/A { 2131089SN/A buildMe(); 2141080SN/A } 2151080SN/A 2161080SN/A inline %(class_name)s::%(class_name)s( 2171080SN/A ExtMachInst machInst, const char * instMnem, 218595SN/A bool isMicro, bool isDelayed, bool isFirst, bool isLast, 2192623SN/A InstRegIndex _src1, uint8_t _imm8, InstRegIndex _dest, 2202623SN/A uint8_t _dataSize, uint16_t _ext) : 221595SN/A %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2222090SN/A isMicro, isDelayed, isFirst, isLast, 2232190SN/A _src1, _imm8, _dest, _dataSize, _ext, 2242190SN/A %(op_class)s) 225595SN/A { 2262205SN/A buildMe(); 2272205SN/A } 2282190SN/A}}; 2292190SN/A 230595SN/Aoutput header {{ 231595SN/A void 2322390SN/A divide(uint64_t dividend, uint64_t divisor, 2332423SN/A uint64_t "ient, uint64_t &remainder); 2342390SN/A 235595SN/A enum SegmentSelectorCheck { 236595SN/A SegNoCheck, SegCSCheck, SegCallGateCheck, SegIntGateCheck, 237595SN/A SegSoftIntGateCheck, SegSSCheck, SegIretCheck, SegIntCSCheck, 2382623SN/A SegTRCheck, SegTSSCheck, SegInGDTCheck, SegLDTCheck 239595SN/A }; 2402390SN/A 2411080SN/A enum LongModeDescriptorType { 242595SN/A LDT64 = 2, 2431080SN/A AvailableTSS64 = 9, 2441080SN/A BusyTSS64 = 0xb, 245595SN/A CallGate64 = 0xc, 2462190SN/A IntGate64 = 0xe, 2471080SN/A TrapGate64 = 0xf 2481080SN/A }; 2491080SN/A}}; 2501121SN/A 2512107SN/Aoutput decoder {{ 2521089SN/A void 2531080SN/A divide(uint64_t dividend, uint64_t divisor, 2541089SN/A uint64_t "ient, uint64_t &remainder) 2551080SN/A { 2561080SN/A //Check for divide by zero. 2571080SN/A if (divisor == 0) 258595SN/A panic("Divide by zero!\\n"); 2592422SN/A //If the divisor is bigger than the dividend, don't do anything. 2601080SN/A if (divisor <= dividend) { 2612090SN/A //Shift the divisor so it's msb lines up with the dividend. 2621080SN/A int dividendMsb = findMsbSet(dividend); 263595SN/A int divisorMsb = findMsbSet(divisor); 2642190SN/A int shift = dividendMsb - divisorMsb; 2652190SN/A divisor <<= shift; 266595SN/A //Compute what we'll add to the quotient if the divisor isn't 2672190SN/A //now larger than the dividend. 2681098SN/A uint64_t quotientBit = 1; 2691098SN/A quotientBit <<= shift; 2701098SN/A //If we need to step back a bit (no pun intended) because the 2712190SN/A //divisor got too to large, do that here. This is the "or two" 2721098SN/A //part of one or two bit division. 2731098SN/A if (divisor > dividend) { 2741098SN/A quotientBit >>= 1; 2752012SN/A divisor >>= 1; 2761098SN/A } 2771098SN/A //Decrement the remainder and increment the quotient. 278595SN/A quotient += quotientBit; 2792205SN/A remainder -= divisor; 2802205SN/A } 2812205SN/A } 282595SN/A}}; 2832390SN/A 2842420SN/Alet {{ 2852423SN/A # Make these empty strings so that concatenating onto 2862390SN/A # them will always work. 287595SN/A header_output = "" 288595SN/A decoder_output = "" 2891858SN/A exec_output = "" 2902SN/A 2912623SN/A immTemplates = ( 2922SN/A MicroRegOpImmDeclare, 2932680Sktlim@umich.edu MicroRegOpImmConstructor, 2942SN/A MicroRegOpImmExecute) 2952SN/A 2962SN/A regTemplates = ( 2971858SN/A MicroRegOpDeclare, 2982SN/A MicroRegOpConstructor, 2992623SN/A MicroRegOpExecute) 3002SN/A 3012SN/A class RegOpMeta(type): 3022SN/A def buildCppClasses(self, name, Name, suffix, \ 3032680Sktlim@umich.edu code, flag_code, cond_check, else_code): 3042SN/A 3052190SN/A # Globals to stick the output in 3062SN/A global header_output 3072SN/A global decoder_output 3082SN/A global exec_output 3092SN/A 3102SN/A # Stick all the code together so it can be searched at once 3112623SN/A allCode = "|".join((code, flag_code, cond_check, else_code)) 3122SN/A 3131858SN/A # If op2 is used anywhere, make register and immediate versions 3142626SN/A # of this code. 3152SN/A matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?") 3162SN/A match = matcher.search(allCode) 3171133SN/A if match: 3182SN/A typeQual = "" 3192190SN/A if match.group("typeQual"): 3202107SN/A typeQual = match.group("typeQual") 3212107SN/A src2_name = "%spsrc2%s" % (match.group("prefix"), typeQual) 3222190SN/A self.buildCppClasses(name, Name, suffix, 3232SN/A matcher.sub(src2_name, code), 3242107SN/A matcher.sub(src2_name, flag_code), 3252SN/A matcher.sub(src2_name, cond_check), 3262SN/A matcher.sub(src2_name, else_code)) 3272SN/A imm_name = "%simm8" % match.group("prefix") 3282SN/A self.buildCppClasses(name + "i", Name, suffix + "Imm", 3292SN/A matcher.sub(imm_name, code), 3302190SN/A matcher.sub(imm_name, flag_code), 3312107SN/A matcher.sub(imm_name, cond_check), 3322107SN/A matcher.sub(imm_name, else_code)) 3332SN/A return 3342SN/A 3352SN/A # If there's something optional to do with flags, generate 3362SN/A # a version without it and fix up this version to use it. 3372SN/A if flag_code != "" or cond_check != "true": 3382SN/A self.buildCppClasses(name, Name, suffix, 3392SN/A code, "", "true", else_code) 3402190SN/A suffix = "Flags" + suffix 3412SN/A 3422SN/A # If psrc1 or psrc2 is used, we need to actually insert code to 3432190SN/A # compute it. 3442190SN/A matcher = re.compile("(?<!\w)psrc1(?!\w)") 3452190SN/A if matcher.search(allCode): 3462234SN/A code = "uint64_t psrc1 = pick(SrcReg1, 0, dataSize);" + code 3472680Sktlim@umich.edu matcher = re.compile("(?<!\w)psrc2(?!\w)") 3482SN/A if matcher.search(allCode): 3492SN/A code = "uint64_t psrc2 = pick(SrcReg2, 1, dataSize);" + code 3502190SN/A # Also make available versions which do sign extension 3512SN/A matcher = re.compile("(?<!\w)spsrc1(?!\w)") 3522SN/A if matcher.search(allCode): 3532SN/A code = "int64_t spsrc1 = signedPick(SrcReg1, 0, dataSize);" + code 3542623SN/A matcher = re.compile("(?<!\w)spsrc2(?!\w)") 3552SN/A if matcher.search(allCode): 3562623SN/A code = "int64_t spsrc2 = signedPick(SrcReg2, 1, dataSize);" + code 3572623SN/A matcher = re.compile("(?<!\w)simm8(?!\w)") 3582662Sstever@eecs.umich.edu if matcher.search(allCode): 3592623SN/A code = "int8_t simm8 = imm8;" + code 3602623SN/A 3612623SN/A base = "X86ISA::RegOp" 3622623SN/A 3632623SN/A # If imm8 shows up in the code, use the immediate templates, if 3642663Sstever@eecs.umich.edu # not, hopefully the register ones will be correct. 3652663Sstever@eecs.umich.edu templates = regTemplates 3662663Sstever@eecs.umich.edu matcher = re.compile("(?<!\w)s?imm8(?!\w)") 3672623SN/A if matcher.search(allCode): 3682662Sstever@eecs.umich.edu base += "Imm" 3692623SN/A templates = immTemplates 3702623SN/A 3712623SN/A # Get everything ready for the substitution 3722623SN/A iop = InstObjParams(name, Name + suffix, base, 3732623SN/A {"code" : code, 3742623SN/A "flag_code" : flag_code, 3752623SN/A "cond_check" : cond_check, 3762623SN/A "else_code" : else_code}) 3772SN/A 3782190SN/A # Generate the actual code (finally!) 3792427SN/A header_output += templates[0].subst(iop) 3802455SN/A decoder_output += templates[1].subst(iop) 3812427SN/A exec_output += templates[2].subst(iop) 3822SN/A 3832623SN/A 3842623SN/A def __new__(mcls, Name, bases, dict): 3852623SN/A abstract = False 3862SN/A name = Name.lower() 3872623SN/A if "abstract" in dict: 3882SN/A abstract = dict['abstract'] 3892623SN/A del dict['abstract'] 3902623SN/A 3912SN/A cls = super(RegOpMeta, mcls).__new__(mcls, Name, bases, dict) 3922623SN/A if not abstract: 3932623SN/A cls.className = Name 3942623SN/A cls.base_mnemonic = name 3952470SN/A code = cls.code 3962680Sktlim@umich.edu flag_code = cls.flag_code 3972623SN/A cond_check = cls.cond_check 3982623SN/A else_code = cls.else_code 3992623SN/A 4002623SN/A # Set up the C++ classes 4012623SN/A mcls.buildCppClasses(cls, name, Name, "", 4022623SN/A code, flag_code, cond_check, else_code) 4032623SN/A 4042623SN/A # Hook into the microassembler dict 4052623SN/A global microopClasses 4062623SN/A microopClasses[name] = cls 4072623SN/A 4082623SN/A allCode = "|".join((code, flag_code, cond_check, else_code)) 4092623SN/A 4102623SN/A # If op2 is used anywhere, make register and immediate versions 4112623SN/A # of this code. 4122623SN/A matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 4132671Sktlim@umich.edu if matcher.search(allCode): 4142680Sktlim@umich.edu microopClasses[name + 'i'] = cls 4152623SN/A return cls 4162623SN/A 4172623SN/A 4182623SN/A class RegOp(X86Microop): 4192623SN/A __metaclass__ = RegOpMeta 4202623SN/A # This class itself doesn't act as a microop 4212680Sktlim@umich.edu abstract = True 4222623SN/A 4232623SN/A # Default template parameter values 4242623SN/A flag_code = "" 4252420SN/A cond_check = "true" 4262SN/A else_code = ";" 4272623SN/A 4282623SN/A def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): 4292SN/A self.dest = dest 4302SN/A self.src1 = src1 4312623SN/A self.op2 = op2 4322623SN/A self.flags = flags 4332623SN/A self.dataSize = dataSize 4342623SN/A if flags is None: 4352SN/A self.ext = 0 4362623SN/A else: 4372644Sstever@eecs.umich.edu if not isinstance(flags, (list, tuple)): 4382644Sstever@eecs.umich.edu raise Exception, "flags must be a list or tuple of flags" 4392644Sstever@eecs.umich.edu self.ext = " | ".join(flags) 4402644Sstever@eecs.umich.edu self.className += "Flags" 4412623SN/A 4422SN/A def getAllocator(self, *microFlags): 4432SN/A className = self.className 4442623SN/A if self.mnemonic == self.base_mnemonic + 'i': 4452623SN/A className += "Imm" 4462623SN/A allocator = '''new %(class_name)s(machInst, macrocodeBlock 4472090SN/A %(flags)s, %(src1)s, %(op2)s, %(dest)s, 4481858SN/A %(dataSize)s, %(ext)s)''' % { 4492680Sktlim@umich.edu "class_name" : className, 4502SN/A "flags" : self.microFlagsText(microFlags), 4512470SN/A "src1" : self.src1, "op2" : self.op2, 4522SN/A "dest" : self.dest, 4532SN/A "dataSize" : self.dataSize, 4542SN/A "ext" : self.ext} 4552SN/A return allocator 4562190SN/A 4572623SN/A class LogicRegOp(RegOp): 4582190SN/A abstract = True 4592251SN/A flag_code = ''' 4602262SN/A //Don't have genFlags handle the OF or CF bits 4612262SN/A uint64_t mask = CFBit | ECFBit | OFBit; 4622251SN/A ccFlagBits = genFlags(ccFlagBits, ext & ~mask, DestReg, psrc1, op2); 4632251SN/A //If a logic microop wants to set these, it wants to set them to 0. 4642SN/A ccFlagBits &= ~(CFBit & ext); 4652SN/A ccFlagBits &= ~(ECFBit & ext); 4661858SN/A ccFlagBits &= ~(OFBit & ext); 4672SN/A ''' 4682SN/A 4692190SN/A class FlagRegOp(RegOp): 4702680Sktlim@umich.edu abstract = True 4712190SN/A flag_code = \ 4722SN/A "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, op2);" 4732SN/A 4742SN/A class SubRegOp(RegOp): 475 abstract = True 476 flag_code = \ 477 "ccFlagBits = genFlags(ccFlagBits, ext, DestReg, psrc1, ~op2, true);" 478 479 class CondRegOp(RegOp): 480 abstract = True 481 cond_check = "checkCondition(ccFlagBits, ext)" 482 483 class RdRegOp(RegOp): 484 abstract = True 485 def __init__(self, dest, src1=None, dataSize="env.dataSize"): 486 if not src1: 487 src1 = dest 488 super(RdRegOp, self).__init__(dest, src1, \ 489 "InstRegIndex(NUM_INTREGS)", None, dataSize) 490 491 class WrRegOp(RegOp): 492 abstract = True 493 def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): 494 super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \ 495 src1, src2, flags, dataSize) 496 497 class Add(FlagRegOp): 498 code = 'DestReg = merge(DestReg, psrc1 + op2, dataSize);' 499 500 class Or(LogicRegOp): 501 code = 'DestReg = merge(DestReg, psrc1 | op2, dataSize);' 502 503 class Adc(FlagRegOp): 504 code = ''' 505 CCFlagBits flags = ccFlagBits; 506 DestReg = merge(DestReg, psrc1 + op2 + flags.cf, dataSize); 507 ''' 508 509 class Sbb(SubRegOp): 510 code = ''' 511 CCFlagBits flags = ccFlagBits; 512 DestReg = merge(DestReg, psrc1 - op2 - flags.cf, dataSize); 513 ''' 514 515 class And(LogicRegOp): 516 code = 'DestReg = merge(DestReg, psrc1 & op2, dataSize)' 517 518 class Sub(SubRegOp): 519 code = 'DestReg = merge(DestReg, psrc1 - op2, dataSize)' 520 521 class Xor(LogicRegOp): 522 code = 'DestReg = merge(DestReg, psrc1 ^ op2, dataSize)' 523 524 class Mul1s(WrRegOp): 525 code = ''' 526 ProdLow = psrc1 * op2; 527 int halfSize = (dataSize * 8) / 2; 528 uint64_t shifter = (ULL(1) << halfSize); 529 uint64_t hiResult; 530 uint64_t psrc1_h = psrc1 / shifter; 531 uint64_t psrc1_l = psrc1 & mask(halfSize); 532 uint64_t psrc2_h = (op2 / shifter) & mask(halfSize); 533 uint64_t psrc2_l = op2 & mask(halfSize); 534 hiResult = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 535 ((psrc1_l * psrc2_l) / shifter)) /shifter) + 536 psrc1_h * psrc2_h; 537 if (bits(psrc1, dataSize * 8 - 1)) 538 hiResult -= op2; 539 if (bits(op2, dataSize * 8 - 1)) 540 hiResult -= psrc1; 541 ProdHi = hiResult; 542 ''' 543 flag_code = ''' 544 if ((-ProdHi & mask(dataSize * 8)) != 545 bits(ProdLow, dataSize * 8 - 1)) { 546 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 547 } else { 548 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 549 } 550 ''' 551 552 class Mul1u(WrRegOp): 553 code = ''' 554 ProdLow = psrc1 * op2; 555 int halfSize = (dataSize * 8) / 2; 556 uint64_t shifter = (ULL(1) << halfSize); 557 uint64_t psrc1_h = psrc1 / shifter; 558 uint64_t psrc1_l = psrc1 & mask(halfSize); 559 uint64_t psrc2_h = (op2 / shifter) & mask(halfSize); 560 uint64_t psrc2_l = op2 & mask(halfSize); 561 ProdHi = ((psrc1_l * psrc2_h + psrc1_h * psrc2_l + 562 ((psrc1_l * psrc2_l) / shifter)) / shifter) + 563 psrc1_h * psrc2_h; 564 ''' 565 flag_code = ''' 566 if (ProdHi) { 567 ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); 568 } else { 569 ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); 570 } 571 ''' 572 573 class Mulel(RdRegOp): 574 code = 'DestReg = merge(SrcReg1, ProdLow, dataSize);' 575 576 class Muleh(RdRegOp): 577 def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): 578 if not src1: 579 src1 = dest 580 super(RdRegOp, self).__init__(dest, src1, \ 581 "InstRegIndex(NUM_INTREGS)", flags, dataSize) 582 code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' 583 584 # One or two bit divide 585 class Div1(WrRegOp): 586 code = ''' 587 //These are temporaries so that modifying them later won't make 588 //the ISA parser think they're also sources. 589 uint64_t quotient = 0; 590 uint64_t remainder = psrc1; 591 //Similarly, this is a temporary so changing it doesn't make it 592 //a source. 593 uint64_t divisor = op2; 594 //This is a temporary just for consistency and clarity. 595 uint64_t dividend = remainder; 596 //Do the division. 597 divide(dividend, divisor, quotient, remainder); 598 //Record the final results. 599 Remainder = remainder; 600 Quotient = quotient; 601 Divisor = divisor; 602 ''' 603 604 # Step divide 605 class Div2(RegOp): 606 code = ''' 607 uint64_t dividend = Remainder; 608 uint64_t divisor = Divisor; 609 uint64_t quotient = Quotient; 610 uint64_t remainder = dividend; 611 int remaining = op2; 612 //If we overshot, do nothing. This lets us unrool division loops a 613 //little. 614 if (remaining) { 615 //Shift in bits from the low order portion of the dividend 616 while(dividend < divisor && remaining) { 617 dividend = (dividend << 1) | bits(SrcReg1, remaining - 1); 618 quotient <<= 1; 619 remaining--; 620 } 621 remainder = dividend; 622 //Do the division. 623 divide(dividend, divisor, quotient, remainder); 624 } 625 //Keep track of how many bits there are still to pull in. 626 DestReg = merge(DestReg, remaining, dataSize); 627 //Record the final results 628 Remainder = remainder; 629 Quotient = quotient; 630 ''' 631 flag_code = ''' 632 if (DestReg == 0) 633 ccFlagBits = ccFlagBits | (ext & EZFBit); 634 else 635 ccFlagBits = ccFlagBits & ~(ext & EZFBit); 636 ''' 637 638 class Divq(RdRegOp): 639 code = 'DestReg = merge(SrcReg1, Quotient, dataSize);' 640 641 class Divr(RdRegOp): 642 code = 'DestReg = merge(SrcReg1, Remainder, dataSize);' 643 644 class Mov(CondRegOp): 645 code = 'DestReg = merge(SrcReg1, op2, dataSize)' 646 else_code = 'DestReg = DestReg;' 647 648 # Shift instructions 649 650 class Sll(RegOp): 651 code = ''' 652 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 653 DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); 654 ''' 655 flag_code = ''' 656 // If the shift amount is zero, no flags should be modified. 657 if (shiftAmt) { 658 //Zero out any flags we might modify. This way we only have to 659 //worry about setting them. 660 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 661 int CFBits = 0; 662 //Figure out if we -would- set the CF bits if requested. 663 if (shiftAmt <= dataSize * 8 && 664 bits(SrcReg1, dataSize * 8 - shiftAmt)) { 665 CFBits = 1; 666 } 667 //If some combination of the CF bits need to be set, set them. 668 if ((ext & (CFBit | ECFBit)) && CFBits) 669 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 670 //Figure out what the OF bit should be. 671 if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1))) 672 ccFlagBits = ccFlagBits | OFBit; 673 //Use the regular mechanisms to calculate the other flags. 674 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 675 DestReg, psrc1, op2); 676 } 677 ''' 678 679 class Srl(RegOp): 680 code = ''' 681 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 682 // Because what happens to the bits shift -in- on a right shift 683 // is not defined in the C/C++ standard, we have to mask them out 684 // to be sure they're zero. 685 uint64_t logicalMask = mask(dataSize * 8 - shiftAmt); 686 DestReg = merge(DestReg, (psrc1 >> shiftAmt) & logicalMask, dataSize); 687 ''' 688 flag_code = ''' 689 // If the shift amount is zero, no flags should be modified. 690 if (shiftAmt) { 691 //Zero out any flags we might modify. This way we only have to 692 //worry about setting them. 693 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 694 //If some combination of the CF bits need to be set, set them. 695 if ((ext & (CFBit | ECFBit)) && 696 shiftAmt <= dataSize * 8 && 697 bits(SrcReg1, shiftAmt - 1)) { 698 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 699 } 700 //Figure out what the OF bit should be. 701 if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1)) 702 ccFlagBits = ccFlagBits | OFBit; 703 //Use the regular mechanisms to calculate the other flags. 704 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 705 DestReg, psrc1, op2); 706 } 707 ''' 708 709 class Sra(RegOp): 710 code = ''' 711 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 712 // Because what happens to the bits shift -in- on a right shift 713 // is not defined in the C/C++ standard, we have to sign extend 714 // them manually to be sure. 715 uint64_t arithMask = (shiftAmt == 0) ? 0 : 716 -bits(psrc1, dataSize * 8 - 1) << (dataSize * 8 - shiftAmt); 717 DestReg = merge(DestReg, (psrc1 >> shiftAmt) | arithMask, dataSize); 718 ''' 719 flag_code = ''' 720 // If the shift amount is zero, no flags should be modified. 721 if (shiftAmt) { 722 //Zero out any flags we might modify. This way we only have to 723 //worry about setting them. 724 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 725 //If some combination of the CF bits need to be set, set them. 726 uint8_t effectiveShift = 727 (shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8); 728 if ((ext & (CFBit | ECFBit)) && 729 bits(SrcReg1, effectiveShift - 1)) { 730 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 731 } 732 //Use the regular mechanisms to calculate the other flags. 733 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 734 DestReg, psrc1, op2); 735 } 736 ''' 737 738 class Ror(RegOp): 739 code = ''' 740 uint8_t shiftAmt = 741 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 742 uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 743 if(realShiftAmt) 744 { 745 uint64_t top = psrc1 << (dataSize * 8 - realShiftAmt); 746 uint64_t bottom = bits(psrc1, dataSize * 8, realShiftAmt); 747 DestReg = merge(DestReg, top | bottom, dataSize); 748 } 749 else 750 DestReg = merge(DestReg, DestReg, dataSize); 751 ''' 752 flag_code = ''' 753 // If the shift amount is zero, no flags should be modified. 754 if (shiftAmt) { 755 //Zero out any flags we might modify. This way we only have to 756 //worry about setting them. 757 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 758 //Find the most and second most significant bits of the result. 759 int msb = bits(DestReg, dataSize * 8 - 1); 760 int smsb = bits(DestReg, dataSize * 8 - 2); 761 //If some combination of the CF bits need to be set, set them. 762 if ((ext & (CFBit | ECFBit)) && msb) 763 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 764 //Figure out what the OF bit should be. 765 if ((ext & OFBit) && (msb ^ smsb)) 766 ccFlagBits = ccFlagBits | OFBit; 767 //Use the regular mechanisms to calculate the other flags. 768 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 769 DestReg, psrc1, op2); 770 } 771 ''' 772 773 class Rcr(RegOp): 774 code = ''' 775 uint8_t shiftAmt = 776 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 777 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 778 if(realShiftAmt) 779 { 780 CCFlagBits flags = ccFlagBits; 781 uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt); 782 if (realShiftAmt > 1) 783 top |= psrc1 << (dataSize * 8 - realShiftAmt + 1); 784 uint64_t bottom = bits(psrc1, dataSize * 8 - 1, realShiftAmt); 785 DestReg = merge(DestReg, top | bottom, dataSize); 786 } 787 else 788 DestReg = merge(DestReg, DestReg, dataSize); 789 ''' 790 flag_code = ''' 791 // If the shift amount is zero, no flags should be modified. 792 if (shiftAmt) { 793 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0; 794 //Zero out any flags we might modify. This way we only have to 795 //worry about setting them. 796 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 797 //Figure out what the OF bit should be. 798 if ((ext & OFBit) && (origCFBit ^ 799 bits(SrcReg1, dataSize * 8 - 1))) { 800 ccFlagBits = ccFlagBits | OFBit; 801 } 802 //If some combination of the CF bits need to be set, set them. 803 if ((ext & (CFBit | ECFBit)) && 804 (realShiftAmt == 0) ? origCFBit : 805 bits(SrcReg1, realShiftAmt - 1)) { 806 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 807 } 808 //Use the regular mechanisms to calculate the other flags. 809 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 810 DestReg, psrc1, op2); 811 } 812 ''' 813 814 class Rol(RegOp): 815 code = ''' 816 uint8_t shiftAmt = 817 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 818 uint8_t realShiftAmt = shiftAmt % (dataSize * 8); 819 if(realShiftAmt) 820 { 821 uint64_t top = psrc1 << realShiftAmt; 822 uint64_t bottom = 823 bits(psrc1, dataSize * 8 - 1, dataSize * 8 - realShiftAmt); 824 DestReg = merge(DestReg, top | bottom, dataSize); 825 } 826 else 827 DestReg = merge(DestReg, DestReg, dataSize); 828 ''' 829 flag_code = ''' 830 // If the shift amount is zero, no flags should be modified. 831 if (shiftAmt) { 832 //Zero out any flags we might modify. This way we only have to 833 //worry about setting them. 834 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 835 //The CF bits, if set, would be set to the lsb of the result. 836 int lsb = DestReg & 0x1; 837 int msb = bits(DestReg, dataSize * 8 - 1); 838 //If some combination of the CF bits need to be set, set them. 839 if ((ext & (CFBit | ECFBit)) && lsb) 840 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 841 //Figure out what the OF bit should be. 842 if ((ext & OFBit) && (msb ^ lsb)) 843 ccFlagBits = ccFlagBits | OFBit; 844 //Use the regular mechanisms to calculate the other flags. 845 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 846 DestReg, psrc1, op2); 847 } 848 ''' 849 850 class Rcl(RegOp): 851 code = ''' 852 uint8_t shiftAmt = 853 (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 854 uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); 855 if(realShiftAmt) 856 { 857 CCFlagBits flags = ccFlagBits; 858 uint64_t top = psrc1 << realShiftAmt; 859 uint64_t bottom = flags.cf << (realShiftAmt - 1); 860 if(shiftAmt > 1) 861 bottom |= 862 bits(psrc1, dataSize * 8 - 1, 863 dataSize * 8 - realShiftAmt + 1); 864 DestReg = merge(DestReg, top | bottom, dataSize); 865 } 866 else 867 DestReg = merge(DestReg, DestReg, dataSize); 868 ''' 869 flag_code = ''' 870 // If the shift amount is zero, no flags should be modified. 871 if (shiftAmt) { 872 int origCFBit = (ccFlagBits & CFBit) ? 1 : 0; 873 //Zero out any flags we might modify. This way we only have to 874 //worry about setting them. 875 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 876 int msb = bits(DestReg, dataSize * 8 - 1); 877 int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt); 878 //If some combination of the CF bits need to be set, set them. 879 if ((ext & (CFBit | ECFBit)) && 880 (realShiftAmt == 0) ? origCFBit : CFBits) 881 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 882 //Figure out what the OF bit should be. 883 if ((ext & OFBit) && (msb ^ CFBits)) 884 ccFlagBits = ccFlagBits | OFBit; 885 //Use the regular mechanisms to calculate the other flags. 886 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 887 DestReg, psrc1, op2); 888 } 889 ''' 890 891 class Sld(RegOp): 892 code = ''' 893 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 894 uint8_t dataBits = dataSize * 8; 895 uint8_t realShiftAmt = shiftAmt % (2 * dataBits); 896 uint64_t result; 897 if (realShiftAmt == 0) { 898 result = psrc1; 899 } else if (realShiftAmt < dataBits) { 900 result = (psrc1 << realShiftAmt) | 901 (DoubleBits >> (dataBits - realShiftAmt)); 902 } else { 903 result = (DoubleBits << (realShiftAmt - dataBits)) | 904 (psrc1 >> (2 * dataBits - realShiftAmt)); 905 } 906 DestReg = merge(DestReg, result, dataSize); 907 ''' 908 flag_code = ''' 909 // If the shift amount is zero, no flags should be modified. 910 if (shiftAmt) { 911 //Zero out any flags we might modify. This way we only have to 912 //worry about setting them. 913 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 914 int CFBits = 0; 915 //Figure out if we -would- set the CF bits if requested. 916 if ((realShiftAmt == 0 && 917 bits(DoubleBits, 0)) || 918 (realShiftAmt <= dataBits && 919 bits(SrcReg1, dataBits - realShiftAmt)) || 920 (realShiftAmt > dataBits && 921 bits(DoubleBits, 2 * dataBits - realShiftAmt))) { 922 CFBits = 1; 923 } 924 //If some combination of the CF bits need to be set, set them. 925 if ((ext & (CFBit | ECFBit)) && CFBits) 926 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 927 //Figure out what the OF bit should be. 928 if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ 929 bits(result, dataBits - 1))) 930 ccFlagBits = ccFlagBits | OFBit; 931 //Use the regular mechanisms to calculate the other flags. 932 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 933 DestReg, psrc1, op2); 934 } 935 ''' 936 937 class Srd(RegOp): 938 code = ''' 939 uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); 940 uint8_t dataBits = dataSize * 8; 941 uint8_t realShiftAmt = shiftAmt % (2 * dataBits); 942 uint64_t result; 943 if (realShiftAmt == 0) { 944 result = psrc1; 945 } else if (realShiftAmt < dataBits) { 946 // Because what happens to the bits shift -in- on a right 947 // shift is not defined in the C/C++ standard, we have to 948 // mask them out to be sure they're zero. 949 uint64_t logicalMask = mask(dataBits - realShiftAmt); 950 result = ((psrc1 >> realShiftAmt) & logicalMask) | 951 (DoubleBits << (dataBits - realShiftAmt)); 952 } else { 953 uint64_t logicalMask = mask(2 * dataBits - realShiftAmt); 954 result = ((DoubleBits >> (realShiftAmt - dataBits)) & 955 logicalMask) | 956 (psrc1 << (2 * dataBits - realShiftAmt)); 957 } 958 DestReg = merge(DestReg, result, dataSize); 959 ''' 960 flag_code = ''' 961 // If the shift amount is zero, no flags should be modified. 962 if (shiftAmt) { 963 //Zero out any flags we might modify. This way we only have to 964 //worry about setting them. 965 ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); 966 int CFBits = 0; 967 //If some combination of the CF bits need to be set, set them. 968 if ((realShiftAmt == 0 && 969 bits(DoubleBits, dataBits - 1)) || 970 (realShiftAmt <= dataBits && 971 bits(SrcReg1, realShiftAmt - 1)) || 972 (realShiftAmt > dataBits && 973 bits(DoubleBits, realShiftAmt - dataBits - 1))) { 974 CFBits = 1; 975 } 976 //If some combination of the CF bits need to be set, set them. 977 if ((ext & (CFBit | ECFBit)) && CFBits) 978 ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); 979 //Figure out what the OF bit should be. 980 if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ 981 bits(result, dataBits - 1))) 982 ccFlagBits = ccFlagBits | OFBit; 983 //Use the regular mechanisms to calculate the other flags. 984 ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), 985 DestReg, psrc1, op2); 986 } 987 ''' 988 989 class Mdb(WrRegOp): 990 code = 'DoubleBits = psrc1 ^ op2;' 991 992 class Wrip(WrRegOp, CondRegOp): 993 code = 'RIP = psrc1 + sop2 + CSBase' 994 else_code="RIP = RIP;" 995 996 class Wruflags(WrRegOp): 997 code = 'ccFlagBits = psrc1 ^ op2' 998 999 class Wrflags(WrRegOp): 1000 code = ''' 1001 MiscReg newFlags = psrc1 ^ op2; 1002 MiscReg userFlagMask = 0xDD5; 1003 // Get only the user flags 1004 ccFlagBits = newFlags & userFlagMask; 1005 // Get everything else 1006 nccFlagBits = newFlags & ~userFlagMask; 1007 ''' 1008 1009 class Rdip(RdRegOp): 1010 code = 'DestReg = RIP - CSBase' 1011 1012 class Ruflags(RdRegOp): 1013 code = 'DestReg = ccFlagBits' 1014 1015 class Rflags(RdRegOp): 1016 code = 'DestReg = ccFlagBits | nccFlagBits' 1017 1018 class Ruflag(RegOp): 1019 code = ''' 1020 int flag = bits(ccFlagBits, imm8); 1021 DestReg = merge(DestReg, flag, dataSize); 1022 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 1023 (ccFlagBits & ~EZFBit); 1024 ''' 1025 def __init__(self, dest, imm, flags=None, \ 1026 dataSize="env.dataSize"): 1027 super(Ruflag, self).__init__(dest, \ 1028 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 1029 1030 class Rflag(RegOp): 1031 code = ''' 1032 MiscReg flagMask = 0x3F7FDD5; 1033 MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask; 1034 int flag = bits(flags, imm8); 1035 DestReg = merge(DestReg, flag, dataSize); 1036 ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : 1037 (ccFlagBits & ~EZFBit); 1038 ''' 1039 def __init__(self, dest, imm, flags=None, \ 1040 dataSize="env.dataSize"): 1041 super(Rflag, self).__init__(dest, \ 1042 "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) 1043 1044 class Sext(RegOp): 1045 code = ''' 1046 IntReg val = psrc1; 1047 // Mask the bit position so that it wraps. 1048 int bitPos = op2 & (dataSize * 8 - 1); 1049 int sign_bit = bits(val, bitPos, bitPos); 1050 uint64_t maskVal = mask(bitPos+1); 1051 val = sign_bit ? (val | ~maskVal) : (val & maskVal); 1052 DestReg = merge(DestReg, val, dataSize); 1053 ''' 1054 flag_code = ''' 1055 if (!sign_bit) 1056 ccFlagBits = ccFlagBits & 1057 ~(ext & (CFBit | ECFBit | ZFBit | EZFBit)); 1058 else 1059 ccFlagBits = ccFlagBits | 1060 (ext & (CFBit | ECFBit | ZFBit | EZFBit)); 1061 ''' 1062 1063 class Zext(RegOp): 1064 code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);' 1065 1066 class Rddr(RegOp): 1067 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1068 super(Rddr, self).__init__(dest, \ 1069 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1070 code = ''' 1071 CR4 cr4 = CR4Op; 1072 DR7 dr7 = DR7Op; 1073 if ((cr4.de == 1 && (src1 == 4 || src1 == 5)) || src1 >= 8) { 1074 fault = new InvalidOpcode(); 1075 } else if (dr7.gd) { 1076 fault = new DebugException(); 1077 } else { 1078 DestReg = merge(DestReg, DebugSrc1, dataSize); 1079 } 1080 ''' 1081 1082 class Wrdr(RegOp): 1083 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1084 super(Wrdr, self).__init__(dest, \ 1085 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1086 code = ''' 1087 CR4 cr4 = CR4Op; 1088 DR7 dr7 = DR7Op; 1089 if ((cr4.de == 1 && (dest == 4 || dest == 5)) || dest >= 8) { 1090 fault = new InvalidOpcode(); 1091 } else if ((dest == 6 || dest == 7) && bits(psrc1, 63, 32) && 1092 machInst.mode.mode == LongMode) { 1093 fault = new GeneralProtection(0); 1094 } else if (dr7.gd) { 1095 fault = new DebugException(); 1096 } else { 1097 DebugDest = psrc1; 1098 } 1099 ''' 1100 1101 class Rdcr(RegOp): 1102 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1103 super(Rdcr, self).__init__(dest, \ 1104 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1105 code = ''' 1106 if (src1 == 1 || (src1 > 4 && src1 < 8) || (src1 > 8)) { 1107 fault = new InvalidOpcode(); 1108 } else { 1109 DestReg = merge(DestReg, ControlSrc1, dataSize); 1110 } 1111 ''' 1112 1113 class Wrcr(RegOp): 1114 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1115 super(Wrcr, self).__init__(dest, \ 1116 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1117 code = ''' 1118 if (dest == 1 || (dest > 4 && dest < 8) || (dest > 8)) { 1119 fault = new InvalidOpcode(); 1120 } else { 1121 // There are *s in the line below so it doesn't confuse the 1122 // parser. They may be unnecessary. 1123 //Mis*cReg old*Val = pick(Cont*rolDest, 0, dat*aSize); 1124 MiscReg newVal = psrc1; 1125 1126 // Check for any modifications that would cause a fault. 1127 switch(dest) { 1128 case 0: 1129 { 1130 Efer efer = EferOp; 1131 CR0 cr0 = newVal; 1132 CR4 oldCr4 = CR4Op; 1133 if (bits(newVal, 63, 32) || 1134 (!cr0.pe && cr0.pg) || 1135 (!cr0.cd && cr0.nw) || 1136 (cr0.pg && efer.lme && !oldCr4.pae)) 1137 fault = new GeneralProtection(0); 1138 } 1139 break; 1140 case 2: 1141 break; 1142 case 3: 1143 break; 1144 case 4: 1145 { 1146 CR4 cr4 = newVal; 1147 // PAE can't be disabled in long mode. 1148 if (bits(newVal, 63, 11) || 1149 (machInst.mode.mode == LongMode && !cr4.pae)) 1150 fault = new GeneralProtection(0); 1151 } 1152 break; 1153 case 8: 1154 { 1155 if (bits(newVal, 63, 4)) 1156 fault = new GeneralProtection(0); 1157 } 1158 default: 1159 panic("Unrecognized control register %d.\\n", dest); 1160 } 1161 ControlDest = newVal; 1162 } 1163 ''' 1164 1165 # Microops for manipulating segmentation registers 1166 class SegOp(CondRegOp): 1167 abstract = True 1168 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1169 super(SegOp, self).__init__(dest, \ 1170 src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1171 1172 class Wrbase(SegOp): 1173 code = ''' 1174 SegBaseDest = psrc1; 1175 ''' 1176 1177 class Wrlimit(SegOp): 1178 code = ''' 1179 SegLimitDest = psrc1; 1180 ''' 1181 1182 class Wrsel(SegOp): 1183 code = ''' 1184 SegSelDest = psrc1; 1185 ''' 1186 1187 class WrAttr(SegOp): 1188 code = ''' 1189 SegAttrDest = psrc1; 1190 ''' 1191 1192 class Rdbase(SegOp): 1193 code = ''' 1194 DestReg = merge(DestReg, SegBaseSrc1, dataSize); 1195 ''' 1196 1197 class Rdlimit(SegOp): 1198 code = ''' 1199 DestReg = merge(DestReg, SegLimitSrc1, dataSize); 1200 ''' 1201 1202 class RdAttr(SegOp): 1203 code = ''' 1204 DestReg = merge(DestReg, SegAttrSrc1, dataSize); 1205 ''' 1206 1207 class Rdsel(SegOp): 1208 code = ''' 1209 DestReg = merge(DestReg, SegSelSrc1, dataSize); 1210 ''' 1211 1212 class Rdval(RegOp): 1213 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1214 super(Rdval, self).__init__(dest, src1, \ 1215 "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1216 code = ''' 1217 DestReg = MiscRegSrc1; 1218 ''' 1219 1220 class Wrval(RegOp): 1221 def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): 1222 super(Wrval, self).__init__(dest, src1, \ 1223 "InstRegIndex(NUM_INTREGS)", flags, dataSize) 1224 code = ''' 1225 MiscRegDest = SrcReg1; 1226 ''' 1227 1228 class Chks(RegOp): 1229 def __init__(self, dest, src1, src2=0, 1230 flags=None, dataSize="env.dataSize"): 1231 super(Chks, self).__init__(dest, 1232 src1, src2, flags, dataSize) 1233 code = ''' 1234 // The selector is in source 1 and can be at most 16 bits. 1235 SegSelector selector = DestReg; 1236 SegDescriptor desc = SrcReg1; 1237 HandyM5Reg m5reg = M5Reg; 1238 1239 switch (imm8) 1240 { 1241 case SegNoCheck: 1242 break; 1243 case SegCSCheck: 1244 // Make sure it's the right type 1245 if (desc.s == 0 || desc.type.codeOrData != 1) { 1246 fault = new GeneralProtection(0); 1247 } else if (m5reg.cpl != desc.dpl) { 1248 fault = new GeneralProtection(0); 1249 } 1250 break; 1251 case SegCallGateCheck: 1252 panic("CS checks for far calls/jumps through call gates" 1253 "not implemented.\\n"); 1254 break; 1255 case SegSoftIntGateCheck: 1256 // Check permissions. 1257 if (desc.dpl < m5reg.cpl) { 1258 fault = new GeneralProtection(selector); 1259 break; 1260 } 1261 // Fall through on purpose 1262 case SegIntGateCheck: 1263 // Make sure the gate's the right type. 1264 if ((m5reg.mode == LongMode && (desc.type & 0xe) != 0xe) || 1265 ((desc.type & 0x6) != 0x6)) { 1266 fault = new GeneralProtection(0); 1267 } 1268 break; 1269 case SegSSCheck: 1270 if (selector.si || selector.ti) { 1271 if (!desc.p) { 1272 fault = new StackFault(selector); 1273 } 1274 } else { 1275 if ((m5reg.submode != SixtyFourBitMode || 1276 m5reg.cpl == 3) || 1277 !(desc.s == 1 && 1278 desc.type.codeOrData == 0 && desc.type.w) || 1279 (desc.dpl != m5reg.cpl) || 1280 (selector.rpl != m5reg.cpl)) { 1281 fault = new GeneralProtection(selector); 1282 } 1283 } 1284 break; 1285 case SegIretCheck: 1286 { 1287 if ((!selector.si && !selector.ti) || 1288 (selector.rpl < m5reg.cpl) || 1289 !(desc.s == 1 && desc.type.codeOrData == 1) || 1290 (!desc.type.c && desc.dpl != selector.rpl) || 1291 (desc.type.c && desc.dpl > selector.rpl)) { 1292 fault = new GeneralProtection(selector); 1293 } else if (!desc.p) { 1294 fault = new SegmentNotPresent(selector); 1295 } 1296 break; 1297 } 1298 case SegIntCSCheck: 1299 if (m5reg.mode == LongMode) { 1300 if (desc.l != 1 || desc.d != 0) { 1301 fault = new GeneralProtection(selector); 1302 } 1303 } else { 1304 panic("Interrupt CS checks not implemented " 1305 "in legacy mode.\\n"); 1306 } 1307 break; 1308 case SegTRCheck: 1309 if (!selector.si || selector.ti) { 1310 fault = new GeneralProtection(selector); 1311 } 1312 break; 1313 case SegTSSCheck: 1314 if (!desc.p) { 1315 fault = new SegmentNotPresent(selector); 1316 } else if (!(desc.type == 0x9 || 1317 (desc.type == 1 && 1318 m5reg.mode != LongMode))) { 1319 fault = new GeneralProtection(selector); 1320 } 1321 break; 1322 case SegInGDTCheck: 1323 if (selector.ti) { 1324 fault = new GeneralProtection(selector); 1325 } 1326 break; 1327 case SegLDTCheck: 1328 if (!desc.p) { 1329 fault = new SegmentNotPresent(selector); 1330 } else if (desc.type != 0x2) { 1331 fault = new GeneralProtection(selector); 1332 } 1333 break; 1334 default: 1335 panic("Undefined segment check type.\\n"); 1336 } 1337 ''' 1338 flag_code = ''' 1339 // Check for a NULL selector and set ZF,EZF appropriately. 1340 ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit)); 1341 if (!selector.si && !selector.ti) 1342 ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit)); 1343 ''' 1344 1345 class Wrdh(RegOp): 1346 code = ''' 1347 SegDescriptor desc = SrcReg1; 1348 1349 uint64_t target = bits(SrcReg2, 31, 0) << 32; 1350 switch(desc.type) { 1351 case LDT64: 1352 case AvailableTSS64: 1353 case BusyTSS64: 1354 replaceBits(target, 23, 0, desc.baseLow); 1355 replaceBits(target, 31, 24, desc.baseHigh); 1356 break; 1357 case CallGate64: 1358 case IntGate64: 1359 case TrapGate64: 1360 replaceBits(target, 15, 0, bits(desc, 15, 0)); 1361 replaceBits(target, 31, 16, bits(desc, 63, 48)); 1362 break; 1363 default: 1364 panic("Wrdh used with wrong descriptor type!\\n"); 1365 } 1366 DestReg = target; 1367 ''' 1368 1369 class Wrtsc(WrRegOp): 1370 code = ''' 1371 TscOp = psrc1; 1372 ''' 1373 1374 class Rdtsc(RdRegOp): 1375 code = ''' 1376 DestReg = TscOp; 1377 ''' 1378 1379 class Rdm5reg(RdRegOp): 1380 code = ''' 1381 DestReg = M5Reg; 1382 ''' 1383 1384 class Wrdl(RegOp): 1385 code = ''' 1386 SegDescriptor desc = SrcReg1; 1387 SegSelector selector = SrcReg2; 1388 if (selector.si || selector.ti) { 1389 if (!desc.p) 1390 panic("Segment not present.\\n"); 1391 SegAttr attr = 0; 1392 attr.dpl = desc.dpl; 1393 attr.unusable = 0; 1394 attr.defaultSize = desc.d; 1395 attr.longMode = desc.l; 1396 attr.avl = desc.avl; 1397 attr.granularity = desc.g; 1398 attr.present = desc.p; 1399 attr.system = desc.s; 1400 attr.type = desc.type; 1401 if (!desc.s) { 1402 // The expand down bit happens to be set for gates. 1403 if (desc.type.e) { 1404 panic("Gate descriptor encountered.\\n"); 1405 } 1406 attr.readable = 1; 1407 attr.writable = 1; 1408 attr.expandDown = 0; 1409 } else { 1410 if (desc.type.codeOrData) { 1411 attr.expandDown = 0; 1412 attr.readable = desc.type.r; 1413 attr.writable = 0; 1414 } else { 1415 attr.expandDown = desc.type.e; 1416 attr.readable = 1; 1417 attr.writable = desc.type.w; 1418 } 1419 } 1420 Addr base = desc.baseLow | (desc.baseHigh << 24); 1421 Addr limit = desc.limitLow | (desc.limitHigh << 16); 1422 if (desc.g) 1423 limit = (limit << 12) | mask(12); 1424 SegBaseDest = base; 1425 SegLimitDest = limit; 1426 SegAttrDest = attr; 1427 } else { 1428 SegBaseDest = SegBaseDest; 1429 SegLimitDest = SegLimitDest; 1430 SegAttrDest = SegAttrDest; 1431 } 1432 ''' 1433}}; 1434