regop.isa revision 4519:f8da6b45573f
19651SAndreas.Sandberg@ARM.com// Copyright (c) 2007 The Hewlett-Packard Development Company 29651SAndreas.Sandberg@ARM.com// All rights reserved. 39651SAndreas.Sandberg@ARM.com// 49651SAndreas.Sandberg@ARM.com// Redistribution and use of this software in source and binary forms, 59651SAndreas.Sandberg@ARM.com// with or without modification, are permitted provided that the 69651SAndreas.Sandberg@ARM.com// following conditions are met: 79651SAndreas.Sandberg@ARM.com// 89651SAndreas.Sandberg@ARM.com// The software must be used only for Non-Commercial Use which means any 99651SAndreas.Sandberg@ARM.com// use which is NOT directed to receiving any direct monetary 109651SAndreas.Sandberg@ARM.com// compensation for, or commercial advantage from such use. Illustrative 119651SAndreas.Sandberg@ARM.com// examples of non-commercial use are academic research, personal study, 129651SAndreas.Sandberg@ARM.com// teaching, education and corporate research & development. 139651SAndreas.Sandberg@ARM.com// Illustrative examples of commercial use are distributing products for 149651SAndreas.Sandberg@ARM.com// commercial advantage and providing services using the software for 159651SAndreas.Sandberg@ARM.com// commercial advantage. 169651SAndreas.Sandberg@ARM.com// 179651SAndreas.Sandberg@ARM.com// If you wish to use this software or functionality therein that may be 189651SAndreas.Sandberg@ARM.com// covered by patents for commercial use, please contact: 199651SAndreas.Sandberg@ARM.com// Director of Intellectual Property Licensing 209651SAndreas.Sandberg@ARM.com// Office of Strategy and Technology 219651SAndreas.Sandberg@ARM.com// Hewlett-Packard Company 229651SAndreas.Sandberg@ARM.com// 1501 Page Mill Road 239651SAndreas.Sandberg@ARM.com// Palo Alto, California 94304 249651SAndreas.Sandberg@ARM.com// 259651SAndreas.Sandberg@ARM.com// Redistributions of source code must retain the above copyright notice, 269651SAndreas.Sandberg@ARM.com// this list of conditions and the following disclaimer. Redistributions 279651SAndreas.Sandberg@ARM.com// in binary form must reproduce the above copyright notice, this list of 289651SAndreas.Sandberg@ARM.com// conditions and the following disclaimer in the documentation and/or 299651SAndreas.Sandberg@ARM.com// other materials provided with the distribution. Neither the name of 309651SAndreas.Sandberg@ARM.com// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 319651SAndreas.Sandberg@ARM.com// contributors may be used to endorse or promote products derived from 329651SAndreas.Sandberg@ARM.com// this software without specific prior written permission. No right of 339651SAndreas.Sandberg@ARM.com// sublicense is granted herewith. Derivatives of the software and 349651SAndreas.Sandberg@ARM.com// output created using the software may be prepared, but only for 359651SAndreas.Sandberg@ARM.com// Non-Commercial Uses. Derivatives of the software may be shared with 369651SAndreas.Sandberg@ARM.com// others provided: (i) the others agree to abide by the list of 379651SAndreas.Sandberg@ARM.com// conditions herein which includes the Non-Commercial Use restrictions; 389651SAndreas.Sandberg@ARM.com// and (ii) such Derivatives of the software include the above copyright 399651SAndreas.Sandberg@ARM.com// notice to acknowledge the contribution from this software where 4011793Sbrandon.potter@amd.com// applicable, this list of conditions and the disclaimer below. 419651SAndreas.Sandberg@ARM.com// 429651SAndreas.Sandberg@ARM.com// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 439651SAndreas.Sandberg@ARM.com// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 449651SAndreas.Sandberg@ARM.com// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 459651SAndreas.Sandberg@ARM.com// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 469651SAndreas.Sandberg@ARM.com// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 479651SAndreas.Sandberg@ARM.com// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 489651SAndreas.Sandberg@ARM.com// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 499651SAndreas.Sandberg@ARM.com// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 509651SAndreas.Sandberg@ARM.com// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 519651SAndreas.Sandberg@ARM.com// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 529651SAndreas.Sandberg@ARM.com// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 5312334Sgabeblack@google.com// 549651SAndreas.Sandberg@ARM.com// Authors: Gabe Black 559651SAndreas.Sandberg@ARM.com 569651SAndreas.Sandberg@ARM.com////////////////////////////////////////////////////////////////////////// 579651SAndreas.Sandberg@ARM.com// 589651SAndreas.Sandberg@ARM.com// RegOp Microop templates 599651SAndreas.Sandberg@ARM.com// 609651SAndreas.Sandberg@ARM.com////////////////////////////////////////////////////////////////////////// 619651SAndreas.Sandberg@ARM.com 629651SAndreas.Sandberg@ARM.comdef template MicroRegOpExecute {{ 639651SAndreas.Sandberg@ARM.com Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 649651SAndreas.Sandberg@ARM.com Trace::InstRecord *traceData) const 659651SAndreas.Sandberg@ARM.com { 669651SAndreas.Sandberg@ARM.com Fault fault = NoFault; 679651SAndreas.Sandberg@ARM.com 689651SAndreas.Sandberg@ARM.com %(op_decl)s; 699651SAndreas.Sandberg@ARM.com %(op_rd)s; 709651SAndreas.Sandberg@ARM.com %(code)s; 719651SAndreas.Sandberg@ARM.com 729651SAndreas.Sandberg@ARM.com //Write the resulting state to the execution context 739651SAndreas.Sandberg@ARM.com if(fault == NoFault) 749651SAndreas.Sandberg@ARM.com { 759651SAndreas.Sandberg@ARM.com %(op_wb)s; 769651SAndreas.Sandberg@ARM.com } 779651SAndreas.Sandberg@ARM.com return fault; 789651SAndreas.Sandberg@ARM.com } 799651SAndreas.Sandberg@ARM.com}}; 809651SAndreas.Sandberg@ARM.com 819651SAndreas.Sandberg@ARM.comdef template MicroRegOpImmExecute {{ 829651SAndreas.Sandberg@ARM.com Fault %(class_name)sImm::execute(%(CPU_exec_context)s *xc, 839651SAndreas.Sandberg@ARM.com Trace::InstRecord *traceData) const 849651SAndreas.Sandberg@ARM.com { 859651SAndreas.Sandberg@ARM.com Fault fault = NoFault; 869651SAndreas.Sandberg@ARM.com 879651SAndreas.Sandberg@ARM.com %(op_decl)s; 889651SAndreas.Sandberg@ARM.com %(op_rd)s; 899651SAndreas.Sandberg@ARM.com %(code)s; 909651SAndreas.Sandberg@ARM.com 919651SAndreas.Sandberg@ARM.com //Write the resulting state to the execution context 929651SAndreas.Sandberg@ARM.com if(fault == NoFault) 939651SAndreas.Sandberg@ARM.com { 949651SAndreas.Sandberg@ARM.com %(op_wb)s; 959651SAndreas.Sandberg@ARM.com } 969651SAndreas.Sandberg@ARM.com return fault; 979651SAndreas.Sandberg@ARM.com } 989651SAndreas.Sandberg@ARM.com}}; 999651SAndreas.Sandberg@ARM.com 1009651SAndreas.Sandberg@ARM.comdef template MicroRegOpDeclare {{ 1019651SAndreas.Sandberg@ARM.com class %(class_name)s : public %(base_class)s 1029651SAndreas.Sandberg@ARM.com { 1039651SAndreas.Sandberg@ARM.com protected: 1049651SAndreas.Sandberg@ARM.com const RegIndex src1; 1059651SAndreas.Sandberg@ARM.com const RegIndex src2; 1069651SAndreas.Sandberg@ARM.com const RegIndex dest; 1079651SAndreas.Sandberg@ARM.com const bool setStatus; 1089651SAndreas.Sandberg@ARM.com const uint8_t dataSize; 1099651SAndreas.Sandberg@ARM.com const uint8_t ext; 1109651SAndreas.Sandberg@ARM.com void buildMe(); 1119651SAndreas.Sandberg@ARM.com 1129651SAndreas.Sandberg@ARM.com public: 1139651SAndreas.Sandberg@ARM.com %(class_name)s(ExtMachInst _machInst, 1149651SAndreas.Sandberg@ARM.com const char * instMnem, 1159651SAndreas.Sandberg@ARM.com bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1169651SAndreas.Sandberg@ARM.com RegIndex _src1, RegIndex _src2, RegIndex _dest, 1179651SAndreas.Sandberg@ARM.com bool _setStatus, uint8_t _dataSize, uint8_t _ext); 1189651SAndreas.Sandberg@ARM.com 1199651SAndreas.Sandberg@ARM.com %(class_name)s(ExtMachInst _machInst, 1209651SAndreas.Sandberg@ARM.com const char * instMnem, 1219651SAndreas.Sandberg@ARM.com RegIndex _src1, RegIndex _src2, RegIndex _dest, 1229651SAndreas.Sandberg@ARM.com bool _setStatus, uint8_t _dataSize, uint8_t _ext); 1239651SAndreas.Sandberg@ARM.com 1249651SAndreas.Sandberg@ARM.com %(BasicExecDeclare)s 1259651SAndreas.Sandberg@ARM.com }; 1269651SAndreas.Sandberg@ARM.com}}; 1279651SAndreas.Sandberg@ARM.com 1289651SAndreas.Sandberg@ARM.comdef template MicroRegOpImmDeclare {{ 1299651SAndreas.Sandberg@ARM.com 1309651SAndreas.Sandberg@ARM.com class %(class_name)sImm : public %(base_class)s 1319651SAndreas.Sandberg@ARM.com { 1329651SAndreas.Sandberg@ARM.com protected: 1339651SAndreas.Sandberg@ARM.com const RegIndex src1; 1349651SAndreas.Sandberg@ARM.com const uint8_t imm8; 1359651SAndreas.Sandberg@ARM.com const RegIndex dest; 1369651SAndreas.Sandberg@ARM.com const bool setStatus; 1379651SAndreas.Sandberg@ARM.com const uint8_t dataSize; 1389651SAndreas.Sandberg@ARM.com const uint8_t ext; 1399651SAndreas.Sandberg@ARM.com void buildMe(); 1409651SAndreas.Sandberg@ARM.com 1419651SAndreas.Sandberg@ARM.com public: 1429651SAndreas.Sandberg@ARM.com %(class_name)sImm(ExtMachInst _machInst, 1439651SAndreas.Sandberg@ARM.com const char * instMnem, 1449651SAndreas.Sandberg@ARM.com bool isMicro, bool isDelayed, bool isFirst, bool isLast, 1459651SAndreas.Sandberg@ARM.com RegIndex _src1, uint8_t _imm8, RegIndex _dest, 1469651SAndreas.Sandberg@ARM.com bool _setStatus, uint8_t _dataSize, uint8_t _ext); 1479651SAndreas.Sandberg@ARM.com 1489651SAndreas.Sandberg@ARM.com %(class_name)sImm(ExtMachInst _machInst, 1499651SAndreas.Sandberg@ARM.com const char * instMnem, 1509651SAndreas.Sandberg@ARM.com RegIndex _src1, uint8_t _imm8, RegIndex _dest, 1519651SAndreas.Sandberg@ARM.com bool _setStatus, uint8_t _dataSize, uint8_t _ext); 1529651SAndreas.Sandberg@ARM.com 1539651SAndreas.Sandberg@ARM.com %(BasicExecDeclare)s 1549651SAndreas.Sandberg@ARM.com }; 1559651SAndreas.Sandberg@ARM.com}}; 1569651SAndreas.Sandberg@ARM.com 1579651SAndreas.Sandberg@ARM.comdef template MicroRegOpConstructor {{ 1589651SAndreas.Sandberg@ARM.com 1599651SAndreas.Sandberg@ARM.com inline void %(class_name)s::buildMe() 1609651SAndreas.Sandberg@ARM.com { 1619651SAndreas.Sandberg@ARM.com %(constructor)s; 1629651SAndreas.Sandberg@ARM.com } 1639651SAndreas.Sandberg@ARM.com 1649651SAndreas.Sandberg@ARM.com inline %(class_name)s::%(class_name)s( 1659651SAndreas.Sandberg@ARM.com ExtMachInst machInst, const char * instMnem, 1669651SAndreas.Sandberg@ARM.com RegIndex _src1, RegIndex _src2, RegIndex _dest, 1679651SAndreas.Sandberg@ARM.com bool _setStatus, uint8_t _dataSize, uint8_t _ext) : 1689651SAndreas.Sandberg@ARM.com %(base_class)s(machInst, "%(mnemonic)s", instMnem, 1699651SAndreas.Sandberg@ARM.com false, false, false, false, %(op_class)s), 1709651SAndreas.Sandberg@ARM.com src1(_src1), src2(_src2), dest(_dest), 1719651SAndreas.Sandberg@ARM.com setStatus(_setStatus), dataSize(_dataSize), ext(_ext) 17213787Sgambordr@oregonstate.edu { 17313787Sgambordr@oregonstate.edu buildMe(); 17413787Sgambordr@oregonstate.edu } 17513787Sgambordr@oregonstate.edu 17613787Sgambordr@oregonstate.edu inline %(class_name)s::%(class_name)s( 17713787Sgambordr@oregonstate.edu ExtMachInst machInst, const char * instMnem, 17813787Sgambordr@oregonstate.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 17913787Sgambordr@oregonstate.edu RegIndex _src1, RegIndex _src2, RegIndex _dest, 18013787Sgambordr@oregonstate.edu bool _setStatus, uint8_t _dataSize, uint8_t _ext) : 18113787Sgambordr@oregonstate.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 18213787Sgambordr@oregonstate.edu isMicro, isDelayed, isFirst, isLast, %(op_class)s), 18313787Sgambordr@oregonstate.edu src1(_src1), src2(_src2), dest(_dest), 1849651SAndreas.Sandberg@ARM.com setStatus(_setStatus), dataSize(_dataSize), ext(_ext) 1859651SAndreas.Sandberg@ARM.com { 1869651SAndreas.Sandberg@ARM.com buildMe(); 1879651SAndreas.Sandberg@ARM.com } 1889651SAndreas.Sandberg@ARM.com}}; 1899651SAndreas.Sandberg@ARM.com 1909651SAndreas.Sandberg@ARM.comdef template MicroRegOpImmConstructor {{ 1919651SAndreas.Sandberg@ARM.com 1929651SAndreas.Sandberg@ARM.com inline void %(class_name)sImm::buildMe() 1939651SAndreas.Sandberg@ARM.com { 1949651SAndreas.Sandberg@ARM.com %(constructor)s; 1959651SAndreas.Sandberg@ARM.com } 1969651SAndreas.Sandberg@ARM.com 1979651SAndreas.Sandberg@ARM.com inline %(class_name)sImm::%(class_name)sImm( 1989651SAndreas.Sandberg@ARM.com ExtMachInst machInst, const char * instMnem, 1999651SAndreas.Sandberg@ARM.com RegIndex _src1, uint8_t _imm8, RegIndex _dest, 2009651SAndreas.Sandberg@ARM.com bool _setStatus, uint8_t _dataSize, uint8_t _ext) : 2019651SAndreas.Sandberg@ARM.com %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2029651SAndreas.Sandberg@ARM.com false, false, false, false, %(op_class)s), 2039651SAndreas.Sandberg@ARM.com src1(_src1), imm8(_imm8), dest(_dest), 2049651SAndreas.Sandberg@ARM.com setStatus(_setStatus), dataSize(_dataSize), ext(_ext) 2059651SAndreas.Sandberg@ARM.com { 2069651SAndreas.Sandberg@ARM.com buildMe(); 2079651SAndreas.Sandberg@ARM.com } 2089651SAndreas.Sandberg@ARM.com 2099651SAndreas.Sandberg@ARM.com inline %(class_name)sImm::%(class_name)sImm( 2109651SAndreas.Sandberg@ARM.com ExtMachInst machInst, const char * instMnem, 2119651SAndreas.Sandberg@ARM.com bool isMicro, bool isDelayed, bool isFirst, bool isLast, 2129651SAndreas.Sandberg@ARM.com RegIndex _src1, uint8_t _imm8, RegIndex _dest, 2139651SAndreas.Sandberg@ARM.com bool _setStatus, uint8_t _dataSize, uint8_t _ext) : 2149651SAndreas.Sandberg@ARM.com %(base_class)s(machInst, "%(mnemonic)s", instMnem, 2159651SAndreas.Sandberg@ARM.com isMicro, isDelayed, isFirst, isLast, %(op_class)s), 2169651SAndreas.Sandberg@ARM.com src1(_src1), imm8(_imm8), dest(_dest), 2179651SAndreas.Sandberg@ARM.com setStatus(_setStatus), dataSize(_dataSize), ext(_ext) 2189651SAndreas.Sandberg@ARM.com { 2199651SAndreas.Sandberg@ARM.com buildMe(); 2209651SAndreas.Sandberg@ARM.com } 2219651SAndreas.Sandberg@ARM.com}}; 2229651SAndreas.Sandberg@ARM.com 2239651SAndreas.Sandberg@ARM.comlet {{ 2249651SAndreas.Sandberg@ARM.com class RegOp(object): 2259651SAndreas.Sandberg@ARM.com def __init__(self, dest, src1, src2): 2269651SAndreas.Sandberg@ARM.com self.dest = dest 2279651SAndreas.Sandberg@ARM.com self.src1 = src1 2289651SAndreas.Sandberg@ARM.com self.src2 = src2 2299651SAndreas.Sandberg@ARM.com self.setStatus = False 2309651SAndreas.Sandberg@ARM.com self.dataSize = 1 2319651SAndreas.Sandberg@ARM.com self.ext = 0 2329651SAndreas.Sandberg@ARM.com 2339651SAndreas.Sandberg@ARM.com def getAllocator(self, *microFlags): 2349651SAndreas.Sandberg@ARM.com allocator = '''new %(class_name)s(machInst, %(mnemonic)s, 2359651SAndreas.Sandberg@ARM.com %(flags)s %(src1)s, %(src2)s, %(dest)s, 2369651SAndreas.Sandberg@ARM.com %(setStatus)s, %(dataSize)s, %(ext)s)''' % { 2379651SAndreas.Sandberg@ARM.com "class_name" : self.className, 2389651SAndreas.Sandberg@ARM.com "mnemonic" : self.mnemonic, 2399651SAndreas.Sandberg@ARM.com "flags" : self.microFlagsText(microFlags), 2409651SAndreas.Sandberg@ARM.com "src1" : self.src1, "src2" : self.src2, 2419651SAndreas.Sandberg@ARM.com "dest" : self.dest, 2429651SAndreas.Sandberg@ARM.com "setStatus" : self.setStatus, 2439651SAndreas.Sandberg@ARM.com "dataSize" : self.dataSize, 2449651SAndreas.Sandberg@ARM.com "ext" : self.ext} 2459651SAndreas.Sandberg@ARM.com 2469651SAndreas.Sandberg@ARM.com class RegOpImm(object): 2479651SAndreas.Sandberg@ARM.com def __init__(self, dest, src1, imm): 2489651SAndreas.Sandberg@ARM.com self.dest = dest 2499651SAndreas.Sandberg@ARM.com self.src1 = src1 2509651SAndreas.Sandberg@ARM.com self.imm = imm 2519651SAndreas.Sandberg@ARM.com self.setStatus = False 2529651SAndreas.Sandberg@ARM.com self.dataSize = 1 2539651SAndreas.Sandberg@ARM.com self.ext = 0 2549651SAndreas.Sandberg@ARM.com 2559651SAndreas.Sandberg@ARM.com def getAllocator(self, *microFlags): 25611321Ssteve.reinhardt@amd.com allocator = '''new %(class_name)s(machInst, %(mnemonic)s, 2579651SAndreas.Sandberg@ARM.com %(flags)s %(src1)s, %(imm8)s, %(dest)s, 258 %(setStatus)s, %(dataSize)s, %(ext)s)''' % { 259 "class_name" : self.className, 260 "mnemonic" : self.mnemonic, 261 "flags" : self.microFlagsText(microFlags), 262 "src1" : self.src1, "imm8" : self.imm8, 263 "dest" : self.dest, 264 "setStatus" : self.setStatus, 265 "dataSize" : self.dataSize, 266 "ext" : self.ext} 267}}; 268 269let {{ 270 271 # Make these empty strings so that concatenating onto 272 # them will always work. 273 header_output = "" 274 decoder_output = "" 275 exec_output = "" 276 277 def defineMicroIntOp(mnemonic, code): 278 global header_output 279 global decoder_output 280 global exec_output 281 Name = mnemonic 282 name = mnemonic.lower() 283 284 # Find op2 in each of the instruction definitions. Create two versions 285 # of the code, one with an integer operand, and one with an immediate 286 # operand. 287 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 288 regCode = matcher.sub("SrcReg2", code) 289 immCode = matcher.sub("imm8", code) 290 291 # Build up the all register version of this micro op 292 iop = InstObjParams(name, Name, 'X86MicroOpBase', {"code" : regCode}) 293 header_output += MicroRegOpDeclare.subst(iop) 294 decoder_output += MicroRegOpConstructor.subst(iop) 295 exec_output += MicroRegOpExecute.subst(iop) 296 297 class RegOpChild(RegOp): 298 def __init__(self, dest, src1, src2): 299 super(RegOpChild, self).__init__(self, dest, src1, src2) 300 self.mnemonic = name 301 302 microopClasses[name] = RegOpChild 303 304 # Build up the immediate version of this micro op 305 iop = InstObjParams(name + "i", Name, 306 'X86MicroOpBase', {"code" : immCode}) 307 header_output += MicroRegOpImmDeclare.subst(iop) 308 decoder_output += MicroRegOpImmConstructor.subst(iop) 309 exec_output += MicroRegOpImmExecute.subst(iop) 310 311 class RegOpImmChild(RegOpImm): 312 def __init__(self, dest, src1, imm): 313 super(RegOpImmChild, self).__init__(self, dest, src1, imm) 314 self.mnemonic = name + "i" 315 316 microopClasses[name + "i"] = RegOpChild 317 318 defineMicroIntOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to set OF,CF,SF 319 defineMicroIntOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)') 320 defineMicroIntOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to add in CF, set OF,CF,SF 321 defineMicroIntOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to subtract CF, set OF,CF,SF 322 defineMicroIntOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)') 323 defineMicroIntOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to set OF,CF,SF 324 defineMicroIntOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)') 325 defineMicroIntOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)') #Needs to set OF,CF,SF and not DestReg 326 defineMicroIntOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)') 327 328}}; 329