mediaop.isa revision 7081:ff2321547ca3
111723Sar4jc@virginia.edu/// Copyright (c) 2009 The Regents of The University of Michigan 211723Sar4jc@virginia.edu// All rights reserved. 311723Sar4jc@virginia.edu// 411723Sar4jc@virginia.edu// Redistribution and use in source and binary forms, with or without 511723Sar4jc@virginia.edu// modification, are permitted provided that the following conditions are 611723Sar4jc@virginia.edu// met: redistributions of source code must retain the above copyright 711723Sar4jc@virginia.edu// notice, this list of conditions and the following disclaimer; 811723Sar4jc@virginia.edu// redistributions in binary form must reproduce the above copyright 911723Sar4jc@virginia.edu// notice, this list of conditions and the following disclaimer in the 1011723Sar4jc@virginia.edu// documentation and/or other materials provided with the distribution; 1111723Sar4jc@virginia.edu// neither the name of the copyright holders nor the names of its 1211723Sar4jc@virginia.edu// contributors may be used to endorse or promote products derived from 1311723Sar4jc@virginia.edu// this software without specific prior written permission. 1411723Sar4jc@virginia.edu// 1511723Sar4jc@virginia.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1611723Sar4jc@virginia.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1711723Sar4jc@virginia.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1811723Sar4jc@virginia.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 1911723Sar4jc@virginia.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2011723Sar4jc@virginia.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2111723Sar4jc@virginia.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2211723Sar4jc@virginia.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2311723Sar4jc@virginia.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2411723Sar4jc@virginia.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2511723Sar4jc@virginia.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2611723Sar4jc@virginia.edu// 2711723Sar4jc@virginia.edu// Authors: Gabe Black 2811723Sar4jc@virginia.edu 2911723Sar4jc@virginia.edudef template MediaOpExecute {{ 3011723Sar4jc@virginia.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 3111723Sar4jc@virginia.edu Trace::InstRecord *traceData) const 3211723Sar4jc@virginia.edu { 3311723Sar4jc@virginia.edu Fault fault = NoFault; 3411723Sar4jc@virginia.edu 3511963Sar4jc@virginia.edu %(op_decl)s; 3611723Sar4jc@virginia.edu %(op_rd)s; 3711723Sar4jc@virginia.edu 3811723Sar4jc@virginia.edu %(code)s; 3911723Sar4jc@virginia.edu 4011723Sar4jc@virginia.edu //Write the resulting state to the execution context 4111723Sar4jc@virginia.edu if(fault == NoFault) 4211723Sar4jc@virginia.edu { 4311723Sar4jc@virginia.edu %(op_wb)s; 4411723Sar4jc@virginia.edu } 4511723Sar4jc@virginia.edu return fault; 4611723Sar4jc@virginia.edu } 4711723Sar4jc@virginia.edu}}; 4811723Sar4jc@virginia.edu 4911723Sar4jc@virginia.edudef template MediaOpRegDeclare {{ 5011723Sar4jc@virginia.edu class %(class_name)s : public %(base_class)s 5111723Sar4jc@virginia.edu { 5211723Sar4jc@virginia.edu protected: 5311723Sar4jc@virginia.edu void buildMe(); 5411723Sar4jc@virginia.edu 5511723Sar4jc@virginia.edu public: 5611723Sar4jc@virginia.edu %(class_name)s(ExtMachInst _machInst, 5711723Sar4jc@virginia.edu const char * instMnem, 5811723Sar4jc@virginia.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 5911723Sar4jc@virginia.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 6011723Sar4jc@virginia.edu uint8_t _srcSize, uint8_t _destSize, uint16_t _ext); 6111723Sar4jc@virginia.edu 6211723Sar4jc@virginia.edu %(class_name)s(ExtMachInst _machInst, 6311963Sar4jc@virginia.edu const char * instMnem, 6412695Sar4jc@virginia.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 6512695Sar4jc@virginia.edu uint8_t _srcSize, uint8_t _destSize, uint16_t _ext); 6612695Sar4jc@virginia.edu 6712695Sar4jc@virginia.edu %(BasicExecDeclare)s 6812695Sar4jc@virginia.edu }; 6912695Sar4jc@virginia.edu}}; 7012695Sar4jc@virginia.edu 7112695Sar4jc@virginia.edudef template MediaOpImmDeclare {{ 7212695Sar4jc@virginia.edu 7311723Sar4jc@virginia.edu class %(class_name)s : public %(base_class)s 7411723Sar4jc@virginia.edu { 7512695Sar4jc@virginia.edu protected: 7612695Sar4jc@virginia.edu void buildMe(); 7712695Sar4jc@virginia.edu 7812695Sar4jc@virginia.edu public: 7912695Sar4jc@virginia.edu %(class_name)s(ExtMachInst _machInst, 8012695Sar4jc@virginia.edu const char * instMnem, 8112695Sar4jc@virginia.edu bool isMicro, bool isDelayed, bool isFirst, bool isLast, 8212695Sar4jc@virginia.edu InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, 8312695Sar4jc@virginia.edu uint8_t _srcSize, uint8_t _destSize, uint16_t _ext); 8412695Sar4jc@virginia.edu 8512695Sar4jc@virginia.edu %(class_name)s(ExtMachInst _machInst, 8612695Sar4jc@virginia.edu const char * instMnem, 8712695Sar4jc@virginia.edu InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, 8812695Sar4jc@virginia.edu uint8_t _srcSize, uint8_t _destSize, uint16_t _ext); 8912695Sar4jc@virginia.edu 9012695Sar4jc@virginia.edu %(BasicExecDeclare)s 9112695Sar4jc@virginia.edu }; 9212695Sar4jc@virginia.edu}}; 9312695Sar4jc@virginia.edu 9412695Sar4jc@virginia.edudef template MediaOpRegConstructor {{ 9512695Sar4jc@virginia.edu 9612695Sar4jc@virginia.edu inline void %(class_name)s::buildMe() 9711723Sar4jc@virginia.edu { 9813612Sgabeblack@google.com %(constructor)s; 9911723Sar4jc@virginia.edu } 10011723Sar4jc@virginia.edu 10112695Sar4jc@virginia.edu inline %(class_name)s::%(class_name)s( 10212695Sar4jc@virginia.edu ExtMachInst machInst, const char * instMnem, 10312695Sar4jc@virginia.edu InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 10412695Sar4jc@virginia.edu uint8_t _srcSize, uint8_t _destSize, uint16_t _ext) : 10511723Sar4jc@virginia.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 10612695Sar4jc@virginia.edu false, false, false, false, 10712695Sar4jc@virginia.edu _src1, _src2, _dest, _srcSize, _destSize, _ext, 10812695Sar4jc@virginia.edu %(op_class)s) 10911723Sar4jc@virginia.edu { 11011723Sar4jc@virginia.edu buildMe(); 11113612Sgabeblack@google.com } 11211723Sar4jc@virginia.edu 11311723Sar4jc@virginia.edu inline %(class_name)s::%(class_name)s( 11411723Sar4jc@virginia.edu ExtMachInst machInst, const char * instMnem, 11513935Salec.roelke@gmail.com bool isMicro, bool isDelayed, bool isFirst, bool isLast, 11613935Salec.roelke@gmail.com InstRegIndex _src1, InstRegIndex _src2, InstRegIndex _dest, 11712695Sar4jc@virginia.edu uint8_t _srcSize, uint8_t _destSize, uint16_t _ext) : 11812695Sar4jc@virginia.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 11912695Sar4jc@virginia.edu isMicro, isDelayed, isFirst, isLast, 12012695Sar4jc@virginia.edu _src1, _src2, _dest, _srcSize, _destSize, _ext, 12112695Sar4jc@virginia.edu %(op_class)s) 12212695Sar4jc@virginia.edu { 12312695Sar4jc@virginia.edu buildMe(); 12412695Sar4jc@virginia.edu } 12512695Sar4jc@virginia.edu}}; 12612695Sar4jc@virginia.edu 12712695Sar4jc@virginia.edudef template MediaOpImmConstructor {{ 12812695Sar4jc@virginia.edu 12912695Sar4jc@virginia.edu inline void %(class_name)s::buildMe() 13012695Sar4jc@virginia.edu { 13112695Sar4jc@virginia.edu %(constructor)s; 13212695Sar4jc@virginia.edu } 13312695Sar4jc@virginia.edu 13412695Sar4jc@virginia.edu inline %(class_name)s::%(class_name)s( 13511723Sar4jc@virginia.edu ExtMachInst machInst, const char * instMnem, 13612695Sar4jc@virginia.edu InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, 13712695Sar4jc@virginia.edu uint8_t _srcSize, uint8_t _destSize, uint16_t _ext) : 13812695Sar4jc@virginia.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 13912695Sar4jc@virginia.edu false, false, false, false, 14012695Sar4jc@virginia.edu _src1, _imm8, _dest, _srcSize, _destSize, _ext, 14112695Sar4jc@virginia.edu %(op_class)s) 14212695Sar4jc@virginia.edu { 14312695Sar4jc@virginia.edu buildMe(); 14413548Salec.roelke@gmail.com } 14513548Salec.roelke@gmail.com 14613548Salec.roelke@gmail.com inline %(class_name)s::%(class_name)s( 14713548Salec.roelke@gmail.com ExtMachInst machInst, const char * instMnem, 14813548Salec.roelke@gmail.com bool isMicro, bool isDelayed, bool isFirst, bool isLast, 14913548Salec.roelke@gmail.com InstRegIndex _src1, uint16_t _imm8, InstRegIndex _dest, 15011723Sar4jc@virginia.edu uint8_t _srcSize, uint8_t _destSize, uint16_t _ext) : 15112695Sar4jc@virginia.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, 15212695Sar4jc@virginia.edu isMicro, isDelayed, isFirst, isLast, 15312695Sar4jc@virginia.edu _src1, _imm8, _dest, _srcSize, _destSize, _ext, 15412695Sar4jc@virginia.edu %(op_class)s) 15512695Sar4jc@virginia.edu { 15612695Sar4jc@virginia.edu buildMe(); 15712695Sar4jc@virginia.edu } 15812695Sar4jc@virginia.edu}}; 15912695Sar4jc@virginia.edu 16012695Sar4jc@virginia.edulet {{ 16112695Sar4jc@virginia.edu # Make these empty strings so that concatenating onto 16212695Sar4jc@virginia.edu # them will always work. 16312695Sar4jc@virginia.edu header_output = "" 16411723Sar4jc@virginia.edu decoder_output = "" 16511723Sar4jc@virginia.edu exec_output = "" 16611723Sar4jc@virginia.edu 16711723Sar4jc@virginia.edu immTemplates = ( 16811723Sar4jc@virginia.edu MediaOpImmDeclare, 16913612Sgabeblack@google.com MediaOpImmConstructor, 17011723Sar4jc@virginia.edu MediaOpExecute) 17112695Sar4jc@virginia.edu 17212695Sar4jc@virginia.edu regTemplates = ( 17312695Sar4jc@virginia.edu MediaOpRegDeclare, 17411723Sar4jc@virginia.edu MediaOpRegConstructor, 17512695Sar4jc@virginia.edu MediaOpExecute) 17612695Sar4jc@virginia.edu 17711723Sar4jc@virginia.edu class MediaOpMeta(type): 17811723Sar4jc@virginia.edu def buildCppClasses(self, name, Name, suffix, code): 17911723Sar4jc@virginia.edu 18013612Sgabeblack@google.com # Globals to stick the output in 18111723Sar4jc@virginia.edu global header_output 18212695Sar4jc@virginia.edu global decoder_output 18312695Sar4jc@virginia.edu global exec_output 18412695Sar4jc@virginia.edu 18512695Sar4jc@virginia.edu # If op2 is used anywhere, make register and immediate versions 18613548Salec.roelke@gmail.com # of this code. 18713548Salec.roelke@gmail.com matcher = re.compile("(?<!\\w)(?P<prefix>s?)op2(?P<typeQual>\\.\\w+)?") 18813548Salec.roelke@gmail.com match = matcher.search(code) 18913548Salec.roelke@gmail.com if match: 19013548Salec.roelke@gmail.com typeQual = "" 19113548Salec.roelke@gmail.com if match.group("typeQual"): 19213548Salec.roelke@gmail.com typeQual = match.group("typeQual") 19313548Salec.roelke@gmail.com src2_name = "%sFpSrcReg2%s" % (match.group("prefix"), typeQual) 19413548Salec.roelke@gmail.com self.buildCppClasses(name, Name, suffix, 19513548Salec.roelke@gmail.com matcher.sub(src2_name, code)) 19611723Sar4jc@virginia.edu self.buildCppClasses(name + "i", Name, suffix + "Imm", 19711723Sar4jc@virginia.edu matcher.sub("imm8", code)) 19811723Sar4jc@virginia.edu return 19911723Sar4jc@virginia.edu 20011723Sar4jc@virginia.edu base = "X86ISA::MediaOp" 20111723Sar4jc@virginia.edu 20211723Sar4jc@virginia.edu # If imm8 shows up in the code, use the immediate templates, if 20311723Sar4jc@virginia.edu # not, hopefully the register ones will be correct. 20411723Sar4jc@virginia.edu matcher = re.compile("(?<!\w)imm8(?!\w)") 20513582Sgabeblack@google.com if matcher.search(code): 206 base += "Imm" 207 templates = immTemplates 208 else: 209 base += "Reg" 210 templates = regTemplates 211 212 # Get everything ready for the substitution 213 iop = InstObjParams(name, Name + suffix, base, {"code" : code}) 214 215 # Generate the actual code (finally!) 216 header_output += templates[0].subst(iop) 217 decoder_output += templates[1].subst(iop) 218 exec_output += templates[2].subst(iop) 219 220 221 def __new__(mcls, Name, bases, dict): 222 abstract = False 223 name = Name.lower() 224 if "abstract" in dict: 225 abstract = dict['abstract'] 226 del dict['abstract'] 227 228 cls = super(MediaOpMeta, mcls).__new__(mcls, Name, bases, dict) 229 if not abstract: 230 cls.className = Name 231 cls.base_mnemonic = name 232 code = cls.code 233 234 # Set up the C++ classes 235 mcls.buildCppClasses(cls, name, Name, "", code) 236 237 # Hook into the microassembler dict 238 global microopClasses 239 microopClasses[name] = cls 240 241 # If op2 is used anywhere, make register and immediate versions 242 # of this code. 243 matcher = re.compile("op2(?P<typeQual>\\.\\w+)?") 244 if matcher.search(code): 245 microopClasses[name + 'i'] = cls 246 return cls 247 248 249 class MediaOp(X86Microop): 250 __metaclass__ = MediaOpMeta 251 # This class itself doesn't act as a microop 252 abstract = True 253 254 def __init__(self, dest, src1, op2, 255 size = None, destSize = None, srcSize = None, ext = None): 256 self.dest = dest 257 self.src1 = src1 258 self.op2 = op2 259 if size is not None: 260 self.srcSize = size 261 self.destSize = size 262 if srcSize is not None: 263 self.srcSize = srcSize 264 if destSize is not None: 265 self.destSize = destSize 266 if self.srcSize is None: 267 raise Exception, "Source size not set." 268 if self.destSize is None: 269 raise Exception, "Dest size not set." 270 if ext is None: 271 self.ext = 0 272 else: 273 self.ext = ext 274 275 def getAllocator(self, *microFlags): 276 className = self.className 277 if self.mnemonic == self.base_mnemonic + 'i': 278 className += "Imm" 279 allocator = '''new %(class_name)s(machInst, macrocodeBlock 280 %(flags)s, %(src1)s, %(op2)s, %(dest)s, 281 %(srcSize)s, %(destSize)s, %(ext)s)''' % { 282 "class_name" : className, 283 "flags" : self.microFlagsText(microFlags), 284 "src1" : self.src1, "op2" : self.op2, 285 "dest" : self.dest, 286 "srcSize" : self.srcSize, 287 "destSize" : self.destSize, 288 "ext" : self.ext} 289 return allocator 290 291 class Mov2int(MediaOp): 292 def __init__(self, dest, src1, src2 = 0, \ 293 size = None, destSize = None, srcSize = None, ext = None): 294 super(Mov2int, self).__init__(dest, src1,\ 295 src2, size, destSize, srcSize, ext) 296 code = ''' 297 int items = sizeof(FloatRegBits) / srcSize; 298 int offset = imm8; 299 if (bits(src1, 0) && (ext & 0x1)) 300 offset -= items; 301 if (offset >= 0 && offset < items) { 302 uint64_t fpSrcReg1 = 303 bits(FpSrcReg1.uqw, 304 (offset + 1) * srcSize * 8 - 1, 305 (offset + 0) * srcSize * 8); 306 DestReg = merge(0, fpSrcReg1, destSize); 307 } else { 308 DestReg = DestReg; 309 } 310 ''' 311 312 class Mov2fp(MediaOp): 313 def __init__(self, dest, src1, src2 = 0, \ 314 size = None, destSize = None, srcSize = None, ext = None): 315 super(Mov2fp, self).__init__(dest, src1,\ 316 src2, size, destSize, srcSize, ext) 317 code = ''' 318 int items = sizeof(FloatRegBits) / destSize; 319 int offset = imm8; 320 if (bits(dest, 0) && (ext & 0x1)) 321 offset -= items; 322 if (offset >= 0 && offset < items) { 323 uint64_t srcReg1 = pick(SrcReg1, 0, srcSize); 324 FpDestReg.uqw = 325 insertBits(FpDestReg.uqw, 326 (offset + 1) * destSize * 8 - 1, 327 (offset + 0) * destSize * 8, srcReg1); 328 } else { 329 FpDestReg.uqw = FpDestReg.uqw; 330 } 331 ''' 332 333 class Movsign(MediaOp): 334 def __init__(self, dest, src, \ 335 size = None, destSize = None, srcSize = None, ext = None): 336 super(Movsign, self).__init__(dest, src,\ 337 "InstRegIndex(0)", size, destSize, srcSize, ext) 338 code = ''' 339 int items = sizeof(FloatRegBits) / srcSize; 340 uint64_t result = 0; 341 int offset = (ext & 0x1) ? items : 0; 342 for (int i = 0; i < items; i++) { 343 uint64_t picked = 344 bits(FpSrcReg1.uqw, (i + 1) * 8 * srcSize - 1); 345 result = insertBits(result, i + offset, i + offset, picked); 346 } 347 DestReg = DestReg | result; 348 ''' 349 350 class Maskmov(MediaOp): 351 code = ''' 352 assert(srcSize == destSize); 353 int size = srcSize; 354 int sizeBits = size * 8; 355 int items = numItems(size); 356 uint64_t result = FpDestReg.uqw; 357 358 for (int i = 0; i < items; i++) { 359 int hiIndex = (i + 1) * sizeBits - 1; 360 int loIndex = (i + 0) * sizeBits; 361 uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); 362 if (bits(FpSrcReg2.uqw, hiIndex)) 363 result = insertBits(result, hiIndex, loIndex, arg1Bits); 364 } 365 FpDestReg.uqw = result; 366 ''' 367 368 class shuffle(MediaOp): 369 code = ''' 370 assert(srcSize == destSize); 371 int size = srcSize; 372 int sizeBits = size * 8; 373 int items = sizeof(FloatRegBits) / size; 374 int options; 375 int optionBits; 376 if (size == 8) { 377 options = 2; 378 optionBits = 1; 379 } else { 380 options = 4; 381 optionBits = 2; 382 } 383 384 uint64_t result = 0; 385 uint8_t sel = ext; 386 387 for (int i = 0; i < items; i++) { 388 uint64_t resBits; 389 uint8_t lsel = sel & mask(optionBits); 390 if (lsel * size >= sizeof(FloatRegBits)) { 391 lsel -= options / 2; 392 resBits = bits(FpSrcReg2.uqw, 393 (lsel + 1) * sizeBits - 1, 394 (lsel + 0) * sizeBits); 395 } else { 396 resBits = bits(FpSrcReg1.uqw, 397 (lsel + 1) * sizeBits - 1, 398 (lsel + 0) * sizeBits); 399 } 400 401 sel >>= optionBits; 402 403 int hiIndex = (i + 1) * sizeBits - 1; 404 int loIndex = (i + 0) * sizeBits; 405 result = insertBits(result, hiIndex, loIndex, resBits); 406 } 407 FpDestReg.uqw = result; 408 ''' 409 410 class Unpack(MediaOp): 411 code = ''' 412 assert(srcSize == destSize); 413 int size = destSize; 414 int items = (sizeof(FloatRegBits) / size) / 2; 415 int offset = ext ? items : 0; 416 uint64_t result = 0; 417 for (int i = 0; i < items; i++) { 418 uint64_t pickedLow = 419 bits(FpSrcReg1.uqw, (i + offset + 1) * 8 * size - 1, 420 (i + offset) * 8 * size); 421 result = insertBits(result, 422 (2 * i + 1) * 8 * size - 1, 423 (2 * i + 0) * 8 * size, 424 pickedLow); 425 uint64_t pickedHigh = 426 bits(FpSrcReg2.uqw, (i + offset + 1) * 8 * size - 1, 427 (i + offset) * 8 * size); 428 result = insertBits(result, 429 (2 * i + 2) * 8 * size - 1, 430 (2 * i + 1) * 8 * size, 431 pickedHigh); 432 } 433 FpDestReg.uqw = result; 434 ''' 435 436 class Pack(MediaOp): 437 code = ''' 438 assert(srcSize == destSize * 2); 439 int items = (sizeof(FloatRegBits) / destSize); 440 int destBits = destSize * 8; 441 int srcBits = srcSize * 8; 442 uint64_t result = 0; 443 int i; 444 for (i = 0; i < items / 2; i++) { 445 uint64_t picked = 446 bits(FpSrcReg1.uqw, (i + 1) * srcBits - 1, 447 (i + 0) * srcBits); 448 unsigned signBit = bits(picked, srcBits - 1); 449 uint64_t overflow = bits(picked, srcBits - 1, destBits - 1); 450 451 // Handle saturation. 452 if (signBit) { 453 if (overflow != mask(destBits - srcBits + 1)) { 454 if (signedOp()) 455 picked = (ULL(1) << (destBits - 1)); 456 else 457 picked = 0; 458 } 459 } else { 460 if (overflow != 0) { 461 if (signedOp()) 462 picked = mask(destBits - 1); 463 else 464 picked = mask(destBits); 465 } 466 } 467 result = insertBits(result, 468 (i + 1) * destBits - 1, 469 (i + 0) * destBits, 470 picked); 471 } 472 for (;i < items; i++) { 473 uint64_t picked = 474 bits(FpSrcReg2.uqw, (i - items + 1) * srcBits - 1, 475 (i - items + 0) * srcBits); 476 unsigned signBit = bits(picked, srcBits - 1); 477 uint64_t overflow = bits(picked, srcBits - 1, destBits - 1); 478 479 // Handle saturation. 480 if (signBit) { 481 if (overflow != mask(destBits - srcBits + 1)) { 482 if (signedOp()) 483 picked = (ULL(1) << (destBits - 1)); 484 else 485 picked = 0; 486 } 487 } else { 488 if (overflow != 0) { 489 if (signedOp()) 490 picked = mask(destBits - 1); 491 else 492 picked = mask(destBits); 493 } 494 } 495 result = insertBits(result, 496 (i + 1) * destBits - 1, 497 (i + 0) * destBits, 498 picked); 499 } 500 FpDestReg.uqw = result; 501 ''' 502 503 class Mxor(MediaOp): 504 def __init__(self, dest, src1, src2): 505 super(Mxor, self).__init__(dest, src1, src2, 1) 506 code = ''' 507 FpDestReg.uqw = FpSrcReg1.uqw ^ FpSrcReg2.uqw; 508 ''' 509 510 class Mor(MediaOp): 511 def __init__(self, dest, src1, src2): 512 super(Mor, self).__init__(dest, src1, src2, 1) 513 code = ''' 514 FpDestReg.uqw = FpSrcReg1.uqw | FpSrcReg2.uqw; 515 ''' 516 517 class Mand(MediaOp): 518 def __init__(self, dest, src1, src2): 519 super(Mand, self).__init__(dest, src1, src2, 1) 520 code = ''' 521 FpDestReg.uqw = FpSrcReg1.uqw & FpSrcReg2.uqw; 522 ''' 523 524 class Mandn(MediaOp): 525 def __init__(self, dest, src1, src2): 526 super(Mandn, self).__init__(dest, src1, src2, 1) 527 code = ''' 528 FpDestReg.uqw = ~FpSrcReg1.uqw & FpSrcReg2.uqw; 529 ''' 530 531 class Mminf(MediaOp): 532 code = ''' 533 union floatInt 534 { 535 float f; 536 uint32_t i; 537 }; 538 union doubleInt 539 { 540 double d; 541 uint64_t i; 542 }; 543 544 assert(srcSize == destSize); 545 int size = srcSize; 546 int sizeBits = size * 8; 547 assert(srcSize == 4 || srcSize == 8); 548 int items = numItems(size); 549 uint64_t result = FpDestReg.uqw; 550 551 for (int i = 0; i < items; i++) { 552 double arg1, arg2; 553 int hiIndex = (i + 1) * sizeBits - 1; 554 int loIndex = (i + 0) * sizeBits; 555 uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); 556 uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); 557 558 if (size == 4) { 559 floatInt fi; 560 fi.i = arg1Bits; 561 arg1 = fi.f; 562 fi.i = arg2Bits; 563 arg2 = fi.f; 564 } else { 565 doubleInt di; 566 di.i = arg1Bits; 567 arg1 = di.d; 568 di.i = arg2Bits; 569 arg2 = di.d; 570 } 571 572 if (arg1 < arg2) { 573 result = insertBits(result, hiIndex, loIndex, arg1Bits); 574 } else { 575 result = insertBits(result, hiIndex, loIndex, arg2Bits); 576 } 577 } 578 FpDestReg.uqw = result; 579 ''' 580 581 class Mmaxf(MediaOp): 582 code = ''' 583 union floatInt 584 { 585 float f; 586 uint32_t i; 587 }; 588 union doubleInt 589 { 590 double d; 591 uint64_t i; 592 }; 593 594 assert(srcSize == destSize); 595 int size = srcSize; 596 int sizeBits = size * 8; 597 assert(srcSize == 4 || srcSize == 8); 598 int items = numItems(size); 599 uint64_t result = FpDestReg.uqw; 600 601 for (int i = 0; i < items; i++) { 602 double arg1, arg2; 603 int hiIndex = (i + 1) * sizeBits - 1; 604 int loIndex = (i + 0) * sizeBits; 605 uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); 606 uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); 607 608 if (size == 4) { 609 floatInt fi; 610 fi.i = arg1Bits; 611 arg1 = fi.f; 612 fi.i = arg2Bits; 613 arg2 = fi.f; 614 } else { 615 doubleInt di; 616 di.i = arg1Bits; 617 arg1 = di.d; 618 di.i = arg2Bits; 619 arg2 = di.d; 620 } 621 622 if (arg1 > arg2) { 623 result = insertBits(result, hiIndex, loIndex, arg1Bits); 624 } else { 625 result = insertBits(result, hiIndex, loIndex, arg2Bits); 626 } 627 } 628 FpDestReg.uqw = result; 629 ''' 630 631 class Mmini(MediaOp): 632 code = ''' 633 634 assert(srcSize == destSize); 635 int size = srcSize; 636 int sizeBits = size * 8; 637 int items = numItems(size); 638 uint64_t result = FpDestReg.uqw; 639 640 for (int i = 0; i < items; i++) { 641 int hiIndex = (i + 1) * sizeBits - 1; 642 int loIndex = (i + 0) * sizeBits; 643 uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); 644 int64_t arg1 = arg1Bits | 645 (0 - (arg1Bits & (ULL(1) << (sizeBits - 1)))); 646 uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); 647 int64_t arg2 = arg2Bits | 648 (0 - (arg2Bits & (ULL(1) << (sizeBits - 1)))); 649 uint64_t resBits; 650 651 if (signedOp()) { 652 if (arg1 < arg2) { 653 resBits = arg1Bits; 654 } else { 655 resBits = arg2Bits; 656 } 657 } else { 658 if (arg1Bits < arg2Bits) { 659 resBits = arg1Bits; 660 } else { 661 resBits = arg2Bits; 662 } 663 } 664 result = insertBits(result, hiIndex, loIndex, resBits); 665 } 666 FpDestReg.uqw = result; 667 ''' 668 669 class Mmaxi(MediaOp): 670 code = ''' 671 672 assert(srcSize == destSize); 673 int size = srcSize; 674 int sizeBits = size * 8; 675 int items = numItems(size); 676 uint64_t result = FpDestReg.uqw; 677 678 for (int i = 0; i < items; i++) { 679 int hiIndex = (i + 1) * sizeBits - 1; 680 int loIndex = (i + 0) * sizeBits; 681 uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); 682 int64_t arg1 = arg1Bits | 683 (0 - (arg1Bits & (ULL(1) << (sizeBits - 1)))); 684 uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); 685 int64_t arg2 = arg2Bits | 686 (0 - (arg2Bits & (ULL(1) << (sizeBits - 1)))); 687 uint64_t resBits; 688 689 if (signedOp()) { 690 if (arg1 > arg2) { 691 resBits = arg1Bits; 692 } else { 693 resBits = arg2Bits; 694 } 695 } else { 696 if (arg1Bits > arg2Bits) { 697 resBits = arg1Bits; 698 } else { 699 resBits = arg2Bits; 700 } 701 } 702 result = insertBits(result, hiIndex, loIndex, resBits); 703 } 704 FpDestReg.uqw = result; 705 ''' 706 707 class Msqrt(MediaOp): 708 def __init__(self, dest, src, \ 709 size = None, destSize = None, srcSize = None, ext = None): 710 super(Msqrt, self).__init__(dest, src,\ 711 "InstRegIndex(0)", size, destSize, srcSize, ext) 712 code = ''' 713 union floatInt 714 { 715 float f; 716 uint32_t i; 717 }; 718 union doubleInt 719 { 720 double d; 721 uint64_t i; 722 }; 723 724 assert(srcSize == destSize); 725 int size = srcSize; 726 int sizeBits = size * 8; 727 assert(srcSize == 4 || srcSize == 8); 728 int items = numItems(size); 729 uint64_t result = FpDestReg.uqw; 730 731 for (int i = 0; i < items; i++) { 732 int hiIndex = (i + 1) * sizeBits - 1; 733 int loIndex = (i + 0) * sizeBits; 734 uint64_t argBits = bits(FpSrcReg1.uqw, hiIndex, loIndex); 735 736 if (size == 4) { 737 floatInt fi; 738 fi.i = argBits; 739 fi.f = sqrt(fi.f); 740 argBits = fi.i; 741 } else { 742 doubleInt di; 743 di.i = argBits; 744 di.d = sqrt(di.d); 745 argBits = di.i; 746 } 747 result = insertBits(result, hiIndex, loIndex, argBits); 748 } 749 FpDestReg.uqw = result; 750 ''' 751 752 class Maddf(MediaOp): 753 code = ''' 754 union floatInt 755 { 756 float f; 757 uint32_t i; 758 }; 759 union doubleInt 760 { 761 double d; 762 uint64_t i; 763 }; 764 765 assert(srcSize == destSize); 766 int size = srcSize; 767 int sizeBits = size * 8; 768 assert(srcSize == 4 || srcSize == 8); 769 int items = numItems(size); 770 uint64_t result = FpDestReg.uqw; 771 772 for (int i = 0; i < items; i++) { 773 int hiIndex = (i + 1) * sizeBits - 1; 774 int loIndex = (i + 0) * sizeBits; 775 uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); 776 uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); 777 uint64_t resBits; 778 779 if (size == 4) { 780 floatInt arg1, arg2, res; 781 arg1.i = arg1Bits; 782 arg2.i = arg2Bits; 783 res.f = arg1.f + arg2.f; 784 resBits = res.i; 785 } else { 786 doubleInt arg1, arg2, res; 787 arg1.i = arg1Bits; 788 arg2.i = arg2Bits; 789 res.d = arg1.d + arg2.d; 790 resBits = res.i; 791 } 792 793 result = insertBits(result, hiIndex, loIndex, resBits); 794 } 795 FpDestReg.uqw = result; 796 ''' 797 798 class Msubf(MediaOp): 799 code = ''' 800 union floatInt 801 { 802 float f; 803 uint32_t i; 804 }; 805 union doubleInt 806 { 807 double d; 808 uint64_t i; 809 }; 810 811 assert(srcSize == destSize); 812 int size = srcSize; 813 int sizeBits = size * 8; 814 assert(srcSize == 4 || srcSize == 8); 815 int items = numItems(size); 816 uint64_t result = FpDestReg.uqw; 817 818 for (int i = 0; i < items; i++) { 819 int hiIndex = (i + 1) * sizeBits - 1; 820 int loIndex = (i + 0) * sizeBits; 821 uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); 822 uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); 823 uint64_t resBits; 824 825 if (size == 4) { 826 floatInt arg1, arg2, res; 827 arg1.i = arg1Bits; 828 arg2.i = arg2Bits; 829 res.f = arg1.f - arg2.f; 830 resBits = res.i; 831 } else { 832 doubleInt arg1, arg2, res; 833 arg1.i = arg1Bits; 834 arg2.i = arg2Bits; 835 res.d = arg1.d - arg2.d; 836 resBits = res.i; 837 } 838 839 result = insertBits(result, hiIndex, loIndex, resBits); 840 } 841 FpDestReg.uqw = result; 842 ''' 843 844 class Mmulf(MediaOp): 845 code = ''' 846 union floatInt 847 { 848 float f; 849 uint32_t i; 850 }; 851 union doubleInt 852 { 853 double d; 854 uint64_t i; 855 }; 856 857 assert(srcSize == destSize); 858 int size = srcSize; 859 int sizeBits = size * 8; 860 assert(srcSize == 4 || srcSize == 8); 861 int items = numItems(size); 862 uint64_t result = FpDestReg.uqw; 863 864 for (int i = 0; i < items; i++) { 865 int hiIndex = (i + 1) * sizeBits - 1; 866 int loIndex = (i + 0) * sizeBits; 867 uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); 868 uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); 869 uint64_t resBits; 870 871 if (size == 4) { 872 floatInt arg1, arg2, res; 873 arg1.i = arg1Bits; 874 arg2.i = arg2Bits; 875 res.f = arg1.f * arg2.f; 876 resBits = res.i; 877 } else { 878 doubleInt arg1, arg2, res; 879 arg1.i = arg1Bits; 880 arg2.i = arg2Bits; 881 res.d = arg1.d * arg2.d; 882 resBits = res.i; 883 } 884 885 result = insertBits(result, hiIndex, loIndex, resBits); 886 } 887 FpDestReg.uqw = result; 888 ''' 889 890 class Mdivf(MediaOp): 891 code = ''' 892 union floatInt 893 { 894 float f; 895 uint32_t i; 896 }; 897 union doubleInt 898 { 899 double d; 900 uint64_t i; 901 }; 902 903 assert(srcSize == destSize); 904 int size = srcSize; 905 int sizeBits = size * 8; 906 assert(srcSize == 4 || srcSize == 8); 907 int items = numItems(size); 908 uint64_t result = FpDestReg.uqw; 909 910 for (int i = 0; i < items; i++) { 911 int hiIndex = (i + 1) * sizeBits - 1; 912 int loIndex = (i + 0) * sizeBits; 913 uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); 914 uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); 915 uint64_t resBits; 916 917 if (size == 4) { 918 floatInt arg1, arg2, res; 919 arg1.i = arg1Bits; 920 arg2.i = arg2Bits; 921 res.f = arg1.f / arg2.f; 922 resBits = res.i; 923 } else { 924 doubleInt arg1, arg2, res; 925 arg1.i = arg1Bits; 926 arg2.i = arg2Bits; 927 res.d = arg1.d / arg2.d; 928 resBits = res.i; 929 } 930 931 result = insertBits(result, hiIndex, loIndex, resBits); 932 } 933 FpDestReg.uqw = result; 934 ''' 935 936 class Maddi(MediaOp): 937 code = ''' 938 assert(srcSize == destSize); 939 int size = srcSize; 940 int sizeBits = size * 8; 941 int items = numItems(size); 942 uint64_t result = FpDestReg.uqw; 943 944 for (int i = 0; i < items; i++) { 945 int hiIndex = (i + 1) * sizeBits - 1; 946 int loIndex = (i + 0) * sizeBits; 947 uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); 948 uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); 949 uint64_t resBits = arg1Bits + arg2Bits; 950 951 if (ext & 0x2) { 952 if (signedOp()) { 953 int arg1Sign = bits(arg1Bits, sizeBits - 1); 954 int arg2Sign = bits(arg2Bits, sizeBits - 1); 955 int resSign = bits(resBits, sizeBits - 1); 956 if ((arg1Sign == arg2Sign) && (arg1Sign != resSign)) { 957 if (resSign == 0) 958 resBits = (ULL(1) << (sizeBits - 1)); 959 else 960 resBits = mask(sizeBits - 1); 961 } 962 } else { 963 if (findCarry(sizeBits, resBits, arg1Bits, arg2Bits)) 964 resBits = mask(sizeBits); 965 } 966 } 967 968 result = insertBits(result, hiIndex, loIndex, resBits); 969 } 970 FpDestReg.uqw = result; 971 ''' 972 973 class Msubi(MediaOp): 974 code = ''' 975 assert(srcSize == destSize); 976 int size = srcSize; 977 int sizeBits = size * 8; 978 int items = numItems(size); 979 uint64_t result = FpDestReg.uqw; 980 981 for (int i = 0; i < items; i++) { 982 int hiIndex = (i + 1) * sizeBits - 1; 983 int loIndex = (i + 0) * sizeBits; 984 uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); 985 uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); 986 uint64_t resBits = arg1Bits - arg2Bits; 987 988 if (ext & 0x2) { 989 if (signedOp()) { 990 int arg1Sign = bits(arg1Bits, sizeBits - 1); 991 int arg2Sign = !bits(arg2Bits, sizeBits - 1); 992 int resSign = bits(resBits, sizeBits - 1); 993 if ((arg1Sign == arg2Sign) && (arg1Sign != resSign)) { 994 if (resSign == 0) 995 resBits = (ULL(1) << (sizeBits - 1)); 996 else 997 resBits = mask(sizeBits - 1); 998 } 999 } else { 1000 if (arg2Bits > arg1Bits) { 1001 resBits = 0; 1002 } else if (!findCarry(sizeBits, resBits, 1003 arg1Bits, ~arg2Bits)) { 1004 resBits = mask(sizeBits); 1005 } 1006 } 1007 } 1008 1009 result = insertBits(result, hiIndex, loIndex, resBits); 1010 } 1011 FpDestReg.uqw = result; 1012 ''' 1013 1014 class Mmuli(MediaOp): 1015 code = ''' 1016 int srcBits = srcSize * 8; 1017 int destBits = destSize * 8; 1018 assert(destBits <= 64); 1019 assert(destSize >= srcSize); 1020 int items = numItems(destSize); 1021 uint64_t result = FpDestReg.uqw; 1022 1023 for (int i = 0; i < items; i++) { 1024 int offset = 0; 1025 if (ext & 16) { 1026 if (ext & 32) 1027 offset = i * (destBits - srcBits); 1028 else 1029 offset = i * (destBits - srcBits) + srcBits; 1030 } 1031 int srcHiIndex = (i + 1) * srcBits - 1 + offset; 1032 int srcLoIndex = (i + 0) * srcBits + offset; 1033 uint64_t arg1Bits = bits(FpSrcReg1.uqw, srcHiIndex, srcLoIndex); 1034 uint64_t arg2Bits = bits(FpSrcReg2.uqw, srcHiIndex, srcLoIndex); 1035 uint64_t resBits; 1036 1037 if (signedOp()) { 1038 int64_t arg1 = arg1Bits | 1039 (0 - (arg1Bits & (ULL(1) << (srcBits - 1)))); 1040 int64_t arg2 = arg2Bits | 1041 (0 - (arg2Bits & (ULL(1) << (srcBits - 1)))); 1042 resBits = (uint64_t)(arg1 * arg2); 1043 } else { 1044 resBits = arg1Bits * arg2Bits; 1045 } 1046 1047 if (ext & 0x4) 1048 resBits += (ULL(1) << (destBits - 1)); 1049 1050 if (multHi()) 1051 resBits >>= destBits; 1052 1053 int destHiIndex = (i + 1) * destBits - 1; 1054 int destLoIndex = (i + 0) * destBits; 1055 result = insertBits(result, destHiIndex, destLoIndex, resBits); 1056 } 1057 FpDestReg.uqw = result; 1058 ''' 1059 1060 class Mavg(MediaOp): 1061 code = ''' 1062 assert(srcSize == destSize); 1063 int size = srcSize; 1064 int sizeBits = size * 8; 1065 int items = numItems(size); 1066 uint64_t result = FpDestReg.uqw; 1067 1068 for (int i = 0; i < items; i++) { 1069 int hiIndex = (i + 1) * sizeBits - 1; 1070 int loIndex = (i + 0) * sizeBits; 1071 uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); 1072 uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); 1073 uint64_t resBits = (arg1Bits + arg2Bits + 1) / 2; 1074 1075 result = insertBits(result, hiIndex, loIndex, resBits); 1076 } 1077 FpDestReg.uqw = result; 1078 ''' 1079 1080 class Msad(MediaOp): 1081 code = ''' 1082 int srcBits = srcSize * 8; 1083 int items = sizeof(FloatRegBits) / srcSize; 1084 1085 uint64_t sum = 0; 1086 for (int i = 0; i < items; i++) { 1087 int hiIndex = (i + 1) * srcBits - 1; 1088 int loIndex = (i + 0) * srcBits; 1089 uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); 1090 uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); 1091 int64_t resBits = arg1Bits - arg2Bits; 1092 if (resBits < 0) 1093 resBits = -resBits; 1094 sum += resBits; 1095 } 1096 FpDestReg.uqw = sum & mask(destSize * 8); 1097 ''' 1098 1099 class Msrl(MediaOp): 1100 code = ''' 1101 1102 assert(srcSize == destSize); 1103 int size = srcSize; 1104 int sizeBits = size * 8; 1105 int items = numItems(size); 1106 uint64_t shiftAmt = op2.uqw; 1107 uint64_t result = FpDestReg.uqw; 1108 1109 for (int i = 0; i < items; i++) { 1110 int hiIndex = (i + 1) * sizeBits - 1; 1111 int loIndex = (i + 0) * sizeBits; 1112 uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); 1113 uint64_t resBits; 1114 if (shiftAmt >= sizeBits) { 1115 resBits = 0; 1116 } else { 1117 resBits = (arg1Bits >> shiftAmt) & 1118 mask(sizeBits - shiftAmt); 1119 } 1120 1121 result = insertBits(result, hiIndex, loIndex, resBits); 1122 } 1123 FpDestReg.uqw = result; 1124 ''' 1125 1126 class Msra(MediaOp): 1127 code = ''' 1128 1129 assert(srcSize == destSize); 1130 int size = srcSize; 1131 int sizeBits = size * 8; 1132 int items = numItems(size); 1133 uint64_t shiftAmt = op2.uqw; 1134 uint64_t result = FpDestReg.uqw; 1135 1136 for (int i = 0; i < items; i++) { 1137 int hiIndex = (i + 1) * sizeBits - 1; 1138 int loIndex = (i + 0) * sizeBits; 1139 uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); 1140 uint64_t resBits; 1141 if (shiftAmt >= sizeBits) { 1142 if (bits(arg1Bits, sizeBits - 1)) 1143 resBits = mask(sizeBits); 1144 else 1145 resBits = 0; 1146 } else { 1147 resBits = (arg1Bits >> shiftAmt); 1148 resBits = resBits | 1149 (0 - (resBits & (ULL(1) << (sizeBits - 1 - shiftAmt)))); 1150 } 1151 1152 result = insertBits(result, hiIndex, loIndex, resBits); 1153 } 1154 FpDestReg.uqw = result; 1155 ''' 1156 1157 class Msll(MediaOp): 1158 code = ''' 1159 1160 assert(srcSize == destSize); 1161 int size = srcSize; 1162 int sizeBits = size * 8; 1163 int items = numItems(size); 1164 uint64_t shiftAmt = op2.uqw; 1165 uint64_t result = FpDestReg.uqw; 1166 1167 for (int i = 0; i < items; i++) { 1168 int hiIndex = (i + 1) * sizeBits - 1; 1169 int loIndex = (i + 0) * sizeBits; 1170 uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); 1171 uint64_t resBits; 1172 if (shiftAmt >= sizeBits) { 1173 resBits = 0; 1174 } else { 1175 resBits = (arg1Bits << shiftAmt); 1176 } 1177 1178 result = insertBits(result, hiIndex, loIndex, resBits); 1179 } 1180 FpDestReg.uqw = result; 1181 ''' 1182 1183 class Cvtf2i(MediaOp): 1184 def __init__(self, dest, src, \ 1185 size = None, destSize = None, srcSize = None, ext = None): 1186 super(Cvtf2i, self).__init__(dest, src,\ 1187 "InstRegIndex(0)", size, destSize, srcSize, ext) 1188 code = ''' 1189 union floatInt 1190 { 1191 float f; 1192 uint32_t i; 1193 }; 1194 union doubleInt 1195 { 1196 double d; 1197 uint64_t i; 1198 }; 1199 1200 assert(destSize == 4 || destSize == 8); 1201 assert(srcSize == 4 || srcSize == 8); 1202 int srcSizeBits = srcSize * 8; 1203 int destSizeBits = destSize * 8; 1204 int items; 1205 int srcStart = 0; 1206 int destStart = 0; 1207 if (srcSize == 2 * destSize) { 1208 items = numItems(srcSize); 1209 if (ext & 0x2) 1210 destStart = destSizeBits * items; 1211 } else if (destSize == 2 * srcSize) { 1212 items = numItems(destSize); 1213 if (ext & 0x2) 1214 srcStart = srcSizeBits * items; 1215 } else { 1216 items = numItems(destSize); 1217 } 1218 uint64_t result = FpDestReg.uqw; 1219 1220 for (int i = 0; i < items; i++) { 1221 int srcHiIndex = srcStart + (i + 1) * srcSizeBits - 1; 1222 int srcLoIndex = srcStart + (i + 0) * srcSizeBits; 1223 uint64_t argBits = bits(FpSrcReg1.uqw, srcHiIndex, srcLoIndex); 1224 double arg; 1225 1226 if (srcSize == 4) { 1227 floatInt fi; 1228 fi.i = argBits; 1229 arg = fi.f; 1230 } else { 1231 doubleInt di; 1232 di.i = argBits; 1233 arg = di.d; 1234 } 1235 1236 if (ext & 0x4) { 1237 if (arg >= 0) 1238 arg += 0.5; 1239 else 1240 arg -= 0.5; 1241 } 1242 1243 if (destSize == 4) { 1244 argBits = (uint32_t)arg; 1245 } else { 1246 argBits = (uint64_t)arg; 1247 } 1248 int destHiIndex = destStart + (i + 1) * destSizeBits - 1; 1249 int destLoIndex = destStart + (i + 0) * destSizeBits; 1250 result = insertBits(result, destHiIndex, destLoIndex, argBits); 1251 } 1252 FpDestReg.uqw = result; 1253 ''' 1254 1255 class Cvti2f(MediaOp): 1256 def __init__(self, dest, src, \ 1257 size = None, destSize = None, srcSize = None, ext = None): 1258 super(Cvti2f, self).__init__(dest, src,\ 1259 "InstRegIndex(0)", size, destSize, srcSize, ext) 1260 code = ''' 1261 union floatInt 1262 { 1263 float f; 1264 uint32_t i; 1265 }; 1266 union doubleInt 1267 { 1268 double d; 1269 uint64_t i; 1270 }; 1271 1272 assert(destSize == 4 || destSize == 8); 1273 assert(srcSize == 4 || srcSize == 8); 1274 int srcSizeBits = srcSize * 8; 1275 int destSizeBits = destSize * 8; 1276 int items; 1277 int srcStart = 0; 1278 int destStart = 0; 1279 if (srcSize == 2 * destSize) { 1280 items = numItems(srcSize); 1281 if (ext & 0x2) 1282 destStart = destSizeBits * items; 1283 } else if (destSize == 2 * srcSize) { 1284 items = numItems(destSize); 1285 if (ext & 0x2) 1286 srcStart = srcSizeBits * items; 1287 } else { 1288 items = numItems(destSize); 1289 } 1290 uint64_t result = FpDestReg.uqw; 1291 1292 for (int i = 0; i < items; i++) { 1293 int srcHiIndex = srcStart + (i + 1) * srcSizeBits - 1; 1294 int srcLoIndex = srcStart + (i + 0) * srcSizeBits; 1295 uint64_t argBits = bits(FpSrcReg1.uqw, srcHiIndex, srcLoIndex); 1296 1297 int64_t sArg = argBits | 1298 (0 - (argBits & (ULL(1) << (srcSizeBits - 1)))); 1299 double arg = sArg; 1300 1301 if (destSize == 4) { 1302 floatInt fi; 1303 fi.f = arg; 1304 argBits = fi.i; 1305 } else { 1306 doubleInt di; 1307 di.d = arg; 1308 argBits = di.i; 1309 } 1310 int destHiIndex = destStart + (i + 1) * destSizeBits - 1; 1311 int destLoIndex = destStart + (i + 0) * destSizeBits; 1312 result = insertBits(result, destHiIndex, destLoIndex, argBits); 1313 } 1314 FpDestReg.uqw = result; 1315 ''' 1316 1317 class Cvtf2f(MediaOp): 1318 def __init__(self, dest, src, \ 1319 size = None, destSize = None, srcSize = None, ext = None): 1320 super(Cvtf2f, self).__init__(dest, src,\ 1321 "InstRegIndex(0)", size, destSize, srcSize, ext) 1322 code = ''' 1323 union floatInt 1324 { 1325 float f; 1326 uint32_t i; 1327 }; 1328 union doubleInt 1329 { 1330 double d; 1331 uint64_t i; 1332 }; 1333 1334 assert(destSize == 4 || destSize == 8); 1335 assert(srcSize == 4 || srcSize == 8); 1336 int srcSizeBits = srcSize * 8; 1337 int destSizeBits = destSize * 8; 1338 int items; 1339 int srcStart = 0; 1340 int destStart = 0; 1341 if (srcSize == 2 * destSize) { 1342 items = numItems(srcSize); 1343 if (ext & 0x2) 1344 destStart = destSizeBits * items; 1345 } else if (destSize == 2 * srcSize) { 1346 items = numItems(destSize); 1347 if (ext & 0x2) 1348 srcStart = srcSizeBits * items; 1349 } else { 1350 items = numItems(destSize); 1351 } 1352 uint64_t result = FpDestReg.uqw; 1353 1354 for (int i = 0; i < items; i++) { 1355 int srcHiIndex = srcStart + (i + 1) * srcSizeBits - 1; 1356 int srcLoIndex = srcStart + (i + 0) * srcSizeBits; 1357 uint64_t argBits = bits(FpSrcReg1.uqw, srcHiIndex, srcLoIndex); 1358 double arg; 1359 1360 if (srcSize == 4) { 1361 floatInt fi; 1362 fi.i = argBits; 1363 arg = fi.f; 1364 } else { 1365 doubleInt di; 1366 di.i = argBits; 1367 arg = di.d; 1368 } 1369 if (destSize == 4) { 1370 floatInt fi; 1371 fi.f = arg; 1372 argBits = fi.i; 1373 } else { 1374 doubleInt di; 1375 di.d = arg; 1376 argBits = di.i; 1377 } 1378 int destHiIndex = destStart + (i + 1) * destSizeBits - 1; 1379 int destLoIndex = destStart + (i + 0) * destSizeBits; 1380 result = insertBits(result, destHiIndex, destLoIndex, argBits); 1381 } 1382 FpDestReg.uqw = result; 1383 ''' 1384 1385 class Mcmpi2r(MediaOp): 1386 code = ''' 1387 union floatInt 1388 { 1389 float f; 1390 uint32_t i; 1391 }; 1392 union doubleInt 1393 { 1394 double d; 1395 uint64_t i; 1396 }; 1397 1398 assert(srcSize == destSize); 1399 int size = srcSize; 1400 int sizeBits = size * 8; 1401 int items = numItems(size); 1402 uint64_t result = FpDestReg.uqw; 1403 1404 for (int i = 0; i < items; i++) { 1405 int hiIndex = (i + 1) * sizeBits - 1; 1406 int loIndex = (i + 0) * sizeBits; 1407 uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); 1408 int64_t arg1 = arg1Bits | 1409 (0 - (arg1Bits & (ULL(1) << (sizeBits - 1)))); 1410 uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); 1411 int64_t arg2 = arg2Bits | 1412 (0 - (arg2Bits & (ULL(1) << (sizeBits - 1)))); 1413 1414 uint64_t resBits = 0; 1415 if (((ext & 0x2) == 0 && arg1 == arg2) || 1416 ((ext & 0x2) == 0x2 && arg1 > arg2)) 1417 resBits = mask(sizeBits); 1418 1419 result = insertBits(result, hiIndex, loIndex, resBits); 1420 } 1421 FpDestReg.uqw = result; 1422 ''' 1423 1424 class Mcmpf2r(MediaOp): 1425 code = ''' 1426 union floatInt 1427 { 1428 float f; 1429 uint32_t i; 1430 }; 1431 union doubleInt 1432 { 1433 double d; 1434 uint64_t i; 1435 }; 1436 1437 assert(srcSize == destSize); 1438 int size = srcSize; 1439 int sizeBits = size * 8; 1440 int items = numItems(size); 1441 uint64_t result = FpDestReg.uqw; 1442 1443 for (int i = 0; i < items; i++) { 1444 int hiIndex = (i + 1) * sizeBits - 1; 1445 int loIndex = (i + 0) * sizeBits; 1446 uint64_t arg1Bits = bits(FpSrcReg1.uqw, hiIndex, loIndex); 1447 uint64_t arg2Bits = bits(FpSrcReg2.uqw, hiIndex, loIndex); 1448 double arg1, arg2; 1449 1450 if (size == 4) { 1451 floatInt fi; 1452 fi.i = arg1Bits; 1453 arg1 = fi.f; 1454 fi.i = arg2Bits; 1455 arg2 = fi.f; 1456 } else { 1457 doubleInt di; 1458 di.i = arg1Bits; 1459 arg1 = di.d; 1460 di.i = arg2Bits; 1461 arg2 = di.d; 1462 } 1463 1464 uint64_t resBits = 0; 1465 bool nanop = isnan(arg1) || isnan(arg2); 1466 switch (ext & mask(3)) { 1467 case 0: 1468 if (arg1 == arg2 && !nanop) 1469 resBits = mask(sizeBits); 1470 break; 1471 case 1: 1472 if (arg1 < arg2 && !nanop) 1473 resBits = mask(sizeBits); 1474 break; 1475 case 2: 1476 if (arg1 <= arg2 && !nanop) 1477 resBits = mask(sizeBits); 1478 break; 1479 case 3: 1480 if (nanop) 1481 resBits = mask(sizeBits); 1482 break; 1483 case 4: 1484 if (arg1 != arg2 || nanop) 1485 resBits = mask(sizeBits); 1486 break; 1487 case 5: 1488 if (!(arg1 < arg2) || nanop) 1489 resBits = mask(sizeBits); 1490 break; 1491 case 6: 1492 if (!(arg1 <= arg2) || nanop) 1493 resBits = mask(sizeBits); 1494 break; 1495 case 7: 1496 if (!nanop) 1497 resBits = mask(sizeBits); 1498 break; 1499 }; 1500 1501 result = insertBits(result, hiIndex, loIndex, resBits); 1502 } 1503 FpDestReg.uqw = result; 1504 ''' 1505 1506 class Mcmpf2rf(MediaOp): 1507 def __init__(self, src1, src2,\ 1508 size = None, destSize = None, srcSize = None, ext = None): 1509 super(Mcmpf2rf, self).__init__("InstRegIndex(0)", src1,\ 1510 src2, size, destSize, srcSize, ext) 1511 code = ''' 1512 union floatInt 1513 { 1514 float f; 1515 uint32_t i; 1516 }; 1517 union doubleInt 1518 { 1519 double d; 1520 uint64_t i; 1521 }; 1522 1523 assert(srcSize == destSize); 1524 assert(srcSize == 4 || srcSize == 8); 1525 int size = srcSize; 1526 int sizeBits = size * 8; 1527 1528 double arg1, arg2; 1529 uint64_t arg1Bits = bits(FpSrcReg1.uqw, sizeBits - 1, 0); 1530 uint64_t arg2Bits = bits(FpSrcReg2.uqw, sizeBits - 1, 0); 1531 if (size == 4) { 1532 floatInt fi; 1533 fi.i = arg1Bits; 1534 arg1 = fi.f; 1535 fi.i = arg2Bits; 1536 arg2 = fi.f; 1537 } else { 1538 doubleInt di; 1539 di.i = arg1Bits; 1540 arg1 = di.d; 1541 di.i = arg2Bits; 1542 arg2 = di.d; 1543 } 1544 1545 // ZF PF CF 1546 // Unordered 1 1 1 1547 // Greater than 0 0 0 1548 // Less than 0 0 1 1549 // Equal 1 0 0 1550 // OF = SF = AF = 0 1551 ccFlagBits = ccFlagBits & ~(OFBit | SFBit | AFBit | 1552 ZFBit | PFBit | CFBit); 1553 if (isnan(arg1) || isnan(arg2)) 1554 ccFlagBits = ccFlagBits | (ZFBit | PFBit | CFBit); 1555 else if(arg1 < arg2) 1556 ccFlagBits = ccFlagBits | CFBit; 1557 else if(arg1 == arg2) 1558 ccFlagBits = ccFlagBits | ZFBit; 1559 ''' 1560}}; 1561