ldstop.isa revision 7874:c7f15c60898e 
1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company
2// All rights reserved.
3//
4// The license below extends only to copyright in the software and shall
5// not be construed as granting a license to any other intellectual
6// property including but not limited to intellectual property relating
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8// licensed hereunder.  You may use the software subject to the license
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12//
13// Copyright (c) 2008 The Regents of The University of Michigan
14// All rights reserved.
15//
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17// modification, are permitted provided that the following conditions are
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37// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38//
39// Authors: Gabe Black
40
41//////////////////////////////////////////////////////////////////////////
42//
43// LdStOp Microop templates
44//
45//////////////////////////////////////////////////////////////////////////
46
47// LEA template
48
49def template MicroLeaExecute {{
50    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
51          Trace::InstRecord *traceData) const
52    {
53        Fault fault = NoFault;
54        Addr EA;
55
56        %(op_decl)s;
57        %(op_rd)s;
58        %(ea_code)s;
59        DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
60
61        %(code)s;
62        if(fault == NoFault)
63        {
64            %(op_wb)s;
65        }
66
67        return fault;
68    }
69}};
70
71def template MicroLeaDeclare {{
72    class %(class_name)s : public %(base_class)s
73    {
74      public:
75        %(class_name)s(ExtMachInst _machInst,
76                const char * instMnem, uint64_t setFlags,
77                uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
78                uint64_t _disp, InstRegIndex _segment,
79                InstRegIndex _data,
80                uint8_t _dataSize, uint8_t _addressSize,
81                Request::FlagsType _memFlags);
82
83        %(BasicExecDeclare)s
84    };
85}};
86
87// Load templates
88
89def template MicroLoadExecute {{
90    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
91          Trace::InstRecord *traceData) const
92    {
93        Fault fault = NoFault;
94        Addr EA;
95
96        %(op_decl)s;
97        %(op_rd)s;
98        %(ea_code)s;
99        DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
100
101        fault = read(xc, EA, Mem, memFlags);
102
103        if (fault == NoFault) {
104            %(code)s;
105        } else if (memFlags & Request::PREFETCH) {
106            // For prefetches, ignore any faults/exceptions.
107            return NoFault;
108        }
109        if(fault == NoFault)
110        {
111            %(op_wb)s;
112        }
113
114        return fault;
115    }
116}};
117
118def template MicroLoadInitiateAcc {{
119    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
120            Trace::InstRecord * traceData) const
121    {
122        Fault fault = NoFault;
123        Addr EA;
124
125        %(op_decl)s;
126        %(op_rd)s;
127        %(ea_code)s;
128        DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
129
130        fault = read(xc, EA, Mem, memFlags);
131
132        return fault;
133    }
134}};
135
136def template MicroLoadCompleteAcc {{
137    Fault %(class_name)s::completeAcc(PacketPtr pkt,
138            %(CPU_exec_context)s * xc,
139            Trace::InstRecord * traceData) const
140    {
141        Fault fault = NoFault;
142
143        %(op_decl)s;
144        %(op_rd)s;
145
146        Mem = get(pkt);
147
148        %(code)s;
149
150        if(fault == NoFault)
151        {
152            %(op_wb)s;
153        }
154
155        return fault;
156    }
157}};
158
159// Store templates
160
161def template MicroStoreExecute {{
162    Fault %(class_name)s::execute(%(CPU_exec_context)s * xc,
163            Trace::InstRecord *traceData) const
164    {
165        Fault fault = NoFault;
166
167        Addr EA;
168        %(op_decl)s;
169        %(op_rd)s;
170        %(ea_code)s;
171        DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
172
173        %(code)s;
174
175        if(fault == NoFault)
176        {
177            fault = write(xc, Mem, EA, memFlags);
178            if(fault == NoFault)
179            {
180                %(post_code)s;
181                %(op_wb)s;
182            }
183        }
184
185        return fault;
186    }
187}};
188
189def template MicroStoreInitiateAcc {{
190    Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
191            Trace::InstRecord * traceData) const
192    {
193        Fault fault = NoFault;
194
195        Addr EA;
196        %(op_decl)s;
197        %(op_rd)s;
198        %(ea_code)s;
199        DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
200
201        %(code)s;
202
203        if(fault == NoFault)
204        {
205            write(xc, Mem, EA, memFlags);
206        }
207        return fault;
208    }
209}};
210
211def template MicroStoreCompleteAcc {{
212    Fault %(class_name)s::completeAcc(PacketPtr pkt,
213            %(CPU_exec_context)s * xc, Trace::InstRecord * traceData) const
214    {
215        %(op_decl)s;
216        %(op_rd)s;
217        %(complete_code)s;
218        %(op_wb)s;
219        return NoFault;
220    }
221}};
222
223// Common templates
224
225//This delcares the initiateAcc function in memory operations
226def template InitiateAccDeclare {{
227    Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const;
228}};
229
230//This declares the completeAcc function in memory operations
231def template CompleteAccDeclare {{
232    Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const;
233}};
234
235def template MicroLdStOpDeclare {{
236    class %(class_name)s : public %(base_class)s
237    {
238      public:
239        %(class_name)s(ExtMachInst _machInst,
240                const char * instMnem, uint64_t setFlags,
241                uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
242                uint64_t _disp, InstRegIndex _segment,
243                InstRegIndex _data,
244                uint8_t _dataSize, uint8_t _addressSize,
245                Request::FlagsType _memFlags);
246
247        %(BasicExecDeclare)s
248
249        %(InitiateAccDeclare)s
250
251        %(CompleteAccDeclare)s
252    };
253}};
254
255def template MicroLdStOpConstructor {{
256    inline %(class_name)s::%(class_name)s(
257            ExtMachInst machInst, const char * instMnem, uint64_t setFlags,
258            uint8_t _scale, InstRegIndex _index, InstRegIndex _base,
259            uint64_t _disp, InstRegIndex _segment,
260            InstRegIndex _data,
261            uint8_t _dataSize, uint8_t _addressSize,
262            Request::FlagsType _memFlags) :
263        %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags,
264                _scale, _index, _base,
265                _disp, _segment, _data,
266                _dataSize, _addressSize, _memFlags, %(op_class)s)
267    {
268        %(constructor)s;
269    }
270}};
271
272let {{
273    class LdStOp(X86Microop):
274        def __init__(self, data, segment, addr, disp,
275                dataSize, addressSize, baseFlags, atCPL0, prefetch):
276            self.data = data
277            [self.scale, self.index, self.base] = addr
278            self.disp = disp
279            self.segment = segment
280            self.dataSize = dataSize
281            self.addressSize = addressSize
282            self.memFlags = baseFlags
283            if atCPL0:
284                self.memFlags += " | (CPL0FlagBit << FlagShift)"
285            if prefetch:
286                self.memFlags += " | Request::PREFETCH"
287            self.memFlags += " | (machInst.legacy.addr ? " + \
288                             "(AddrSizeFlagBit << FlagShift) : 0)"
289
290        def getAllocator(self, microFlags):
291            allocator = '''new %(class_name)s(machInst, macrocodeBlock,
292                    %(flags)s, %(scale)s, %(index)s, %(base)s,
293                    %(disp)s, %(segment)s, %(data)s,
294                    %(dataSize)s, %(addressSize)s, %(memFlags)s)''' % {
295                "class_name" : self.className,
296                "flags" : self.microFlagsText(microFlags),
297                "scale" : self.scale, "index" : self.index,
298                "base" : self.base,
299                "disp" : self.disp,
300                "segment" : self.segment, "data" : self.data,
301                "dataSize" : self.dataSize, "addressSize" : self.addressSize,
302                "memFlags" : self.memFlags}
303            return allocator
304}};
305
306let {{
307
308    # Make these empty strings so that concatenating onto
309    # them will always work.
310    header_output = ""
311    decoder_output = ""
312    exec_output = ""
313
314    calculateEA = '''
315    EA = bits(SegBase + scale * Index + Base + disp, addressSize * 8 - 1, 0);
316    '''
317
318    def defineMicroLoadOp(mnemonic, code, mem_flags="0"):
319        global header_output
320        global decoder_output
321        global exec_output
322        global microopClasses
323        Name = mnemonic
324        name = mnemonic.lower()
325
326        # Build up the all register version of this micro op
327        iop = InstObjParams(name, Name, 'X86ISA::LdStOp',
328                {"code": code,
329                 "ea_code": calculateEA})
330        header_output += MicroLdStOpDeclare.subst(iop)
331        decoder_output += MicroLdStOpConstructor.subst(iop)
332        exec_output += MicroLoadExecute.subst(iop)
333        exec_output += MicroLoadInitiateAcc.subst(iop)
334        exec_output += MicroLoadCompleteAcc.subst(iop)
335
336        class LoadOp(LdStOp):
337            def __init__(self, data, segment, addr, disp = 0,
338                    dataSize="env.dataSize",
339                    addressSize="env.addressSize",
340                    atCPL0=False, prefetch=False):
341                super(LoadOp, self).__init__(data, segment, addr,
342                        disp, dataSize, addressSize, mem_flags,
343                        atCPL0, prefetch)
344                self.className = Name
345                self.mnemonic = name
346
347        microopClasses[name] = LoadOp
348
349    defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);')
350    defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);',
351            '(StoreCheck << FlagShift)')
352    defineMicroLoadOp('Ldstl', 'Data = merge(Data, Mem, dataSize);',
353            '(StoreCheck << FlagShift) | Request::LOCKED')
354    defineMicroLoadOp('Ldfp', 'FpData.uqw = Mem;')
355
356    def defineMicroStoreOp(mnemonic, code, \
357            postCode="", completeCode="", mem_flags="0"):
358        global header_output
359        global decoder_output
360        global exec_output
361        global microopClasses
362        Name = mnemonic
363        name = mnemonic.lower()
364
365        # Build up the all register version of this micro op
366        iop = InstObjParams(name, Name, 'X86ISA::LdStOp',
367                {"code": code,
368                 "post_code": postCode,
369                 "complete_code": completeCode,
370                 "ea_code": calculateEA})
371        header_output += MicroLdStOpDeclare.subst(iop)
372        decoder_output += MicroLdStOpConstructor.subst(iop)
373        exec_output += MicroStoreExecute.subst(iop)
374        exec_output += MicroStoreInitiateAcc.subst(iop)
375        exec_output += MicroStoreCompleteAcc.subst(iop)
376
377        class StoreOp(LdStOp):
378            def __init__(self, data, segment, addr, disp = 0,
379                    dataSize="env.dataSize",
380                    addressSize="env.addressSize",
381                    atCPL0=False):
382                super(StoreOp, self).__init__(data, segment, addr,
383                        disp, dataSize, addressSize, mem_flags, atCPL0, False)
384                self.className = Name
385                self.mnemonic = name
386
387        microopClasses[name] = StoreOp
388
389    defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);')
390    defineMicroStoreOp('Stul', 'Mem = pick(Data, 2, dataSize);',
391            mem_flags="Request::LOCKED")
392    defineMicroStoreOp('Stfp', 'Mem = FpData.uqw;')
393    defineMicroStoreOp('Cda', 'Mem = 0;', mem_flags="Request::NO_ACCESS")
394
395    iop = InstObjParams("lea", "Lea", 'X86ISA::LdStOp',
396            {"code": "Data = merge(Data, EA, dataSize);",
397             "ea_code": '''
398             EA = bits(scale * Index + Base + disp, addressSize * 8 - 1, 0);
399             '''})
400    header_output += MicroLeaDeclare.subst(iop)
401    decoder_output += MicroLdStOpConstructor.subst(iop)
402    exec_output += MicroLeaExecute.subst(iop)
403
404    class LeaOp(LdStOp):
405        def __init__(self, data, segment, addr, disp = 0,
406                dataSize="env.dataSize", addressSize="env.addressSize"):
407            super(LeaOp, self).__init__(data, segment,
408                    addr, disp, dataSize, addressSize, "0", False, False)
409            self.className = "Lea"
410            self.mnemonic = "lea"
411
412    microopClasses["lea"] = LeaOp
413
414
415    iop = InstObjParams("tia", "Tia", 'X86ISA::LdStOp',
416            {"code": "xc->demapPage(EA, 0);",
417             "ea_code": calculateEA})
418    header_output += MicroLeaDeclare.subst(iop)
419    decoder_output += MicroLdStOpConstructor.subst(iop)
420    exec_output += MicroLeaExecute.subst(iop)
421
422    class TiaOp(LdStOp):
423        def __init__(self, segment, addr, disp = 0,
424                dataSize="env.dataSize",
425                addressSize="env.addressSize"):
426            super(TiaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
427                    addr, disp, dataSize, addressSize, "0", False, False)
428            self.className = "Tia"
429            self.mnemonic = "tia"
430
431    microopClasses["tia"] = TiaOp
432
433    class CdaOp(LdStOp):
434        def __init__(self, segment, addr, disp = 0,
435                dataSize="env.dataSize",
436                addressSize="env.addressSize", atCPL0=False):
437            super(CdaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment,
438                    addr, disp, dataSize, addressSize, "Request::NO_ACCESS",
439                    atCPL0, False)
440            self.className = "Cda"
441            self.mnemonic = "cda"
442
443    microopClasses["cda"] = CdaOp
444}};
445
446