ldstop.isa revision 8102
12SN/A// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 22190SN/A// All rights reserved. 32SN/A// 42SN/A// The license below extends only to copyright in the software and shall 52SN/A// not be construed as granting a license to any other intellectual 62SN/A// property including but not limited to intellectual property relating 72SN/A// to a hardware implementation of the functionality of the software 82SN/A// licensed hereunder. You may use the software subject to the license 92SN/A// terms below provided that you ensure that this notice is replicated 102SN/A// unmodified and in its entirety in all distributions of the software, 112SN/A// modified or unmodified, in source code or in binary form. 122SN/A// 132SN/A// Copyright (c) 2008 The Regents of The University of Michigan 142SN/A// All rights reserved. 152SN/A// 162SN/A// Redistribution and use in source and binary forms, with or without 172SN/A// modification, are permitted provided that the following conditions are 182SN/A// met: redistributions of source code must retain the above copyright 192SN/A// notice, this list of conditions and the following disclaimer; 202SN/A// redistributions in binary form must reproduce the above copyright 212SN/A// notice, this list of conditions and the following disclaimer in the 222SN/A// documentation and/or other materials provided with the distribution; 232SN/A// neither the name of the copyright holders nor the names of its 242SN/A// contributors may be used to endorse or promote products derived from 252SN/A// this software without specific prior written permission. 262SN/A// 272665SN/A// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 282665SN/A// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 292SN/A// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 302SN/A// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 312680Sktlim@umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 322680Sktlim@umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 332SN/A// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 342972Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 353453Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 361858SN/A// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 372423SN/A// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 382190SN/A// 3956SN/A// Authors: Gabe Black 40217SN/A 413776Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 422036SN/A// 432SN/A// LdStOp Microop templates 442190SN/A// 452190SN/A////////////////////////////////////////////////////////////////////////// 463453Sgblack@eecs.umich.edu 473453Sgblack@eecs.umich.edu// LEA template 483453Sgblack@eecs.umich.edu 493453Sgblack@eecs.umich.edudef template MicroLeaExecute {{ 503453Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 512190SN/A Trace::InstRecord *traceData) const 522313SN/A { 532235SN/A Fault fault = NoFault; 542423SN/A Addr EA; 552521SN/A 562521SN/A %(op_decl)s; 572190SN/A %(op_rd)s; 582190SN/A %(ea_code)s; 593548Sgblack@eecs.umich.edu DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); 603548Sgblack@eecs.umich.edu 613548Sgblack@eecs.umich.edu %(code)s; 623548Sgblack@eecs.umich.edu if(fault == NoFault) 632330SN/A { 642SN/A %(op_wb)s; 652680Sktlim@umich.edu } 662680Sktlim@umich.edu 672680Sktlim@umich.edu return fault; 682680Sktlim@umich.edu } 692680Sktlim@umich.edu}}; 702680Sktlim@umich.edu 712680Sktlim@umich.edudef template MicroLeaDeclare {{ 722680Sktlim@umich.edu class %(class_name)s : public %(base_class)s 732680Sktlim@umich.edu { 742680Sktlim@umich.edu public: 752680Sktlim@umich.edu %(class_name)s(ExtMachInst _machInst, 762682Sktlim@umich.edu const char * instMnem, uint64_t setFlags, 772680Sktlim@umich.edu uint8_t _scale, InstRegIndex _index, InstRegIndex _base, 782680Sktlim@umich.edu uint64_t _disp, InstRegIndex _segment, 792680Sktlim@umich.edu InstRegIndex _data, 802680Sktlim@umich.edu uint8_t _dataSize, uint8_t _addressSize, 812680Sktlim@umich.edu Request::FlagsType _memFlags); 822SN/A 832107SN/A %(BasicExecDeclare)s 842107SN/A }; 852107SN/A}}; 862190SN/A 872455SN/A// Load templates 882455SN/A 892107SN/Adef template MicroLoadExecute {{ 902159SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 912SN/A Trace::InstRecord *traceData) const 92246SN/A { 93246SN/A Fault fault = NoFault; 94246SN/A Addr EA; 95246SN/A 96246SN/A %(op_decl)s; 97246SN/A %(op_rd)s; 98246SN/A %(ea_code)s; 99246SN/A DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); 100246SN/A 101246SN/A fault = read(xc, EA, Mem, memFlags); 102246SN/A 103246SN/A if (fault == NoFault) { 104246SN/A %(code)s; 1052190SN/A } else if (memFlags & Request::PREFETCH) { 106246SN/A // For prefetches, ignore any faults/exceptions. 107246SN/A return NoFault; 108246SN/A } 109246SN/A if(fault == NoFault) 110246SN/A { 111246SN/A %(op_wb)s; 112246SN/A } 1132SN/A 1142680Sktlim@umich.edu return fault; 1152423SN/A } 1162190SN/A}}; 117180SN/A 1185712Shsul@eecs.umich.edudef template MicroLoadInitiateAcc {{ 1192190SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 1203453Sgblack@eecs.umich.edu Trace::InstRecord * traceData) const 1212190SN/A { 1223453Sgblack@eecs.umich.edu Fault fault = NoFault; 1232521SN/A Addr EA; 1244997Sgblack@eecs.umich.edu 1254997Sgblack@eecs.umich.edu %(op_decl)s; 1264997Sgblack@eecs.umich.edu %(op_rd)s; 1273548Sgblack@eecs.umich.edu %(ea_code)s; 1282654SN/A DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); 1292521SN/A 1302521SN/A fault = read(xc, EA, Mem, memFlags); 1315499Ssaidi@eecs.umich.edu 1323673Srdreslin@umich.edu return fault; 1335497Ssaidi@eecs.umich.edu } 1342190SN/A}}; 1352518SN/A 1362518SN/Adef template MicroLoadCompleteAcc {{ 1372190SN/A Fault %(class_name)s::completeAcc(PacketPtr pkt, 1382190SN/A %(CPU_exec_context)s * xc, 1392190SN/A Trace::InstRecord * traceData) const 1402190SN/A { 1412159SN/A Fault fault = NoFault; 1422235SN/A 1432103SN/A %(op_decl)s; 144393SN/A %(op_rd)s; 145393SN/A 1462190SN/A Mem = get(pkt); 147393SN/A 148393SN/A %(code)s; 1495250Sksewell@umich.edu 150393SN/A if(fault == NoFault) 151393SN/A { 1522875Sksewell@umich.edu %(op_wb)s; 153393SN/A } 154393SN/A 1555250Sksewell@umich.edu return fault; 1562159SN/A } 1572159SN/A}}; 1582190SN/A 1592159SN/A// Store templates 1602159SN/A 1612680Sktlim@umich.edudef template MicroStoreExecute {{ 1622159SN/A Fault %(class_name)s::execute(%(CPU_exec_context)s * xc, 1632190SN/A Trace::InstRecord *traceData) const 1642159SN/A { 1652190SN/A Fault fault = NoFault; 1662190SN/A 1672159SN/A Addr EA; 1682235SN/A %(op_decl)s; 1692313SN/A %(op_rd)s; 1702235SN/A %(ea_code)s; 1712235SN/A DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); 1722235SN/A 1732235SN/A %(code)s; 1742235SN/A 1752254SN/A if(fault == NoFault) 1762254SN/A { 1772254SN/A fault = write(xc, Mem, EA, memFlags); 1782235SN/A if(fault == NoFault) 1792235SN/A { 1802190SN/A %(post_code)s; 1812159SN/A %(op_wb)s; 1822235SN/A } 1832254SN/A } 1842190SN/A 1852159SN/A return fault; 1862680Sktlim@umich.edu } 1872159SN/A}}; 1882190SN/A 1892159SN/Adef template MicroStoreInitiateAcc {{ 1902159SN/A Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 1912159SN/A Trace::InstRecord * traceData) const 1922159SN/A { 1932190SN/A Fault fault = NoFault; 1942159SN/A 1952455SN/A Addr EA; 1962159SN/A %(op_decl)s; 1972455SN/A %(op_rd)s; 1982159SN/A %(ea_code)s; 1992455SN/A DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); 2002455SN/A 2012455SN/A %(code)s; 2022159SN/A 2032190SN/A if(fault == NoFault) 2042159SN/A { 2052455SN/A write(xc, Mem, EA, memFlags); 2062159SN/A } 2072455SN/A return fault; 2082159SN/A } 2092455SN/A}}; 2102455SN/A 2112455SN/Adef template MicroStoreCompleteAcc {{ 2122159SN/A Fault %(class_name)s::completeAcc(PacketPtr pkt, 2132190SN/A %(CPU_exec_context)s * xc, Trace::InstRecord * traceData) const 2142159SN/A { 2152190SN/A %(op_decl)s; 2162159SN/A %(op_rd)s; 2172190SN/A %(complete_code)s; 2182159SN/A %(op_wb)s; 2192190SN/A return NoFault; 2202159SN/A } 2212447SN/A}}; 2222447SN/A 2232447SN/A// Common templates 2242447SN/A 2255260Sksewell@umich.edu//This delcares the initiateAcc function in memory operations 2265260Sksewell@umich.edudef template InitiateAccDeclare {{ 2275260Sksewell@umich.edu Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 2285260Sksewell@umich.edu}}; 2295260Sksewell@umich.edu 2305260Sksewell@umich.edu//This declares the completeAcc function in memory operations 2315260Sksewell@umich.edudef template CompleteAccDeclare {{ 2325260Sksewell@umich.edu Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 2334172Ssaidi@eecs.umich.edu}}; 2344172Ssaidi@eecs.umich.edu 2352190SN/Adef template MicroLdStOpDeclare {{ 2362159SN/A class %(class_name)s : public %(base_class)s 2374172Ssaidi@eecs.umich.edu { 2382190SN/A public: 2393468Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 2402190SN/A const char * instMnem, uint64_t setFlags, 2414661Sksewell@umich.edu uint8_t _scale, InstRegIndex _index, InstRegIndex _base, 2424661Sksewell@umich.edu uint64_t _disp, InstRegIndex _segment, 2434661Sksewell@umich.edu InstRegIndex _data, 2444661Sksewell@umich.edu uint8_t _dataSize, uint8_t _addressSize, 2452235SN/A Request::FlagsType _memFlags); 2462235SN/A 2472190SN/A %(BasicExecDeclare)s 2482190SN/A 2492190SN/A %(InitiateAccDeclare)s 2502159SN/A 2512235SN/A %(CompleteAccDeclare)s 2522190SN/A }; 2532190SN/A}}; 2542159SN/A 2552190SN/Adef template MicroLdStOpConstructor {{ 2562159SN/A inline %(class_name)s::%(class_name)s( 2572159SN/A ExtMachInst machInst, const char * instMnem, uint64_t setFlags, 2582190SN/A uint8_t _scale, InstRegIndex _index, InstRegIndex _base, 2592159SN/A uint64_t _disp, InstRegIndex _segment, 2602190SN/A InstRegIndex _data, 2612159SN/A uint8_t _dataSize, uint8_t _addressSize, 2622235SN/A Request::FlagsType _memFlags) : 2632190SN/A %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags, 2642834Sksewell@umich.edu _scale, _index, _base, 2654111Sgblack@eecs.umich.edu _disp, _segment, _data, 2664111Sgblack@eecs.umich.edu _dataSize, _addressSize, _memFlags, %(op_class)s) 2672834Sksewell@umich.edu { 2682834Sksewell@umich.edu %(constructor)s; 2692834Sksewell@umich.edu } 2702834Sksewell@umich.edu}}; 2712159SN/A 2722525SN/Alet {{ 2735217Ssaidi@eecs.umich.edu class LdStOp(X86Microop): 2745217Ssaidi@eecs.umich.edu def __init__(self, data, segment, addr, disp, 2752159SN/A dataSize, addressSize, baseFlags, atCPL0, prefetch): 2762159SN/A self.data = data 2772682Sktlim@umich.edu [self.scale, self.index, self.base] = addr 2782682Sktlim@umich.edu self.disp = disp 2792682Sktlim@umich.edu self.segment = segment 2802682Sktlim@umich.edu self.dataSize = dataSize 2812682Sktlim@umich.edu self.addressSize = addressSize 2822682Sktlim@umich.edu self.memFlags = baseFlags 2832682Sktlim@umich.edu if atCPL0: 2842682Sktlim@umich.edu self.memFlags += " | (CPL0FlagBit << FlagShift)" 2852682Sktlim@umich.edu self.instFlags = "" 2862682Sktlim@umich.edu if prefetch: 2872680Sktlim@umich.edu self.memFlags += " | Request::PREFETCH" 2882680Sktlim@umich.edu self.instFlags += " | StaticInst::IsDataPrefetch" 2892190SN/A self.memFlags += " | (machInst.legacy.addr ? " + \ 2902190SN/A "(AddrSizeFlagBit << FlagShift) : 0)" 2912680Sktlim@umich.edu 2922680Sktlim@umich.edu def getAllocator(self, microFlags): 2932159SN/A allocator = '''new %(class_name)s(machInst, macrocodeBlock, 2942190SN/A %(flags)s, %(scale)s, %(index)s, %(base)s, 2952680Sktlim@umich.edu %(disp)s, %(segment)s, %(data)s, 2962SN/A %(dataSize)s, %(addressSize)s, %(memFlags)s)''' % { 2972SN/A "class_name" : self.className, 2982SN/A "flags" : self.microFlagsText(microFlags) + self.instFlags, 2992680Sktlim@umich.edu "scale" : self.scale, "index" : self.index, 3002SN/A "base" : self.base, 3015712Shsul@eecs.umich.edu "disp" : self.disp, 3022SN/A "segment" : self.segment, "data" : self.data, 3033453Sgblack@eecs.umich.edu "dataSize" : self.dataSize, "addressSize" : self.addressSize, 3041917SN/A "memFlags" : self.memFlags} 3053453Sgblack@eecs.umich.edu return allocator 3062521SN/A 3074997Sgblack@eecs.umich.edu class BigLdStOp(X86Microop): 3084997Sgblack@eecs.umich.edu def __init__(self, data, segment, addr, disp, 3094997Sgblack@eecs.umich.edu dataSize, addressSize, baseFlags, atCPL0, prefetch): 3103548Sgblack@eecs.umich.edu self.data = data 3113548Sgblack@eecs.umich.edu [self.scale, self.index, self.base] = addr 3122654SN/A self.disp = disp 3132680Sktlim@umich.edu self.segment = segment 3142521SN/A self.dataSize = dataSize 3155499Ssaidi@eecs.umich.edu self.addressSize = addressSize 3163673Srdreslin@umich.edu self.memFlags = baseFlags 3175497Ssaidi@eecs.umich.edu if atCPL0: 3182SN/A self.memFlags += " | (CPL0FlagBit << FlagShift)" 3192680Sktlim@umich.edu if prefetch: 3202518SN/A self.memFlags += " | Request::PREFETCH" 3212680Sktlim@umich.edu self.memFlags += " | (machInst.legacy.addr ? " + \ 3222SN/A "(AddrSizeFlagBit << FlagShift) : 0)" 3232SN/A 3242680Sktlim@umich.edu def getAllocator(self, microFlags): 325595SN/A allocString = ''' 3262680Sktlim@umich.edu (%(dataSize)s >= 4) ? 3272SN/A (StaticInstPtr)(new %(class_name)sBig(machInst, 3282190SN/A macrocodeBlock, %(flags)s, %(scale)s, %(index)s, 3292190SN/A %(base)s, %(disp)s, %(segment)s, %(data)s, 3302680Sktlim@umich.edu %(dataSize)s, %(addressSize)s, %(memFlags)s)) : 3312SN/A (StaticInstPtr)(new %(class_name)s(machInst, 3322190SN/A macrocodeBlock, %(flags)s, %(scale)s, %(index)s, 3335250Sksewell@umich.edu %(base)s, %(disp)s, %(segment)s, %(data)s, 3342SN/A %(dataSize)s, %(addressSize)s, %(memFlags)s)) 3352190SN/A ''' 3362875Sksewell@umich.edu allocator = allocString % { 3372SN/A "class_name" : self.className, 3382190SN/A "flags" : self.microFlagsText(microFlags), 3395250Sksewell@umich.edu "scale" : self.scale, "index" : self.index, 340217SN/A "base" : self.base, 3411858SN/A "disp" : self.disp, 3422680Sktlim@umich.edu "segment" : self.segment, "data" : self.data, 3432190SN/A "dataSize" : self.dataSize, "addressSize" : self.addressSize, 3442190SN/A "memFlags" : self.memFlags} 3452680Sktlim@umich.edu return allocator 3462680Sktlim@umich.edu}}; 3472190SN/A 3482680Sktlim@umich.edulet {{ 3492190SN/A 3502680Sktlim@umich.edu # Make these empty strings so that concatenating onto 3512190SN/A # them will always work. 3522680Sktlim@umich.edu header_output = "" 3532190SN/A decoder_output = "" 3542235SN/A exec_output = "" 3552680Sktlim@umich.edu 3562235SN/A calculateEA = ''' 3572680Sktlim@umich.edu EA = bits(SegBase + scale * Index + Base + disp, addressSize * 8 - 1, 0); 3582680Sktlim@umich.edu ''' 3592254SN/A 3602680Sktlim@umich.edu def defineMicroLoadOp(mnemonic, code, bigCode='', 3612680Sktlim@umich.edu mem_flags="0", big=True): 3622235SN/A global header_output 3632235SN/A global decoder_output 3642680Sktlim@umich.edu global exec_output 3652190SN/A global microopClasses 3662190SN/A Name = mnemonic 3672680Sktlim@umich.edu name = mnemonic.lower() 3682SN/A 3692190SN/A # Build up the all register version of this micro op 3702680Sktlim@umich.edu iops = [InstObjParams(name, Name, 'X86ISA::LdStOp', 3712SN/A {"code": code, "ea_code": calculateEA})] 3722680Sktlim@umich.edu if big: 373716SN/A iops += [InstObjParams(name, Name + "Big", 'X86ISA::LdStOp', 3742SN/A {"code": bigCode, "ea_code": calculateEA})] 3752SN/A for iop in iops: 3762SN/A header_output += MicroLdStOpDeclare.subst(iop) 3772SN/A decoder_output += MicroLdStOpConstructor.subst(iop) 3782680Sktlim@umich.edu exec_output += MicroLoadExecute.subst(iop) 3792SN/A exec_output += MicroLoadInitiateAcc.subst(iop) 3802455SN/A exec_output += MicroLoadCompleteAcc.subst(iop) 3812680Sktlim@umich.edu 3822SN/A base = LdStOp 3832455SN/A if big: 3842680Sktlim@umich.edu base = BigLdStOp 3852SN/A class LoadOp(base): 3862455SN/A def __init__(self, data, segment, addr, disp = 0, 3872680Sktlim@umich.edu dataSize="env.dataSize", 3882455SN/A addressSize="env.addressSize", 3892455SN/A atCPL0=False, prefetch=False): 3902680Sktlim@umich.edu super(LoadOp, self).__init__(data, segment, addr, 3912SN/A disp, dataSize, addressSize, mem_flags, 3922SN/A atCPL0, prefetch) 3932680Sktlim@umich.edu self.className = Name 3942SN/A self.mnemonic = name 3952455SN/A 3962680Sktlim@umich.edu microopClasses[name] = LoadOp 3972SN/A 3982455SN/A defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);', 3992680Sktlim@umich.edu 'Data = Mem & mask(dataSize * 8);') 4002SN/A defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);', 4012455SN/A 'Data = Mem & mask(dataSize * 8);', 4022680Sktlim@umich.edu '(StoreCheck << FlagShift)') 4032455SN/A defineMicroLoadOp('Ldstl', 'Data = merge(Data, Mem, dataSize);', 4042455SN/A 'Data = Mem & mask(dataSize * 8);', 4052680Sktlim@umich.edu '(StoreCheck << FlagShift) | Request::LOCKED') 4062SN/A defineMicroLoadOp('Ldfp', 'FpData.uqw = Mem;', big = False) 4072680Sktlim@umich.edu 4082SN/A def defineMicroStoreOp(mnemonic, code, \ 4092680Sktlim@umich.edu postCode="", completeCode="", mem_flags="0"): 4102206SN/A global header_output 4112680Sktlim@umich.edu global decoder_output 4122252SN/A global exec_output 4132680Sktlim@umich.edu global microopClasses 4142SN/A Name = mnemonic 4152680Sktlim@umich.edu name = mnemonic.lower() 4162447SN/A 4172680Sktlim@umich.edu # Build up the all register version of this micro op 4182447SN/A iop = InstObjParams(name, Name, 'X86ISA::LdStOp', 4195260Sksewell@umich.edu {"code": code, 4205260Sksewell@umich.edu "post_code": postCode, 4215260Sksewell@umich.edu "complete_code": completeCode, 4225260Sksewell@umich.edu "ea_code": calculateEA}) 4235260Sksewell@umich.edu header_output += MicroLdStOpDeclare.subst(iop) 4245260Sksewell@umich.edu decoder_output += MicroLdStOpConstructor.subst(iop) 4255592Sgblack@eecs.umich.edu exec_output += MicroStoreExecute.subst(iop) 4265260Sksewell@umich.edu exec_output += MicroStoreInitiateAcc.subst(iop) 4274172Ssaidi@eecs.umich.edu exec_output += MicroStoreCompleteAcc.subst(iop) 4284172Ssaidi@eecs.umich.edu 4294172Ssaidi@eecs.umich.edu class StoreOp(LdStOp): 4302159SN/A def __init__(self, data, segment, addr, disp = 0, 4312680Sktlim@umich.edu dataSize="env.dataSize", 4322SN/A addressSize="env.addressSize", 4334172Ssaidi@eecs.umich.edu atCPL0=False): 4344172Ssaidi@eecs.umich.edu super(StoreOp, self).__init__(data, segment, addr, 4352SN/A disp, dataSize, addressSize, mem_flags, atCPL0, False) 4363468Sgblack@eecs.umich.edu self.className = Name 4372680Sktlim@umich.edu self.mnemonic = name 4382SN/A 4392190SN/A microopClasses[name] = StoreOp 4402680Sktlim@umich.edu 4412190SN/A defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);') 4422190SN/A defineMicroStoreOp('Stul', 'Mem = pick(Data, 2, dataSize);', 4432680Sktlim@umich.edu mem_flags="Request::LOCKED") 4442SN/A defineMicroStoreOp('Stfp', 'Mem = FpData.uqw;') 4452190SN/A defineMicroStoreOp('Cda', 'Mem = 0;', mem_flags="Request::NO_ACCESS") 4462680Sktlim@umich.edu 4472190SN/A iop = InstObjParams("lea", "Lea", 'X86ISA::LdStOp', 4481858SN/A {"code": "Data = merge(Data, EA, dataSize);", 4492680Sktlim@umich.edu "ea_code": ''' 450360SN/A EA = bits(scale * Index + Base + disp, addressSize * 8 - 1, 0); 451360SN/A '''}) 4522190SN/A header_output += MicroLeaDeclare.subst(iop) 4532680Sktlim@umich.edu decoder_output += MicroLdStOpConstructor.subst(iop) 454360SN/A exec_output += MicroLeaExecute.subst(iop) 4551450SN/A 4562680Sktlim@umich.edu class LeaOp(LdStOp): 457360SN/A def __init__(self, data, segment, addr, disp = 0, 4584111Sgblack@eecs.umich.edu dataSize="env.dataSize", addressSize="env.addressSize"): 4594111Sgblack@eecs.umich.edu super(LeaOp, self).__init__(data, segment, 4604111Sgblack@eecs.umich.edu addr, disp, dataSize, addressSize, "0", False, False) 4612680Sktlim@umich.edu self.className = "Lea" 4622SN/A self.mnemonic = "lea" 4632SN/A 4642SN/A microopClasses["lea"] = LeaOp 4652190SN/A 466 467 iop = InstObjParams("tia", "Tia", 'X86ISA::LdStOp', 468 {"code": "xc->demapPage(EA, 0);", 469 "ea_code": calculateEA}) 470 header_output += MicroLeaDeclare.subst(iop) 471 decoder_output += MicroLdStOpConstructor.subst(iop) 472 exec_output += MicroLeaExecute.subst(iop) 473 474 class TiaOp(LdStOp): 475 def __init__(self, segment, addr, disp = 0, 476 dataSize="env.dataSize", 477 addressSize="env.addressSize"): 478 super(TiaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment, 479 addr, disp, dataSize, addressSize, "0", False, False) 480 self.className = "Tia" 481 self.mnemonic = "tia" 482 483 microopClasses["tia"] = TiaOp 484 485 class CdaOp(LdStOp): 486 def __init__(self, segment, addr, disp = 0, 487 dataSize="env.dataSize", 488 addressSize="env.addressSize", atCPL0=False): 489 super(CdaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment, 490 addr, disp, dataSize, addressSize, "Request::NO_ACCESS", 491 atCPL0, False) 492 self.className = "Cda" 493 self.mnemonic = "cda" 494 495 microopClasses["cda"] = CdaOp 496}}; 497 498