ldstop.isa revision 7967
17087Snate@binkert.org// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 27087Snate@binkert.org// All rights reserved. 37087Snate@binkert.org// 47087Snate@binkert.org// The license below extends only to copyright in the software and shall 57087Snate@binkert.org// not be construed as granting a license to any other intellectual 67087Snate@binkert.org// property including but not limited to intellectual property relating 77087Snate@binkert.org// to a hardware implementation of the functionality of the software 87087Snate@binkert.org// licensed hereunder. You may use the software subject to the license 97087Snate@binkert.org// terms below provided that you ensure that this notice is replicated 107087Snate@binkert.org// unmodified and in its entirety in all distributions of the software, 117087Snate@binkert.org// modified or unmodified, in source code or in binary form. 127087Snate@binkert.org// 135359Sgblack@eecs.umich.edu// Copyright (c) 2008 The Regents of The University of Michigan 145359Sgblack@eecs.umich.edu// All rights reserved. 155359Sgblack@eecs.umich.edu// 165359Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 175359Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 185359Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 195359Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 205359Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 215359Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 225359Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 235359Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 245359Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 255359Sgblack@eecs.umich.edu// this software without specific prior written permission. 265359Sgblack@eecs.umich.edu// 275359Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 285359Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 295359Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 305359Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 315359Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 325359Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 335359Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 345359Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 355359Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 365359Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 375359Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 385359Sgblack@eecs.umich.edu// 395359Sgblack@eecs.umich.edu// Authors: Gabe Black 405359Sgblack@eecs.umich.edu 414561Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 424561Sgblack@eecs.umich.edu// 434561Sgblack@eecs.umich.edu// LdStOp Microop templates 444561Sgblack@eecs.umich.edu// 454561Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 464561Sgblack@eecs.umich.edu 474601Sgblack@eecs.umich.edu// LEA template 484601Sgblack@eecs.umich.edu 494601Sgblack@eecs.umich.edudef template MicroLeaExecute {{ 504601Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 514601Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 524601Sgblack@eecs.umich.edu { 534601Sgblack@eecs.umich.edu Fault fault = NoFault; 544601Sgblack@eecs.umich.edu Addr EA; 554601Sgblack@eecs.umich.edu 564601Sgblack@eecs.umich.edu %(op_decl)s; 574601Sgblack@eecs.umich.edu %(op_rd)s; 584601Sgblack@eecs.umich.edu %(ea_code)s; 594601Sgblack@eecs.umich.edu DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); 604601Sgblack@eecs.umich.edu 614601Sgblack@eecs.umich.edu %(code)s; 624601Sgblack@eecs.umich.edu if(fault == NoFault) 634601Sgblack@eecs.umich.edu { 644601Sgblack@eecs.umich.edu %(op_wb)s; 654601Sgblack@eecs.umich.edu } 664601Sgblack@eecs.umich.edu 674601Sgblack@eecs.umich.edu return fault; 684601Sgblack@eecs.umich.edu } 694601Sgblack@eecs.umich.edu}}; 704601Sgblack@eecs.umich.edu 714601Sgblack@eecs.umich.edudef template MicroLeaDeclare {{ 724601Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 734601Sgblack@eecs.umich.edu { 744601Sgblack@eecs.umich.edu public: 754601Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 767620Sgblack@eecs.umich.edu const char * instMnem, uint64_t setFlags, 776345Sgblack@eecs.umich.edu uint8_t _scale, InstRegIndex _index, InstRegIndex _base, 786345Sgblack@eecs.umich.edu uint64_t _disp, InstRegIndex _segment, 796345Sgblack@eecs.umich.edu InstRegIndex _data, 805912Sgblack@eecs.umich.edu uint8_t _dataSize, uint8_t _addressSize, 815912Sgblack@eecs.umich.edu Request::FlagsType _memFlags); 824601Sgblack@eecs.umich.edu 834601Sgblack@eecs.umich.edu %(BasicExecDeclare)s 844601Sgblack@eecs.umich.edu }; 854601Sgblack@eecs.umich.edu}}; 864601Sgblack@eecs.umich.edu 874601Sgblack@eecs.umich.edu// Load templates 884601Sgblack@eecs.umich.edu 894587Sgblack@eecs.umich.edudef template MicroLoadExecute {{ 904587Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, 914587Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 924587Sgblack@eecs.umich.edu { 934587Sgblack@eecs.umich.edu Fault fault = NoFault; 944587Sgblack@eecs.umich.edu Addr EA; 954587Sgblack@eecs.umich.edu 964587Sgblack@eecs.umich.edu %(op_decl)s; 974587Sgblack@eecs.umich.edu %(op_rd)s; 984587Sgblack@eecs.umich.edu %(ea_code)s; 994587Sgblack@eecs.umich.edu DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); 1004587Sgblack@eecs.umich.edu 1015912Sgblack@eecs.umich.edu fault = read(xc, EA, Mem, memFlags); 1024720Sgblack@eecs.umich.edu 1035920Sgblack@eecs.umich.edu if (fault == NoFault) { 1044587Sgblack@eecs.umich.edu %(code)s; 1056736Sgblack@eecs.umich.edu } else if (memFlags & Request::PREFETCH) { 1065920Sgblack@eecs.umich.edu // For prefetches, ignore any faults/exceptions. 1075920Sgblack@eecs.umich.edu return NoFault; 1084587Sgblack@eecs.umich.edu } 1094587Sgblack@eecs.umich.edu if(fault == NoFault) 1104587Sgblack@eecs.umich.edu { 1114587Sgblack@eecs.umich.edu %(op_wb)s; 1124587Sgblack@eecs.umich.edu } 1134587Sgblack@eecs.umich.edu 1144587Sgblack@eecs.umich.edu return fault; 1154587Sgblack@eecs.umich.edu } 1164587Sgblack@eecs.umich.edu}}; 1174587Sgblack@eecs.umich.edu 1184587Sgblack@eecs.umich.edudef template MicroLoadInitiateAcc {{ 1194587Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 1204587Sgblack@eecs.umich.edu Trace::InstRecord * traceData) const 1214587Sgblack@eecs.umich.edu { 1224587Sgblack@eecs.umich.edu Fault fault = NoFault; 1234587Sgblack@eecs.umich.edu Addr EA; 1244587Sgblack@eecs.umich.edu 1254587Sgblack@eecs.umich.edu %(op_decl)s; 1264587Sgblack@eecs.umich.edu %(op_rd)s; 1274587Sgblack@eecs.umich.edu %(ea_code)s; 1284587Sgblack@eecs.umich.edu DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); 1294587Sgblack@eecs.umich.edu 1305912Sgblack@eecs.umich.edu fault = read(xc, EA, Mem, memFlags); 1314587Sgblack@eecs.umich.edu 1324587Sgblack@eecs.umich.edu return fault; 1334587Sgblack@eecs.umich.edu } 1344587Sgblack@eecs.umich.edu}}; 1354587Sgblack@eecs.umich.edu 1364587Sgblack@eecs.umich.edudef template MicroLoadCompleteAcc {{ 1374587Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 1384587Sgblack@eecs.umich.edu %(CPU_exec_context)s * xc, 1394587Sgblack@eecs.umich.edu Trace::InstRecord * traceData) const 1404587Sgblack@eecs.umich.edu { 1414587Sgblack@eecs.umich.edu Fault fault = NoFault; 1424587Sgblack@eecs.umich.edu 1434587Sgblack@eecs.umich.edu %(op_decl)s; 1444587Sgblack@eecs.umich.edu %(op_rd)s; 1454587Sgblack@eecs.umich.edu 1465727Sgblack@eecs.umich.edu Mem = get(pkt); 1475002Sgblack@eecs.umich.edu 1484587Sgblack@eecs.umich.edu %(code)s; 1494587Sgblack@eecs.umich.edu 1504587Sgblack@eecs.umich.edu if(fault == NoFault) 1514587Sgblack@eecs.umich.edu { 1524587Sgblack@eecs.umich.edu %(op_wb)s; 1534587Sgblack@eecs.umich.edu } 1544587Sgblack@eecs.umich.edu 1554587Sgblack@eecs.umich.edu return fault; 1564587Sgblack@eecs.umich.edu } 1574587Sgblack@eecs.umich.edu}}; 1584587Sgblack@eecs.umich.edu 1594587Sgblack@eecs.umich.edu// Store templates 1604587Sgblack@eecs.umich.edu 1614587Sgblack@eecs.umich.edudef template MicroStoreExecute {{ 1624587Sgblack@eecs.umich.edu Fault %(class_name)s::execute(%(CPU_exec_context)s * xc, 1634587Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1644587Sgblack@eecs.umich.edu { 1654587Sgblack@eecs.umich.edu Fault fault = NoFault; 1664587Sgblack@eecs.umich.edu 1674587Sgblack@eecs.umich.edu Addr EA; 1684587Sgblack@eecs.umich.edu %(op_decl)s; 1694587Sgblack@eecs.umich.edu %(op_rd)s; 1704587Sgblack@eecs.umich.edu %(ea_code)s; 1714587Sgblack@eecs.umich.edu DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); 1724587Sgblack@eecs.umich.edu 1734587Sgblack@eecs.umich.edu %(code)s; 1744587Sgblack@eecs.umich.edu 1754587Sgblack@eecs.umich.edu if(fault == NoFault) 1764587Sgblack@eecs.umich.edu { 1775912Sgblack@eecs.umich.edu fault = write(xc, Mem, EA, memFlags); 1784767Sgblack@eecs.umich.edu if(fault == NoFault) 1794720Sgblack@eecs.umich.edu { 1805892Sgblack@eecs.umich.edu %(post_code)s; 1814767Sgblack@eecs.umich.edu %(op_wb)s; 1824720Sgblack@eecs.umich.edu } 1834587Sgblack@eecs.umich.edu } 1844587Sgblack@eecs.umich.edu 1854587Sgblack@eecs.umich.edu return fault; 1864587Sgblack@eecs.umich.edu } 1874587Sgblack@eecs.umich.edu}}; 1884587Sgblack@eecs.umich.edu 1894587Sgblack@eecs.umich.edudef template MicroStoreInitiateAcc {{ 1904587Sgblack@eecs.umich.edu Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc, 1914587Sgblack@eecs.umich.edu Trace::InstRecord * traceData) const 1924587Sgblack@eecs.umich.edu { 1934587Sgblack@eecs.umich.edu Fault fault = NoFault; 1944587Sgblack@eecs.umich.edu 1954587Sgblack@eecs.umich.edu Addr EA; 1964587Sgblack@eecs.umich.edu %(op_decl)s; 1974587Sgblack@eecs.umich.edu %(op_rd)s; 1984587Sgblack@eecs.umich.edu %(ea_code)s; 1994587Sgblack@eecs.umich.edu DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); 2004587Sgblack@eecs.umich.edu 2014587Sgblack@eecs.umich.edu %(code)s; 2024587Sgblack@eecs.umich.edu 2034587Sgblack@eecs.umich.edu if(fault == NoFault) 2044587Sgblack@eecs.umich.edu { 2055912Sgblack@eecs.umich.edu write(xc, Mem, EA, memFlags); 2064587Sgblack@eecs.umich.edu } 2074587Sgblack@eecs.umich.edu return fault; 2084587Sgblack@eecs.umich.edu } 2094587Sgblack@eecs.umich.edu}}; 2104587Sgblack@eecs.umich.edu 2114587Sgblack@eecs.umich.edudef template MicroStoreCompleteAcc {{ 2125892Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 2135892Sgblack@eecs.umich.edu %(CPU_exec_context)s * xc, Trace::InstRecord * traceData) const 2144587Sgblack@eecs.umich.edu { 2155892Sgblack@eecs.umich.edu %(op_decl)s; 2165892Sgblack@eecs.umich.edu %(op_rd)s; 2175892Sgblack@eecs.umich.edu %(complete_code)s; 2185892Sgblack@eecs.umich.edu %(op_wb)s; 2194587Sgblack@eecs.umich.edu return NoFault; 2204587Sgblack@eecs.umich.edu } 2214587Sgblack@eecs.umich.edu}}; 2224587Sgblack@eecs.umich.edu 2234587Sgblack@eecs.umich.edu// Common templates 2244587Sgblack@eecs.umich.edu 2254587Sgblack@eecs.umich.edu//This delcares the initiateAcc function in memory operations 2264587Sgblack@eecs.umich.edudef template InitiateAccDeclare {{ 2274587Sgblack@eecs.umich.edu Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 2284587Sgblack@eecs.umich.edu}}; 2294587Sgblack@eecs.umich.edu 2304587Sgblack@eecs.umich.edu//This declares the completeAcc function in memory operations 2314587Sgblack@eecs.umich.edudef template CompleteAccDeclare {{ 2324587Sgblack@eecs.umich.edu Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 2334587Sgblack@eecs.umich.edu}}; 2344587Sgblack@eecs.umich.edu 2354587Sgblack@eecs.umich.edudef template MicroLdStOpDeclare {{ 2364587Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 2374587Sgblack@eecs.umich.edu { 2384561Sgblack@eecs.umich.edu public: 2394561Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 2407620Sgblack@eecs.umich.edu const char * instMnem, uint64_t setFlags, 2416345Sgblack@eecs.umich.edu uint8_t _scale, InstRegIndex _index, InstRegIndex _base, 2426345Sgblack@eecs.umich.edu uint64_t _disp, InstRegIndex _segment, 2436345Sgblack@eecs.umich.edu InstRegIndex _data, 2445912Sgblack@eecs.umich.edu uint8_t _dataSize, uint8_t _addressSize, 2455912Sgblack@eecs.umich.edu Request::FlagsType _memFlags); 2464561Sgblack@eecs.umich.edu 2474561Sgblack@eecs.umich.edu %(BasicExecDeclare)s 2484587Sgblack@eecs.umich.edu 2494587Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 2504587Sgblack@eecs.umich.edu 2514587Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 2524561Sgblack@eecs.umich.edu }; 2534561Sgblack@eecs.umich.edu}}; 2544561Sgblack@eecs.umich.edu 2554561Sgblack@eecs.umich.edudef template MicroLdStOpConstructor {{ 2564561Sgblack@eecs.umich.edu inline %(class_name)s::%(class_name)s( 2577620Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, uint64_t setFlags, 2586345Sgblack@eecs.umich.edu uint8_t _scale, InstRegIndex _index, InstRegIndex _base, 2596345Sgblack@eecs.umich.edu uint64_t _disp, InstRegIndex _segment, 2606345Sgblack@eecs.umich.edu InstRegIndex _data, 2615912Sgblack@eecs.umich.edu uint8_t _dataSize, uint8_t _addressSize, 2625912Sgblack@eecs.umich.edu Request::FlagsType _memFlags) : 2637620Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags, 2644587Sgblack@eecs.umich.edu _scale, _index, _base, 2654587Sgblack@eecs.umich.edu _disp, _segment, _data, 2665912Sgblack@eecs.umich.edu _dataSize, _addressSize, _memFlags, %(op_class)s) 2674561Sgblack@eecs.umich.edu { 2687626Sgblack@eecs.umich.edu %(constructor)s; 2694561Sgblack@eecs.umich.edu } 2704561Sgblack@eecs.umich.edu}}; 2714561Sgblack@eecs.umich.edu 2724587Sgblack@eecs.umich.edulet {{ 2734587Sgblack@eecs.umich.edu class LdStOp(X86Microop): 2745912Sgblack@eecs.umich.edu def __init__(self, data, segment, addr, disp, 2755920Sgblack@eecs.umich.edu dataSize, addressSize, baseFlags, atCPL0, prefetch): 2764587Sgblack@eecs.umich.edu self.data = data 2774587Sgblack@eecs.umich.edu [self.scale, self.index, self.base] = addr 2784587Sgblack@eecs.umich.edu self.disp = disp 2794587Sgblack@eecs.umich.edu self.segment = segment 2804712Sgblack@eecs.umich.edu self.dataSize = dataSize 2815149Sgblack@eecs.umich.edu self.addressSize = addressSize 2825912Sgblack@eecs.umich.edu self.memFlags = baseFlags 2835912Sgblack@eecs.umich.edu if atCPL0: 2845912Sgblack@eecs.umich.edu self.memFlags += " | (CPL0FlagBit << FlagShift)" 2855920Sgblack@eecs.umich.edu if prefetch: 2866736Sgblack@eecs.umich.edu self.memFlags += " | Request::PREFETCH" 2875965Sgblack@eecs.umich.edu self.memFlags += " | (machInst.legacy.addr ? " + \ 2885965Sgblack@eecs.umich.edu "(AddrSizeFlagBit << FlagShift) : 0)" 2894587Sgblack@eecs.umich.edu 2907620Sgblack@eecs.umich.edu def getAllocator(self, microFlags): 2917620Sgblack@eecs.umich.edu allocator = '''new %(class_name)s(machInst, macrocodeBlock, 2924587Sgblack@eecs.umich.edu %(flags)s, %(scale)s, %(index)s, %(base)s, 2934587Sgblack@eecs.umich.edu %(disp)s, %(segment)s, %(data)s, 2945912Sgblack@eecs.umich.edu %(dataSize)s, %(addressSize)s, %(memFlags)s)''' % { 2954587Sgblack@eecs.umich.edu "class_name" : self.className, 2964587Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 2974587Sgblack@eecs.umich.edu "scale" : self.scale, "index" : self.index, 2984587Sgblack@eecs.umich.edu "base" : self.base, 2994587Sgblack@eecs.umich.edu "disp" : self.disp, 3004587Sgblack@eecs.umich.edu "segment" : self.segment, "data" : self.data, 3015912Sgblack@eecs.umich.edu "dataSize" : self.dataSize, "addressSize" : self.addressSize, 3025912Sgblack@eecs.umich.edu "memFlags" : self.memFlags} 3034587Sgblack@eecs.umich.edu return allocator 3047967Sgblack@eecs.umich.edu 3057967Sgblack@eecs.umich.edu class BigLdStOp(X86Microop): 3067967Sgblack@eecs.umich.edu def __init__(self, data, segment, addr, disp, 3077967Sgblack@eecs.umich.edu dataSize, addressSize, baseFlags, atCPL0, prefetch): 3087967Sgblack@eecs.umich.edu self.data = data 3097967Sgblack@eecs.umich.edu [self.scale, self.index, self.base] = addr 3107967Sgblack@eecs.umich.edu self.disp = disp 3117967Sgblack@eecs.umich.edu self.segment = segment 3127967Sgblack@eecs.umich.edu self.dataSize = dataSize 3137967Sgblack@eecs.umich.edu self.addressSize = addressSize 3147967Sgblack@eecs.umich.edu self.memFlags = baseFlags 3157967Sgblack@eecs.umich.edu if atCPL0: 3167967Sgblack@eecs.umich.edu self.memFlags += " | (CPL0FlagBit << FlagShift)" 3177967Sgblack@eecs.umich.edu if prefetch: 3187967Sgblack@eecs.umich.edu self.memFlags += " | Request::PREFETCH" 3197967Sgblack@eecs.umich.edu self.memFlags += " | (machInst.legacy.addr ? " + \ 3207967Sgblack@eecs.umich.edu "(AddrSizeFlagBit << FlagShift) : 0)" 3217967Sgblack@eecs.umich.edu 3227967Sgblack@eecs.umich.edu def getAllocator(self, microFlags): 3237967Sgblack@eecs.umich.edu allocString = ''' 3247967Sgblack@eecs.umich.edu (%(dataSize)s >= 4) ? 3257967Sgblack@eecs.umich.edu (StaticInstPtr)(new %(class_name)sBig(machInst, 3267967Sgblack@eecs.umich.edu macrocodeBlock, %(flags)s, %(scale)s, %(index)s, 3277967Sgblack@eecs.umich.edu %(base)s, %(disp)s, %(segment)s, %(data)s, 3287967Sgblack@eecs.umich.edu %(dataSize)s, %(addressSize)s, %(memFlags)s)) : 3297967Sgblack@eecs.umich.edu (StaticInstPtr)(new %(class_name)s(machInst, 3307967Sgblack@eecs.umich.edu macrocodeBlock, %(flags)s, %(scale)s, %(index)s, 3317967Sgblack@eecs.umich.edu %(base)s, %(disp)s, %(segment)s, %(data)s, 3327967Sgblack@eecs.umich.edu %(dataSize)s, %(addressSize)s, %(memFlags)s)) 3337967Sgblack@eecs.umich.edu ''' 3347967Sgblack@eecs.umich.edu allocator = allocString % { 3357967Sgblack@eecs.umich.edu "class_name" : self.className, 3367967Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags), 3377967Sgblack@eecs.umich.edu "scale" : self.scale, "index" : self.index, 3387967Sgblack@eecs.umich.edu "base" : self.base, 3397967Sgblack@eecs.umich.edu "disp" : self.disp, 3407967Sgblack@eecs.umich.edu "segment" : self.segment, "data" : self.data, 3417967Sgblack@eecs.umich.edu "dataSize" : self.dataSize, "addressSize" : self.addressSize, 3427967Sgblack@eecs.umich.edu "memFlags" : self.memFlags} 3437967Sgblack@eecs.umich.edu return allocator 3444587Sgblack@eecs.umich.edu}}; 3454587Sgblack@eecs.umich.edu 3464587Sgblack@eecs.umich.edulet {{ 3474587Sgblack@eecs.umich.edu 3484587Sgblack@eecs.umich.edu # Make these empty strings so that concatenating onto 3494587Sgblack@eecs.umich.edu # them will always work. 3504587Sgblack@eecs.umich.edu header_output = "" 3514587Sgblack@eecs.umich.edu decoder_output = "" 3524587Sgblack@eecs.umich.edu exec_output = "" 3534587Sgblack@eecs.umich.edu 3545969Sgblack@eecs.umich.edu calculateEA = ''' 3555969Sgblack@eecs.umich.edu EA = bits(SegBase + scale * Index + Base + disp, addressSize * 8 - 1, 0); 3565969Sgblack@eecs.umich.edu ''' 3574587Sgblack@eecs.umich.edu 3587967Sgblack@eecs.umich.edu def defineMicroLoadOp(mnemonic, code, bigCode='', 3597967Sgblack@eecs.umich.edu mem_flags="0", big=True): 3604587Sgblack@eecs.umich.edu global header_output 3614587Sgblack@eecs.umich.edu global decoder_output 3624587Sgblack@eecs.umich.edu global exec_output 3634587Sgblack@eecs.umich.edu global microopClasses 3644587Sgblack@eecs.umich.edu Name = mnemonic 3654587Sgblack@eecs.umich.edu name = mnemonic.lower() 3664587Sgblack@eecs.umich.edu 3674587Sgblack@eecs.umich.edu # Build up the all register version of this micro op 3687967Sgblack@eecs.umich.edu iops = [InstObjParams(name, Name, 'X86ISA::LdStOp', 3697967Sgblack@eecs.umich.edu {"code": code, "ea_code": calculateEA})] 3707967Sgblack@eecs.umich.edu if big: 3717967Sgblack@eecs.umich.edu iops += [InstObjParams(name, Name + "Big", 'X86ISA::LdStOp', 3727967Sgblack@eecs.umich.edu {"code": bigCode, "ea_code": calculateEA})] 3737967Sgblack@eecs.umich.edu for iop in iops: 3747967Sgblack@eecs.umich.edu header_output += MicroLdStOpDeclare.subst(iop) 3757967Sgblack@eecs.umich.edu decoder_output += MicroLdStOpConstructor.subst(iop) 3767967Sgblack@eecs.umich.edu exec_output += MicroLoadExecute.subst(iop) 3777967Sgblack@eecs.umich.edu exec_output += MicroLoadInitiateAcc.subst(iop) 3787967Sgblack@eecs.umich.edu exec_output += MicroLoadCompleteAcc.subst(iop) 3794587Sgblack@eecs.umich.edu 3807967Sgblack@eecs.umich.edu base = LdStOp 3817967Sgblack@eecs.umich.edu if big: 3827967Sgblack@eecs.umich.edu base = BigLdStOp 3837967Sgblack@eecs.umich.edu class LoadOp(base): 3845149Sgblack@eecs.umich.edu def __init__(self, data, segment, addr, disp = 0, 3855912Sgblack@eecs.umich.edu dataSize="env.dataSize", 3865912Sgblack@eecs.umich.edu addressSize="env.addressSize", 3875920Sgblack@eecs.umich.edu atCPL0=False, prefetch=False): 3885912Sgblack@eecs.umich.edu super(LoadOp, self).__init__(data, segment, addr, 3895920Sgblack@eecs.umich.edu disp, dataSize, addressSize, mem_flags, 3905920Sgblack@eecs.umich.edu atCPL0, prefetch) 3914587Sgblack@eecs.umich.edu self.className = Name 3924587Sgblack@eecs.umich.edu self.mnemonic = name 3934587Sgblack@eecs.umich.edu 3944587Sgblack@eecs.umich.edu microopClasses[name] = LoadOp 3954587Sgblack@eecs.umich.edu 3967967Sgblack@eecs.umich.edu defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);', 3977967Sgblack@eecs.umich.edu 'Data = Mem & mask(dataSize * 8);') 3985912Sgblack@eecs.umich.edu defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);', 3997967Sgblack@eecs.umich.edu 'Data = Mem & mask(dataSize * 8);', 4007967Sgblack@eecs.umich.edu '(StoreCheck << FlagShift)') 4016079Sgblack@eecs.umich.edu defineMicroLoadOp('Ldstl', 'Data = merge(Data, Mem, dataSize);', 4027967Sgblack@eecs.umich.edu 'Data = Mem & mask(dataSize * 8);', 4037967Sgblack@eecs.umich.edu '(StoreCheck << FlagShift) | Request::LOCKED') 4047967Sgblack@eecs.umich.edu defineMicroLoadOp('Ldfp', 'FpData.uqw = Mem;', big = False) 4054587Sgblack@eecs.umich.edu 4065892Sgblack@eecs.umich.edu def defineMicroStoreOp(mnemonic, code, \ 4075965Sgblack@eecs.umich.edu postCode="", completeCode="", mem_flags="0"): 4084587Sgblack@eecs.umich.edu global header_output 4094587Sgblack@eecs.umich.edu global decoder_output 4104587Sgblack@eecs.umich.edu global exec_output 4114587Sgblack@eecs.umich.edu global microopClasses 4124587Sgblack@eecs.umich.edu Name = mnemonic 4134587Sgblack@eecs.umich.edu name = mnemonic.lower() 4144587Sgblack@eecs.umich.edu 4154587Sgblack@eecs.umich.edu # Build up the all register version of this micro op 4164679Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'X86ISA::LdStOp', 4175118Sgblack@eecs.umich.edu {"code": code, 4185892Sgblack@eecs.umich.edu "post_code": postCode, 4195892Sgblack@eecs.umich.edu "complete_code": completeCode, 4205912Sgblack@eecs.umich.edu "ea_code": calculateEA}) 4214587Sgblack@eecs.umich.edu header_output += MicroLdStOpDeclare.subst(iop) 4224587Sgblack@eecs.umich.edu decoder_output += MicroLdStOpConstructor.subst(iop) 4234587Sgblack@eecs.umich.edu exec_output += MicroStoreExecute.subst(iop) 4244587Sgblack@eecs.umich.edu exec_output += MicroStoreInitiateAcc.subst(iop) 4254587Sgblack@eecs.umich.edu exec_output += MicroStoreCompleteAcc.subst(iop) 4264587Sgblack@eecs.umich.edu 4274587Sgblack@eecs.umich.edu class StoreOp(LdStOp): 4285149Sgblack@eecs.umich.edu def __init__(self, data, segment, addr, disp = 0, 4295912Sgblack@eecs.umich.edu dataSize="env.dataSize", 4305912Sgblack@eecs.umich.edu addressSize="env.addressSize", 4315912Sgblack@eecs.umich.edu atCPL0=False): 4325912Sgblack@eecs.umich.edu super(StoreOp, self).__init__(data, segment, addr, 4335920Sgblack@eecs.umich.edu disp, dataSize, addressSize, mem_flags, atCPL0, False) 4344587Sgblack@eecs.umich.edu self.className = Name 4354587Sgblack@eecs.umich.edu self.mnemonic = name 4364587Sgblack@eecs.umich.edu 4374587Sgblack@eecs.umich.edu microopClasses[name] = StoreOp 4384587Sgblack@eecs.umich.edu 4395919Sgblack@eecs.umich.edu defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);') 4406080Sgblack@eecs.umich.edu defineMicroStoreOp('Stul', 'Mem = pick(Data, 2, dataSize);', 4416080Sgblack@eecs.umich.edu mem_flags="Request::LOCKED") 4425027Sgblack@eecs.umich.edu defineMicroStoreOp('Stfp', 'Mem = FpData.uqw;') 4435892Sgblack@eecs.umich.edu defineMicroStoreOp('Cda', 'Mem = 0;', mem_flags="Request::NO_ACCESS") 4444601Sgblack@eecs.umich.edu 4454679Sgblack@eecs.umich.edu iop = InstObjParams("lea", "Lea", 'X86ISA::LdStOp', 4465118Sgblack@eecs.umich.edu {"code": "Data = merge(Data, EA, dataSize);", 4476056Sgblack@eecs.umich.edu "ea_code": ''' 4486056Sgblack@eecs.umich.edu EA = bits(scale * Index + Base + disp, addressSize * 8 - 1, 0); 4496056Sgblack@eecs.umich.edu '''}) 4504601Sgblack@eecs.umich.edu header_output += MicroLeaDeclare.subst(iop) 4514601Sgblack@eecs.umich.edu decoder_output += MicroLdStOpConstructor.subst(iop) 4524601Sgblack@eecs.umich.edu exec_output += MicroLeaExecute.subst(iop) 4534601Sgblack@eecs.umich.edu 4544601Sgblack@eecs.umich.edu class LeaOp(LdStOp): 4555149Sgblack@eecs.umich.edu def __init__(self, data, segment, addr, disp = 0, 4565149Sgblack@eecs.umich.edu dataSize="env.dataSize", addressSize="env.addressSize"): 4574712Sgblack@eecs.umich.edu super(LeaOp, self).__init__(data, segment, 4585920Sgblack@eecs.umich.edu addr, disp, dataSize, addressSize, "0", False, False) 4594601Sgblack@eecs.umich.edu self.className = "Lea" 4604601Sgblack@eecs.umich.edu self.mnemonic = "lea" 4614601Sgblack@eecs.umich.edu 4624601Sgblack@eecs.umich.edu microopClasses["lea"] = LeaOp 4635178Sgblack@eecs.umich.edu 4645178Sgblack@eecs.umich.edu 4655359Sgblack@eecs.umich.edu iop = InstObjParams("tia", "Tia", 'X86ISA::LdStOp', 4665359Sgblack@eecs.umich.edu {"code": "xc->demapPage(EA, 0);", 4675912Sgblack@eecs.umich.edu "ea_code": calculateEA}) 4685359Sgblack@eecs.umich.edu header_output += MicroLeaDeclare.subst(iop) 4695359Sgblack@eecs.umich.edu decoder_output += MicroLdStOpConstructor.subst(iop) 4705359Sgblack@eecs.umich.edu exec_output += MicroLeaExecute.subst(iop) 4715359Sgblack@eecs.umich.edu 4725359Sgblack@eecs.umich.edu class TiaOp(LdStOp): 4735359Sgblack@eecs.umich.edu def __init__(self, segment, addr, disp = 0, 4745912Sgblack@eecs.umich.edu dataSize="env.dataSize", 4755912Sgblack@eecs.umich.edu addressSize="env.addressSize"): 4766345Sgblack@eecs.umich.edu super(TiaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment, 4775920Sgblack@eecs.umich.edu addr, disp, dataSize, addressSize, "0", False, False) 4785359Sgblack@eecs.umich.edu self.className = "Tia" 4795359Sgblack@eecs.umich.edu self.mnemonic = "tia" 4805359Sgblack@eecs.umich.edu 4815359Sgblack@eecs.umich.edu microopClasses["tia"] = TiaOp 4825359Sgblack@eecs.umich.edu 4835178Sgblack@eecs.umich.edu class CdaOp(LdStOp): 4845178Sgblack@eecs.umich.edu def __init__(self, segment, addr, disp = 0, 4855912Sgblack@eecs.umich.edu dataSize="env.dataSize", 4865912Sgblack@eecs.umich.edu addressSize="env.addressSize", atCPL0=False): 4876345Sgblack@eecs.umich.edu super(CdaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment, 4886624Sgblack@eecs.umich.edu addr, disp, dataSize, addressSize, "Request::NO_ACCESS", 4896624Sgblack@eecs.umich.edu atCPL0, False) 4905178Sgblack@eecs.umich.edu self.className = "Cda" 4915178Sgblack@eecs.umich.edu self.mnemonic = "cda" 4925178Sgblack@eecs.umich.edu 4935178Sgblack@eecs.umich.edu microopClasses["cda"] = CdaOp 4944587Sgblack@eecs.umich.edu}}; 4954587Sgblack@eecs.umich.edu 496