ldstop.isa revision 11329
17087Snate@binkert.org// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 211329Salexandru.dutu@amd.com// Copyright (c) 2015 Advanced Micro Devices, Inc. 37087Snate@binkert.org// All rights reserved. 47087Snate@binkert.org// 57087Snate@binkert.org// The license below extends only to copyright in the software and shall 67087Snate@binkert.org// not be construed as granting a license to any other intellectual 77087Snate@binkert.org// property including but not limited to intellectual property relating 87087Snate@binkert.org// to a hardware implementation of the functionality of the software 97087Snate@binkert.org// licensed hereunder. You may use the software subject to the license 107087Snate@binkert.org// terms below provided that you ensure that this notice is replicated 117087Snate@binkert.org// unmodified and in its entirety in all distributions of the software, 127087Snate@binkert.org// modified or unmodified, in source code or in binary form. 137087Snate@binkert.org// 145359Sgblack@eecs.umich.edu// Copyright (c) 2008 The Regents of The University of Michigan 155359Sgblack@eecs.umich.edu// All rights reserved. 165359Sgblack@eecs.umich.edu// 175359Sgblack@eecs.umich.edu// Redistribution and use in source and binary forms, with or without 185359Sgblack@eecs.umich.edu// modification, are permitted provided that the following conditions are 195359Sgblack@eecs.umich.edu// met: redistributions of source code must retain the above copyright 205359Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer; 215359Sgblack@eecs.umich.edu// redistributions in binary form must reproduce the above copyright 225359Sgblack@eecs.umich.edu// notice, this list of conditions and the following disclaimer in the 235359Sgblack@eecs.umich.edu// documentation and/or other materials provided with the distribution; 245359Sgblack@eecs.umich.edu// neither the name of the copyright holders nor the names of its 255359Sgblack@eecs.umich.edu// contributors may be used to endorse or promote products derived from 265359Sgblack@eecs.umich.edu// this software without specific prior written permission. 275359Sgblack@eecs.umich.edu// 285359Sgblack@eecs.umich.edu// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 295359Sgblack@eecs.umich.edu// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 305359Sgblack@eecs.umich.edu// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 315359Sgblack@eecs.umich.edu// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 325359Sgblack@eecs.umich.edu// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 335359Sgblack@eecs.umich.edu// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 345359Sgblack@eecs.umich.edu// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 355359Sgblack@eecs.umich.edu// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 365359Sgblack@eecs.umich.edu// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 375359Sgblack@eecs.umich.edu// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 385359Sgblack@eecs.umich.edu// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 395359Sgblack@eecs.umich.edu// 405359Sgblack@eecs.umich.edu// Authors: Gabe Black 415359Sgblack@eecs.umich.edu 424561Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 434561Sgblack@eecs.umich.edu// 444561Sgblack@eecs.umich.edu// LdStOp Microop templates 454561Sgblack@eecs.umich.edu// 464561Sgblack@eecs.umich.edu////////////////////////////////////////////////////////////////////////// 474561Sgblack@eecs.umich.edu 484601Sgblack@eecs.umich.edu// LEA template 494601Sgblack@eecs.umich.edu 504601Sgblack@eecs.umich.edudef template MicroLeaExecute {{ 5110196SCurtis.Dunham@arm.com Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, 524601Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 534601Sgblack@eecs.umich.edu { 544601Sgblack@eecs.umich.edu Fault fault = NoFault; 554601Sgblack@eecs.umich.edu Addr EA; 564601Sgblack@eecs.umich.edu 574601Sgblack@eecs.umich.edu %(op_decl)s; 584601Sgblack@eecs.umich.edu %(op_rd)s; 594601Sgblack@eecs.umich.edu %(ea_code)s; 604601Sgblack@eecs.umich.edu DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); 614601Sgblack@eecs.umich.edu 624601Sgblack@eecs.umich.edu %(code)s; 634601Sgblack@eecs.umich.edu if(fault == NoFault) 644601Sgblack@eecs.umich.edu { 654601Sgblack@eecs.umich.edu %(op_wb)s; 664601Sgblack@eecs.umich.edu } 674601Sgblack@eecs.umich.edu 684601Sgblack@eecs.umich.edu return fault; 694601Sgblack@eecs.umich.edu } 704601Sgblack@eecs.umich.edu}}; 714601Sgblack@eecs.umich.edu 724601Sgblack@eecs.umich.edudef template MicroLeaDeclare {{ 734601Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 744601Sgblack@eecs.umich.edu { 754601Sgblack@eecs.umich.edu public: 764601Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 777620Sgblack@eecs.umich.edu const char * instMnem, uint64_t setFlags, 786345Sgblack@eecs.umich.edu uint8_t _scale, InstRegIndex _index, InstRegIndex _base, 796345Sgblack@eecs.umich.edu uint64_t _disp, InstRegIndex _segment, 806345Sgblack@eecs.umich.edu InstRegIndex _data, 815912Sgblack@eecs.umich.edu uint8_t _dataSize, uint8_t _addressSize, 825912Sgblack@eecs.umich.edu Request::FlagsType _memFlags); 834601Sgblack@eecs.umich.edu 844601Sgblack@eecs.umich.edu %(BasicExecDeclare)s 854601Sgblack@eecs.umich.edu }; 864601Sgblack@eecs.umich.edu}}; 874601Sgblack@eecs.umich.edu 884601Sgblack@eecs.umich.edu// Load templates 894601Sgblack@eecs.umich.edu 904587Sgblack@eecs.umich.edudef template MicroLoadExecute {{ 9110196SCurtis.Dunham@arm.com Fault %(class_name)s::execute(CPU_EXEC_CONTEXT *xc, 924587Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 934587Sgblack@eecs.umich.edu { 944587Sgblack@eecs.umich.edu Fault fault = NoFault; 954587Sgblack@eecs.umich.edu Addr EA; 964587Sgblack@eecs.umich.edu 974587Sgblack@eecs.umich.edu %(op_decl)s; 984587Sgblack@eecs.umich.edu %(op_rd)s; 994587Sgblack@eecs.umich.edu %(ea_code)s; 1004587Sgblack@eecs.umich.edu DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); 1014587Sgblack@eecs.umich.edu 10211329Salexandru.dutu@amd.com fault = readMemAtomic(xc, traceData, EA, Mem, 10311329Salexandru.dutu@amd.com %(memDataSize)s, memFlags); 1044720Sgblack@eecs.umich.edu 1055920Sgblack@eecs.umich.edu if (fault == NoFault) { 1064587Sgblack@eecs.umich.edu %(code)s; 1076736Sgblack@eecs.umich.edu } else if (memFlags & Request::PREFETCH) { 1085920Sgblack@eecs.umich.edu // For prefetches, ignore any faults/exceptions. 1095920Sgblack@eecs.umich.edu return NoFault; 1104587Sgblack@eecs.umich.edu } 1114587Sgblack@eecs.umich.edu if(fault == NoFault) 1124587Sgblack@eecs.umich.edu { 1134587Sgblack@eecs.umich.edu %(op_wb)s; 1144587Sgblack@eecs.umich.edu } 1154587Sgblack@eecs.umich.edu 1164587Sgblack@eecs.umich.edu return fault; 1174587Sgblack@eecs.umich.edu } 1184587Sgblack@eecs.umich.edu}}; 1194587Sgblack@eecs.umich.edu 1204587Sgblack@eecs.umich.edudef template MicroLoadInitiateAcc {{ 12110196SCurtis.Dunham@arm.com Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT * xc, 1224587Sgblack@eecs.umich.edu Trace::InstRecord * traceData) const 1234587Sgblack@eecs.umich.edu { 1244587Sgblack@eecs.umich.edu Fault fault = NoFault; 1254587Sgblack@eecs.umich.edu Addr EA; 1264587Sgblack@eecs.umich.edu 1274587Sgblack@eecs.umich.edu %(op_decl)s; 1284587Sgblack@eecs.umich.edu %(op_rd)s; 1294587Sgblack@eecs.umich.edu %(ea_code)s; 1304587Sgblack@eecs.umich.edu DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); 1314587Sgblack@eecs.umich.edu 13211329Salexandru.dutu@amd.com fault = initiateMemRead(xc, traceData, EA, 13311329Salexandru.dutu@amd.com %(memDataSize)s, memFlags); 1344587Sgblack@eecs.umich.edu 1354587Sgblack@eecs.umich.edu return fault; 1364587Sgblack@eecs.umich.edu } 1374587Sgblack@eecs.umich.edu}}; 1384587Sgblack@eecs.umich.edu 1394587Sgblack@eecs.umich.edudef template MicroLoadCompleteAcc {{ 1404587Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 14110196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT * xc, 1424587Sgblack@eecs.umich.edu Trace::InstRecord * traceData) const 1434587Sgblack@eecs.umich.edu { 1444587Sgblack@eecs.umich.edu Fault fault = NoFault; 1454587Sgblack@eecs.umich.edu 1464587Sgblack@eecs.umich.edu %(op_decl)s; 1474587Sgblack@eecs.umich.edu %(op_rd)s; 1484587Sgblack@eecs.umich.edu 14911329Salexandru.dutu@amd.com getMem(pkt, Mem, %(memDataSize)s, traceData); 1505002Sgblack@eecs.umich.edu 1514587Sgblack@eecs.umich.edu %(code)s; 1524587Sgblack@eecs.umich.edu 1534587Sgblack@eecs.umich.edu if(fault == NoFault) 1544587Sgblack@eecs.umich.edu { 1554587Sgblack@eecs.umich.edu %(op_wb)s; 1564587Sgblack@eecs.umich.edu } 1574587Sgblack@eecs.umich.edu 1584587Sgblack@eecs.umich.edu return fault; 1594587Sgblack@eecs.umich.edu } 1604587Sgblack@eecs.umich.edu}}; 1614587Sgblack@eecs.umich.edu 1624587Sgblack@eecs.umich.edu// Store templates 1634587Sgblack@eecs.umich.edu 1644587Sgblack@eecs.umich.edudef template MicroStoreExecute {{ 16510196SCurtis.Dunham@arm.com Fault %(class_name)s::execute(CPU_EXEC_CONTEXT * xc, 1664587Sgblack@eecs.umich.edu Trace::InstRecord *traceData) const 1674587Sgblack@eecs.umich.edu { 1684587Sgblack@eecs.umich.edu Fault fault = NoFault; 1694587Sgblack@eecs.umich.edu 1704587Sgblack@eecs.umich.edu Addr EA; 1714587Sgblack@eecs.umich.edu %(op_decl)s; 1724587Sgblack@eecs.umich.edu %(op_rd)s; 1734587Sgblack@eecs.umich.edu %(ea_code)s; 1744587Sgblack@eecs.umich.edu DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); 1754587Sgblack@eecs.umich.edu 1764587Sgblack@eecs.umich.edu %(code)s; 1774587Sgblack@eecs.umich.edu 1784587Sgblack@eecs.umich.edu if(fault == NoFault) 1794587Sgblack@eecs.umich.edu { 18011329Salexandru.dutu@amd.com fault = writeMemAtomic(xc, traceData, Mem, %(memDataSize)s, EA, 1818442Sgblack@eecs.umich.edu memFlags, NULL); 1824767Sgblack@eecs.umich.edu if(fault == NoFault) 1834720Sgblack@eecs.umich.edu { 1844767Sgblack@eecs.umich.edu %(op_wb)s; 1854720Sgblack@eecs.umich.edu } 1864587Sgblack@eecs.umich.edu } 1874587Sgblack@eecs.umich.edu 1884587Sgblack@eecs.umich.edu return fault; 1894587Sgblack@eecs.umich.edu } 1904587Sgblack@eecs.umich.edu}}; 1914587Sgblack@eecs.umich.edu 1924587Sgblack@eecs.umich.edudef template MicroStoreInitiateAcc {{ 19310196SCurtis.Dunham@arm.com Fault %(class_name)s::initiateAcc(CPU_EXEC_CONTEXT * xc, 1944587Sgblack@eecs.umich.edu Trace::InstRecord * traceData) const 1954587Sgblack@eecs.umich.edu { 1964587Sgblack@eecs.umich.edu Fault fault = NoFault; 1974587Sgblack@eecs.umich.edu 1984587Sgblack@eecs.umich.edu Addr EA; 1994587Sgblack@eecs.umich.edu %(op_decl)s; 2004587Sgblack@eecs.umich.edu %(op_rd)s; 2014587Sgblack@eecs.umich.edu %(ea_code)s; 2024587Sgblack@eecs.umich.edu DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA); 2034587Sgblack@eecs.umich.edu 2044587Sgblack@eecs.umich.edu %(code)s; 2054587Sgblack@eecs.umich.edu 2064587Sgblack@eecs.umich.edu if(fault == NoFault) 2074587Sgblack@eecs.umich.edu { 20811329Salexandru.dutu@amd.com fault = writeMemTiming(xc, traceData, Mem, %(memDataSize)s, EA, 2098442Sgblack@eecs.umich.edu memFlags, NULL); 2104587Sgblack@eecs.umich.edu } 2114587Sgblack@eecs.umich.edu return fault; 2124587Sgblack@eecs.umich.edu } 2134587Sgblack@eecs.umich.edu}}; 2144587Sgblack@eecs.umich.edu 2154587Sgblack@eecs.umich.edudef template MicroStoreCompleteAcc {{ 2165892Sgblack@eecs.umich.edu Fault %(class_name)s::completeAcc(PacketPtr pkt, 21710196SCurtis.Dunham@arm.com CPU_EXEC_CONTEXT * xc, Trace::InstRecord * traceData) const 2184587Sgblack@eecs.umich.edu { 2195892Sgblack@eecs.umich.edu %(op_decl)s; 2205892Sgblack@eecs.umich.edu %(op_rd)s; 2215892Sgblack@eecs.umich.edu %(complete_code)s; 2225892Sgblack@eecs.umich.edu %(op_wb)s; 2234587Sgblack@eecs.umich.edu return NoFault; 2244587Sgblack@eecs.umich.edu } 2254587Sgblack@eecs.umich.edu}}; 2264587Sgblack@eecs.umich.edu 2274587Sgblack@eecs.umich.edu// Common templates 2284587Sgblack@eecs.umich.edu 2294587Sgblack@eecs.umich.edu//This delcares the initiateAcc function in memory operations 2304587Sgblack@eecs.umich.edudef template InitiateAccDeclare {{ 2314587Sgblack@eecs.umich.edu Fault initiateAcc(%(CPU_exec_context)s *, Trace::InstRecord *) const; 2324587Sgblack@eecs.umich.edu}}; 2334587Sgblack@eecs.umich.edu 2344587Sgblack@eecs.umich.edu//This declares the completeAcc function in memory operations 2354587Sgblack@eecs.umich.edudef template CompleteAccDeclare {{ 2364587Sgblack@eecs.umich.edu Fault completeAcc(PacketPtr, %(CPU_exec_context)s *, Trace::InstRecord *) const; 2374587Sgblack@eecs.umich.edu}}; 2384587Sgblack@eecs.umich.edu 2394587Sgblack@eecs.umich.edudef template MicroLdStOpDeclare {{ 2404587Sgblack@eecs.umich.edu class %(class_name)s : public %(base_class)s 2414587Sgblack@eecs.umich.edu { 2424561Sgblack@eecs.umich.edu public: 2434561Sgblack@eecs.umich.edu %(class_name)s(ExtMachInst _machInst, 2447620Sgblack@eecs.umich.edu const char * instMnem, uint64_t setFlags, 2456345Sgblack@eecs.umich.edu uint8_t _scale, InstRegIndex _index, InstRegIndex _base, 2466345Sgblack@eecs.umich.edu uint64_t _disp, InstRegIndex _segment, 2476345Sgblack@eecs.umich.edu InstRegIndex _data, 2485912Sgblack@eecs.umich.edu uint8_t _dataSize, uint8_t _addressSize, 2495912Sgblack@eecs.umich.edu Request::FlagsType _memFlags); 2504561Sgblack@eecs.umich.edu 2514561Sgblack@eecs.umich.edu %(BasicExecDeclare)s 2524587Sgblack@eecs.umich.edu 2534587Sgblack@eecs.umich.edu %(InitiateAccDeclare)s 2544587Sgblack@eecs.umich.edu 2554587Sgblack@eecs.umich.edu %(CompleteAccDeclare)s 2564561Sgblack@eecs.umich.edu }; 2574561Sgblack@eecs.umich.edu}}; 2584561Sgblack@eecs.umich.edu 25911329Salexandru.dutu@amd.com// LdStSplitOp is a load or store that uses a pair of regs as the 26011329Salexandru.dutu@amd.com// source or destination. Used for cmpxchg{8,16}b. 26111329Salexandru.dutu@amd.comdef template MicroLdStSplitOpDeclare {{ 26211329Salexandru.dutu@amd.com class %(class_name)s : public %(base_class)s 26311329Salexandru.dutu@amd.com { 26411329Salexandru.dutu@amd.com public: 26511329Salexandru.dutu@amd.com %(class_name)s(ExtMachInst _machInst, 26611329Salexandru.dutu@amd.com const char * instMnem, uint64_t setFlags, 26711329Salexandru.dutu@amd.com uint8_t _scale, InstRegIndex _index, InstRegIndex _base, 26811329Salexandru.dutu@amd.com uint64_t _disp, InstRegIndex _segment, 26911329Salexandru.dutu@amd.com InstRegIndex _dataLow, InstRegIndex _dataHi, 27011329Salexandru.dutu@amd.com uint8_t _dataSize, uint8_t _addressSize, 27111329Salexandru.dutu@amd.com Request::FlagsType _memFlags); 27211329Salexandru.dutu@amd.com 27311329Salexandru.dutu@amd.com %(BasicExecDeclare)s 27411329Salexandru.dutu@amd.com 27511329Salexandru.dutu@amd.com %(InitiateAccDeclare)s 27611329Salexandru.dutu@amd.com 27711329Salexandru.dutu@amd.com %(CompleteAccDeclare)s 27811329Salexandru.dutu@amd.com }; 27911329Salexandru.dutu@amd.com}}; 28011329Salexandru.dutu@amd.com 2814561Sgblack@eecs.umich.edudef template MicroLdStOpConstructor {{ 28210184SCurtis.Dunham@arm.com %(class_name)s::%(class_name)s( 2837620Sgblack@eecs.umich.edu ExtMachInst machInst, const char * instMnem, uint64_t setFlags, 2846345Sgblack@eecs.umich.edu uint8_t _scale, InstRegIndex _index, InstRegIndex _base, 2856345Sgblack@eecs.umich.edu uint64_t _disp, InstRegIndex _segment, 2866345Sgblack@eecs.umich.edu InstRegIndex _data, 2875912Sgblack@eecs.umich.edu uint8_t _dataSize, uint8_t _addressSize, 2885912Sgblack@eecs.umich.edu Request::FlagsType _memFlags) : 2897620Sgblack@eecs.umich.edu %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags, 2904587Sgblack@eecs.umich.edu _scale, _index, _base, 2914587Sgblack@eecs.umich.edu _disp, _segment, _data, 2925912Sgblack@eecs.umich.edu _dataSize, _addressSize, _memFlags, %(op_class)s) 2934561Sgblack@eecs.umich.edu { 2947626Sgblack@eecs.umich.edu %(constructor)s; 2954561Sgblack@eecs.umich.edu } 2964561Sgblack@eecs.umich.edu}}; 2974561Sgblack@eecs.umich.edu 29811329Salexandru.dutu@amd.comdef template MicroLdStSplitOpConstructor {{ 29911329Salexandru.dutu@amd.com %(class_name)s::%(class_name)s( 30011329Salexandru.dutu@amd.com ExtMachInst machInst, const char * instMnem, uint64_t setFlags, 30111329Salexandru.dutu@amd.com uint8_t _scale, InstRegIndex _index, InstRegIndex _base, 30211329Salexandru.dutu@amd.com uint64_t _disp, InstRegIndex _segment, 30311329Salexandru.dutu@amd.com InstRegIndex _dataLow, InstRegIndex _dataHi, 30411329Salexandru.dutu@amd.com uint8_t _dataSize, uint8_t _addressSize, 30511329Salexandru.dutu@amd.com Request::FlagsType _memFlags) : 30611329Salexandru.dutu@amd.com %(base_class)s(machInst, "%(mnemonic)s", instMnem, setFlags, 30711329Salexandru.dutu@amd.com _scale, _index, _base, 30811329Salexandru.dutu@amd.com _disp, _segment, _dataLow, _dataHi, 30911329Salexandru.dutu@amd.com _dataSize, _addressSize, _memFlags, %(op_class)s) 31011329Salexandru.dutu@amd.com { 31111329Salexandru.dutu@amd.com %(constructor)s; 31211329Salexandru.dutu@amd.com } 31311329Salexandru.dutu@amd.com}}; 31411329Salexandru.dutu@amd.com 3154587Sgblack@eecs.umich.edulet {{ 3164587Sgblack@eecs.umich.edu class LdStOp(X86Microop): 3175912Sgblack@eecs.umich.edu def __init__(self, data, segment, addr, disp, 3188103Sgblack@eecs.umich.edu dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec): 3194587Sgblack@eecs.umich.edu self.data = data 3204587Sgblack@eecs.umich.edu [self.scale, self.index, self.base] = addr 3214587Sgblack@eecs.umich.edu self.disp = disp 3224587Sgblack@eecs.umich.edu self.segment = segment 3234712Sgblack@eecs.umich.edu self.dataSize = dataSize 3245149Sgblack@eecs.umich.edu self.addressSize = addressSize 3255912Sgblack@eecs.umich.edu self.memFlags = baseFlags 3265912Sgblack@eecs.umich.edu if atCPL0: 3275912Sgblack@eecs.umich.edu self.memFlags += " | (CPL0FlagBit << FlagShift)" 3288102Sgblack@eecs.umich.edu self.instFlags = "" 3295920Sgblack@eecs.umich.edu if prefetch: 3306736Sgblack@eecs.umich.edu self.memFlags += " | Request::PREFETCH" 3318103Sgblack@eecs.umich.edu self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)" 3328103Sgblack@eecs.umich.edu if nonSpec: 3338103Sgblack@eecs.umich.edu self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)" 3345965Sgblack@eecs.umich.edu self.memFlags += " | (machInst.legacy.addr ? " + \ 3355965Sgblack@eecs.umich.edu "(AddrSizeFlagBit << FlagShift) : 0)" 3364587Sgblack@eecs.umich.edu 3377620Sgblack@eecs.umich.edu def getAllocator(self, microFlags): 3387620Sgblack@eecs.umich.edu allocator = '''new %(class_name)s(machInst, macrocodeBlock, 3394587Sgblack@eecs.umich.edu %(flags)s, %(scale)s, %(index)s, %(base)s, 3404587Sgblack@eecs.umich.edu %(disp)s, %(segment)s, %(data)s, 3415912Sgblack@eecs.umich.edu %(dataSize)s, %(addressSize)s, %(memFlags)s)''' % { 3424587Sgblack@eecs.umich.edu "class_name" : self.className, 3438102Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags) + self.instFlags, 3444587Sgblack@eecs.umich.edu "scale" : self.scale, "index" : self.index, 3454587Sgblack@eecs.umich.edu "base" : self.base, 3464587Sgblack@eecs.umich.edu "disp" : self.disp, 3474587Sgblack@eecs.umich.edu "segment" : self.segment, "data" : self.data, 3485912Sgblack@eecs.umich.edu "dataSize" : self.dataSize, "addressSize" : self.addressSize, 3495912Sgblack@eecs.umich.edu "memFlags" : self.memFlags} 3504587Sgblack@eecs.umich.edu return allocator 3517967Sgblack@eecs.umich.edu 3527967Sgblack@eecs.umich.edu class BigLdStOp(X86Microop): 3537967Sgblack@eecs.umich.edu def __init__(self, data, segment, addr, disp, 3548103Sgblack@eecs.umich.edu dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec): 3557967Sgblack@eecs.umich.edu self.data = data 3567967Sgblack@eecs.umich.edu [self.scale, self.index, self.base] = addr 3577967Sgblack@eecs.umich.edu self.disp = disp 3587967Sgblack@eecs.umich.edu self.segment = segment 3597967Sgblack@eecs.umich.edu self.dataSize = dataSize 3607967Sgblack@eecs.umich.edu self.addressSize = addressSize 3617967Sgblack@eecs.umich.edu self.memFlags = baseFlags 3627967Sgblack@eecs.umich.edu if atCPL0: 3637967Sgblack@eecs.umich.edu self.memFlags += " | (CPL0FlagBit << FlagShift)" 3648103Sgblack@eecs.umich.edu self.instFlags = "" 3657967Sgblack@eecs.umich.edu if prefetch: 3667967Sgblack@eecs.umich.edu self.memFlags += " | Request::PREFETCH" 3678103Sgblack@eecs.umich.edu self.instFlags += " | (1ULL << StaticInst::IsDataPrefetch)" 3688103Sgblack@eecs.umich.edu if nonSpec: 3698103Sgblack@eecs.umich.edu self.instFlags += " | (1ULL << StaticInst::IsNonSpeculative)" 3707967Sgblack@eecs.umich.edu self.memFlags += " | (machInst.legacy.addr ? " + \ 3717967Sgblack@eecs.umich.edu "(AddrSizeFlagBit << FlagShift) : 0)" 3727967Sgblack@eecs.umich.edu 3737967Sgblack@eecs.umich.edu def getAllocator(self, microFlags): 3747967Sgblack@eecs.umich.edu allocString = ''' 3757967Sgblack@eecs.umich.edu (%(dataSize)s >= 4) ? 3767967Sgblack@eecs.umich.edu (StaticInstPtr)(new %(class_name)sBig(machInst, 3777967Sgblack@eecs.umich.edu macrocodeBlock, %(flags)s, %(scale)s, %(index)s, 3787967Sgblack@eecs.umich.edu %(base)s, %(disp)s, %(segment)s, %(data)s, 3797967Sgblack@eecs.umich.edu %(dataSize)s, %(addressSize)s, %(memFlags)s)) : 3807967Sgblack@eecs.umich.edu (StaticInstPtr)(new %(class_name)s(machInst, 3817967Sgblack@eecs.umich.edu macrocodeBlock, %(flags)s, %(scale)s, %(index)s, 3827967Sgblack@eecs.umich.edu %(base)s, %(disp)s, %(segment)s, %(data)s, 3837967Sgblack@eecs.umich.edu %(dataSize)s, %(addressSize)s, %(memFlags)s)) 3847967Sgblack@eecs.umich.edu ''' 3857967Sgblack@eecs.umich.edu allocator = allocString % { 3867967Sgblack@eecs.umich.edu "class_name" : self.className, 3878103Sgblack@eecs.umich.edu "flags" : self.microFlagsText(microFlags) + self.instFlags, 3887967Sgblack@eecs.umich.edu "scale" : self.scale, "index" : self.index, 3897967Sgblack@eecs.umich.edu "base" : self.base, 3907967Sgblack@eecs.umich.edu "disp" : self.disp, 3917967Sgblack@eecs.umich.edu "segment" : self.segment, "data" : self.data, 3927967Sgblack@eecs.umich.edu "dataSize" : self.dataSize, "addressSize" : self.addressSize, 3937967Sgblack@eecs.umich.edu "memFlags" : self.memFlags} 3947967Sgblack@eecs.umich.edu return allocator 39511329Salexandru.dutu@amd.com 39611329Salexandru.dutu@amd.com class LdStSplitOp(LdStOp): 39711329Salexandru.dutu@amd.com def __init__(self, data, segment, addr, disp, 39811329Salexandru.dutu@amd.com dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec): 39911329Salexandru.dutu@amd.com super(LdStSplitOp, self).__init__(0, segment, addr, disp, 40011329Salexandru.dutu@amd.com dataSize, addressSize, baseFlags, atCPL0, prefetch, nonSpec) 40111329Salexandru.dutu@amd.com (self.dataLow, self.dataHi) = data 40211329Salexandru.dutu@amd.com 40311329Salexandru.dutu@amd.com def getAllocator(self, microFlags): 40411329Salexandru.dutu@amd.com allocString = '''(StaticInstPtr)(new %(class_name)s(machInst, 40511329Salexandru.dutu@amd.com macrocodeBlock, %(flags)s, %(scale)s, %(index)s, 40611329Salexandru.dutu@amd.com %(base)s, %(disp)s, %(segment)s, 40711329Salexandru.dutu@amd.com %(dataLow)s, %(dataHi)s, 40811329Salexandru.dutu@amd.com %(dataSize)s, %(addressSize)s, %(memFlags)s)) 40911329Salexandru.dutu@amd.com ''' 41011329Salexandru.dutu@amd.com allocator = allocString % { 41111329Salexandru.dutu@amd.com "class_name" : self.className, 41211329Salexandru.dutu@amd.com "flags" : self.microFlagsText(microFlags) + self.instFlags, 41311329Salexandru.dutu@amd.com "scale" : self.scale, "index" : self.index, 41411329Salexandru.dutu@amd.com "base" : self.base, 41511329Salexandru.dutu@amd.com "disp" : self.disp, 41611329Salexandru.dutu@amd.com "segment" : self.segment, 41711329Salexandru.dutu@amd.com "dataLow" : self.dataLow, "dataHi" : self.dataHi, 41811329Salexandru.dutu@amd.com "dataSize" : self.dataSize, "addressSize" : self.addressSize, 41911329Salexandru.dutu@amd.com "memFlags" : self.memFlags} 42011329Salexandru.dutu@amd.com return allocator 42111329Salexandru.dutu@amd.com 4224587Sgblack@eecs.umich.edu}}; 4234587Sgblack@eecs.umich.edu 4244587Sgblack@eecs.umich.edulet {{ 4254587Sgblack@eecs.umich.edu 4264587Sgblack@eecs.umich.edu # Make these empty strings so that concatenating onto 4274587Sgblack@eecs.umich.edu # them will always work. 4284587Sgblack@eecs.umich.edu header_output = "" 4294587Sgblack@eecs.umich.edu decoder_output = "" 4304587Sgblack@eecs.umich.edu exec_output = "" 4314587Sgblack@eecs.umich.edu 43211329Salexandru.dutu@amd.com segmentEAExpr = \ 43311329Salexandru.dutu@amd.com 'bits(scale * Index + Base + disp, addressSize * 8 - 1, 0);' 43411329Salexandru.dutu@amd.com 43511329Salexandru.dutu@amd.com calculateEA = 'EA = SegBase + ' + segmentEAExpr 4364587Sgblack@eecs.umich.edu 4377967Sgblack@eecs.umich.edu def defineMicroLoadOp(mnemonic, code, bigCode='', 43811329Salexandru.dutu@amd.com mem_flags="0", big=True, nonSpec=False): 4394587Sgblack@eecs.umich.edu global header_output 4404587Sgblack@eecs.umich.edu global decoder_output 4414587Sgblack@eecs.umich.edu global exec_output 4424587Sgblack@eecs.umich.edu global microopClasses 4434587Sgblack@eecs.umich.edu Name = mnemonic 4444587Sgblack@eecs.umich.edu name = mnemonic.lower() 4454587Sgblack@eecs.umich.edu 4464587Sgblack@eecs.umich.edu # Build up the all register version of this micro op 4477967Sgblack@eecs.umich.edu iops = [InstObjParams(name, Name, 'X86ISA::LdStOp', 44811329Salexandru.dutu@amd.com { "code": code, 44911329Salexandru.dutu@amd.com "ea_code": calculateEA, 45011329Salexandru.dutu@amd.com "memDataSize": "dataSize" })] 4517967Sgblack@eecs.umich.edu if big: 4527967Sgblack@eecs.umich.edu iops += [InstObjParams(name, Name + "Big", 'X86ISA::LdStOp', 45311329Salexandru.dutu@amd.com { "code": bigCode, 45411329Salexandru.dutu@amd.com "ea_code": calculateEA, 45511329Salexandru.dutu@amd.com "memDataSize": "dataSize" })] 4567967Sgblack@eecs.umich.edu for iop in iops: 4577967Sgblack@eecs.umich.edu header_output += MicroLdStOpDeclare.subst(iop) 4587967Sgblack@eecs.umich.edu decoder_output += MicroLdStOpConstructor.subst(iop) 4597967Sgblack@eecs.umich.edu exec_output += MicroLoadExecute.subst(iop) 4607967Sgblack@eecs.umich.edu exec_output += MicroLoadInitiateAcc.subst(iop) 4617967Sgblack@eecs.umich.edu exec_output += MicroLoadCompleteAcc.subst(iop) 4624587Sgblack@eecs.umich.edu 4637967Sgblack@eecs.umich.edu base = LdStOp 4647967Sgblack@eecs.umich.edu if big: 4657967Sgblack@eecs.umich.edu base = BigLdStOp 4667967Sgblack@eecs.umich.edu class LoadOp(base): 4675149Sgblack@eecs.umich.edu def __init__(self, data, segment, addr, disp = 0, 4685912Sgblack@eecs.umich.edu dataSize="env.dataSize", 4695912Sgblack@eecs.umich.edu addressSize="env.addressSize", 47011329Salexandru.dutu@amd.com atCPL0=False, prefetch=False, nonSpec=nonSpec): 4715912Sgblack@eecs.umich.edu super(LoadOp, self).__init__(data, segment, addr, 4725920Sgblack@eecs.umich.edu disp, dataSize, addressSize, mem_flags, 4738103Sgblack@eecs.umich.edu atCPL0, prefetch, nonSpec) 4744587Sgblack@eecs.umich.edu self.className = Name 4754587Sgblack@eecs.umich.edu self.mnemonic = name 4764587Sgblack@eecs.umich.edu 4774587Sgblack@eecs.umich.edu microopClasses[name] = LoadOp 4784587Sgblack@eecs.umich.edu 4797967Sgblack@eecs.umich.edu defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);', 4807967Sgblack@eecs.umich.edu 'Data = Mem & mask(dataSize * 8);') 4815912Sgblack@eecs.umich.edu defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);', 4827967Sgblack@eecs.umich.edu 'Data = Mem & mask(dataSize * 8);', 4837967Sgblack@eecs.umich.edu '(StoreCheck << FlagShift)') 4846079Sgblack@eecs.umich.edu defineMicroLoadOp('Ldstl', 'Data = merge(Data, Mem, dataSize);', 4857967Sgblack@eecs.umich.edu 'Data = Mem & mask(dataSize * 8);', 48611329Salexandru.dutu@amd.com '(StoreCheck << FlagShift) | Request::LOCKED_RMW', 48711329Salexandru.dutu@amd.com nonSpec=True) 4889894Sandreas@sandberg.pp.se 4899894Sandreas@sandberg.pp.se defineMicroLoadOp('Ldfp', code='FpData_uqw = Mem', big = False) 4909894Sandreas@sandberg.pp.se 4919894Sandreas@sandberg.pp.se defineMicroLoadOp('Ldfp87', code=''' 4929894Sandreas@sandberg.pp.se switch (dataSize) 4939894Sandreas@sandberg.pp.se { 4949894Sandreas@sandberg.pp.se case 4: 4959894Sandreas@sandberg.pp.se FpData_df = *(float *)&Mem; 4969894Sandreas@sandberg.pp.se break; 4979894Sandreas@sandberg.pp.se case 8: 4989894Sandreas@sandberg.pp.se FpData_df = *(double *)&Mem; 4999894Sandreas@sandberg.pp.se break; 5009894Sandreas@sandberg.pp.se default: 5019894Sandreas@sandberg.pp.se panic("Unhandled data size in LdFp87.\\n"); 5029894Sandreas@sandberg.pp.se } 5039894Sandreas@sandberg.pp.se ''', big = False) 5044587Sgblack@eecs.umich.edu 50511159Ssteve.reinhardt@amd.com # Load integer from memory into x87 top-of-stack register. 50611159Ssteve.reinhardt@amd.com # Used to implement fild instruction. 50711159Ssteve.reinhardt@amd.com defineMicroLoadOp('Ldifp87', code=''' 50811159Ssteve.reinhardt@amd.com switch (dataSize) 50911159Ssteve.reinhardt@amd.com { 51011159Ssteve.reinhardt@amd.com case 2: 51111159Ssteve.reinhardt@amd.com FpData_df = (int64_t)sext<16>(Mem); 51211159Ssteve.reinhardt@amd.com break; 51311159Ssteve.reinhardt@amd.com case 4: 51411159Ssteve.reinhardt@amd.com FpData_df = (int64_t)sext<32>(Mem); 51511159Ssteve.reinhardt@amd.com break; 51611159Ssteve.reinhardt@amd.com case 8: 51711159Ssteve.reinhardt@amd.com FpData_df = (int64_t)Mem; 51811159Ssteve.reinhardt@amd.com break; 51911159Ssteve.reinhardt@amd.com default: 52011159Ssteve.reinhardt@amd.com panic("Unhandled data size in LdIFp87.\\n"); 52111159Ssteve.reinhardt@amd.com } 52211159Ssteve.reinhardt@amd.com ''', big = False) 52311159Ssteve.reinhardt@amd.com 52411329Salexandru.dutu@amd.com def defineMicroLoadSplitOp(mnemonic, code, mem_flags="0", nonSpec=False): 52511329Salexandru.dutu@amd.com global header_output 52611329Salexandru.dutu@amd.com global decoder_output 52711329Salexandru.dutu@amd.com global exec_output 52811329Salexandru.dutu@amd.com global microopClasses 52911329Salexandru.dutu@amd.com Name = mnemonic 53011329Salexandru.dutu@amd.com name = mnemonic.lower() 53111329Salexandru.dutu@amd.com 53211329Salexandru.dutu@amd.com iop = InstObjParams(name, Name, 'X86ISA::LdStSplitOp', 53311329Salexandru.dutu@amd.com { "code": code, 53411329Salexandru.dutu@amd.com "ea_code": calculateEA, 53511329Salexandru.dutu@amd.com "memDataSize": "2 * dataSize" }) 53611329Salexandru.dutu@amd.com 53711329Salexandru.dutu@amd.com header_output += MicroLdStSplitOpDeclare.subst(iop) 53811329Salexandru.dutu@amd.com decoder_output += MicroLdStSplitOpConstructor.subst(iop) 53911329Salexandru.dutu@amd.com exec_output += MicroLoadExecute.subst(iop) 54011329Salexandru.dutu@amd.com exec_output += MicroLoadInitiateAcc.subst(iop) 54111329Salexandru.dutu@amd.com exec_output += MicroLoadCompleteAcc.subst(iop) 54211329Salexandru.dutu@amd.com 54311329Salexandru.dutu@amd.com class LoadOp(LdStSplitOp): 54411329Salexandru.dutu@amd.com def __init__(self, data, segment, addr, disp = 0, 54511329Salexandru.dutu@amd.com dataSize="env.dataSize", 54611329Salexandru.dutu@amd.com addressSize="env.addressSize", 54711329Salexandru.dutu@amd.com atCPL0=False, prefetch=False, nonSpec=nonSpec): 54811329Salexandru.dutu@amd.com super(LoadOp, self).__init__(data, segment, addr, 54911329Salexandru.dutu@amd.com disp, dataSize, addressSize, mem_flags, 55011329Salexandru.dutu@amd.com atCPL0, prefetch, nonSpec) 55111329Salexandru.dutu@amd.com self.className = Name 55211329Salexandru.dutu@amd.com self.mnemonic = name 55311329Salexandru.dutu@amd.com 55411329Salexandru.dutu@amd.com microopClasses[name] = LoadOp 55511329Salexandru.dutu@amd.com 55611329Salexandru.dutu@amd.com code = ''' 55711329Salexandru.dutu@amd.com switch (dataSize) { 55811329Salexandru.dutu@amd.com case 4: 55911329Salexandru.dutu@amd.com DataLow = bits(Mem_u2qw[0], 31, 0); 56011329Salexandru.dutu@amd.com DataHi = bits(Mem_u2qw[0], 63, 32); 56111329Salexandru.dutu@amd.com break; 56211329Salexandru.dutu@amd.com case 8: 56311329Salexandru.dutu@amd.com DataLow = Mem_u2qw[0]; 56411329Salexandru.dutu@amd.com DataHi = Mem_u2qw[1]; 56511329Salexandru.dutu@amd.com break; 56611329Salexandru.dutu@amd.com default: 56711329Salexandru.dutu@amd.com panic("Unhandled data size %d in LdSplit.\\n", dataSize); 56811329Salexandru.dutu@amd.com }''' 56911329Salexandru.dutu@amd.com 57011329Salexandru.dutu@amd.com defineMicroLoadSplitOp('LdSplit', code, 57111329Salexandru.dutu@amd.com '(StoreCheck << FlagShift)') 57211329Salexandru.dutu@amd.com 57311329Salexandru.dutu@amd.com defineMicroLoadSplitOp('LdSplitl', code, 57411329Salexandru.dutu@amd.com '(StoreCheck << FlagShift) | Request::LOCKED_RMW', 57511329Salexandru.dutu@amd.com nonSpec=True) 57611329Salexandru.dutu@amd.com 5778432Sgblack@eecs.umich.edu def defineMicroStoreOp(mnemonic, code, completeCode="", mem_flags="0"): 5784587Sgblack@eecs.umich.edu global header_output 5794587Sgblack@eecs.umich.edu global decoder_output 5804587Sgblack@eecs.umich.edu global exec_output 5814587Sgblack@eecs.umich.edu global microopClasses 5824587Sgblack@eecs.umich.edu Name = mnemonic 5834587Sgblack@eecs.umich.edu name = mnemonic.lower() 5844587Sgblack@eecs.umich.edu 5854587Sgblack@eecs.umich.edu # Build up the all register version of this micro op 5864679Sgblack@eecs.umich.edu iop = InstObjParams(name, Name, 'X86ISA::LdStOp', 58711329Salexandru.dutu@amd.com { "code": code, 58811329Salexandru.dutu@amd.com "complete_code": completeCode, 58911329Salexandru.dutu@amd.com "ea_code": calculateEA, 59011329Salexandru.dutu@amd.com "memDataSize": "dataSize" }) 5914587Sgblack@eecs.umich.edu header_output += MicroLdStOpDeclare.subst(iop) 5924587Sgblack@eecs.umich.edu decoder_output += MicroLdStOpConstructor.subst(iop) 5934587Sgblack@eecs.umich.edu exec_output += MicroStoreExecute.subst(iop) 5944587Sgblack@eecs.umich.edu exec_output += MicroStoreInitiateAcc.subst(iop) 5954587Sgblack@eecs.umich.edu exec_output += MicroStoreCompleteAcc.subst(iop) 5964587Sgblack@eecs.umich.edu 5974587Sgblack@eecs.umich.edu class StoreOp(LdStOp): 5985149Sgblack@eecs.umich.edu def __init__(self, data, segment, addr, disp = 0, 5995912Sgblack@eecs.umich.edu dataSize="env.dataSize", 6005912Sgblack@eecs.umich.edu addressSize="env.addressSize", 6018103Sgblack@eecs.umich.edu atCPL0=False, nonSpec=False): 6028103Sgblack@eecs.umich.edu super(StoreOp, self).__init__(data, segment, addr, disp, 6038103Sgblack@eecs.umich.edu dataSize, addressSize, mem_flags, atCPL0, False, 6048103Sgblack@eecs.umich.edu nonSpec) 6054587Sgblack@eecs.umich.edu self.className = Name 6064587Sgblack@eecs.umich.edu self.mnemonic = name 6074587Sgblack@eecs.umich.edu 6084587Sgblack@eecs.umich.edu microopClasses[name] = StoreOp 6094587Sgblack@eecs.umich.edu 6105919Sgblack@eecs.umich.edu defineMicroStoreOp('St', 'Mem = pick(Data, 2, dataSize);') 6116080Sgblack@eecs.umich.edu defineMicroStoreOp('Stul', 'Mem = pick(Data, 2, dataSize);', 61210760Ssteve.reinhardt@amd.com mem_flags="Request::LOCKED_RMW") 6139894Sandreas@sandberg.pp.se 6149894Sandreas@sandberg.pp.se defineMicroStoreOp('Stfp', code='Mem = FpData_uqw;') 6159894Sandreas@sandberg.pp.se 6169894Sandreas@sandberg.pp.se defineMicroStoreOp('Stfp87', code=''' 6179894Sandreas@sandberg.pp.se switch (dataSize) 6189894Sandreas@sandberg.pp.se { 6199894Sandreas@sandberg.pp.se case 4: { 6209894Sandreas@sandberg.pp.se float single(FpData_df); 6219894Sandreas@sandberg.pp.se Mem = *(uint32_t *)&single; 6229894Sandreas@sandberg.pp.se } break; 6239894Sandreas@sandberg.pp.se case 8: 6249894Sandreas@sandberg.pp.se Mem = *(uint64_t *)&FpData_df; 6259894Sandreas@sandberg.pp.se break; 6269894Sandreas@sandberg.pp.se default: 6279894Sandreas@sandberg.pp.se panic("Unhandled data size in StFp87.\\n"); 6289894Sandreas@sandberg.pp.se } 6299894Sandreas@sandberg.pp.se ''') 6309894Sandreas@sandberg.pp.se 6315892Sgblack@eecs.umich.edu defineMicroStoreOp('Cda', 'Mem = 0;', mem_flags="Request::NO_ACCESS") 6324601Sgblack@eecs.umich.edu 63311329Salexandru.dutu@amd.com def defineMicroStoreSplitOp(mnemonic, code, 63411329Salexandru.dutu@amd.com completeCode="", mem_flags="0"): 63511329Salexandru.dutu@amd.com global header_output 63611329Salexandru.dutu@amd.com global decoder_output 63711329Salexandru.dutu@amd.com global exec_output 63811329Salexandru.dutu@amd.com global microopClasses 63911329Salexandru.dutu@amd.com Name = mnemonic 64011329Salexandru.dutu@amd.com name = mnemonic.lower() 64111329Salexandru.dutu@amd.com 64211329Salexandru.dutu@amd.com iop = InstObjParams(name, Name, 'X86ISA::LdStSplitOp', 64311329Salexandru.dutu@amd.com { "code": code, 64411329Salexandru.dutu@amd.com "complete_code": completeCode, 64511329Salexandru.dutu@amd.com "ea_code": calculateEA, 64611329Salexandru.dutu@amd.com "memDataSize": "2 * dataSize" }) 64711329Salexandru.dutu@amd.com 64811329Salexandru.dutu@amd.com header_output += MicroLdStSplitOpDeclare.subst(iop) 64911329Salexandru.dutu@amd.com decoder_output += MicroLdStSplitOpConstructor.subst(iop) 65011329Salexandru.dutu@amd.com exec_output += MicroStoreExecute.subst(iop) 65111329Salexandru.dutu@amd.com exec_output += MicroStoreInitiateAcc.subst(iop) 65211329Salexandru.dutu@amd.com exec_output += MicroStoreCompleteAcc.subst(iop) 65311329Salexandru.dutu@amd.com 65411329Salexandru.dutu@amd.com class StoreOp(LdStSplitOp): 65511329Salexandru.dutu@amd.com def __init__(self, data, segment, addr, disp = 0, 65611329Salexandru.dutu@amd.com dataSize="env.dataSize", 65711329Salexandru.dutu@amd.com addressSize="env.addressSize", 65811329Salexandru.dutu@amd.com atCPL0=False, nonSpec=False): 65911329Salexandru.dutu@amd.com super(StoreOp, self).__init__(data, segment, addr, disp, 66011329Salexandru.dutu@amd.com dataSize, addressSize, mem_flags, atCPL0, False, 66111329Salexandru.dutu@amd.com nonSpec) 66211329Salexandru.dutu@amd.com self.className = Name 66311329Salexandru.dutu@amd.com self.mnemonic = name 66411329Salexandru.dutu@amd.com 66511329Salexandru.dutu@amd.com microopClasses[name] = StoreOp 66611329Salexandru.dutu@amd.com 66711329Salexandru.dutu@amd.com code = ''' 66811329Salexandru.dutu@amd.com switch (dataSize) { 66911329Salexandru.dutu@amd.com case 4: 67011329Salexandru.dutu@amd.com Mem_u2qw[0] = (DataHi << 32) | DataLow; 67111329Salexandru.dutu@amd.com break; 67211329Salexandru.dutu@amd.com case 8: 67311329Salexandru.dutu@amd.com Mem_u2qw[0] = DataLow; 67411329Salexandru.dutu@amd.com Mem_u2qw[1] = DataHi; 67511329Salexandru.dutu@amd.com break; 67611329Salexandru.dutu@amd.com default: 67711329Salexandru.dutu@amd.com panic("Unhandled data size %d in StSplit.\\n", dataSize); 67811329Salexandru.dutu@amd.com }''' 67911329Salexandru.dutu@amd.com 68011329Salexandru.dutu@amd.com defineMicroStoreSplitOp('StSplit', code); 68111329Salexandru.dutu@amd.com 68211329Salexandru.dutu@amd.com defineMicroStoreSplitOp('StSplitul', code, 68311329Salexandru.dutu@amd.com mem_flags='Request::LOCKED_RMW') 68411329Salexandru.dutu@amd.com 6854679Sgblack@eecs.umich.edu iop = InstObjParams("lea", "Lea", 'X86ISA::LdStOp', 68611329Salexandru.dutu@amd.com { "code": "Data = merge(Data, EA, dataSize);", 68711329Salexandru.dutu@amd.com "ea_code": "EA = " + segmentEAExpr, 68811329Salexandru.dutu@amd.com "memDataSize": "dataSize" }) 6894601Sgblack@eecs.umich.edu header_output += MicroLeaDeclare.subst(iop) 6904601Sgblack@eecs.umich.edu decoder_output += MicroLdStOpConstructor.subst(iop) 6914601Sgblack@eecs.umich.edu exec_output += MicroLeaExecute.subst(iop) 6924601Sgblack@eecs.umich.edu 6934601Sgblack@eecs.umich.edu class LeaOp(LdStOp): 6945149Sgblack@eecs.umich.edu def __init__(self, data, segment, addr, disp = 0, 6955149Sgblack@eecs.umich.edu dataSize="env.dataSize", addressSize="env.addressSize"): 6968103Sgblack@eecs.umich.edu super(LeaOp, self).__init__(data, segment, addr, disp, 6978103Sgblack@eecs.umich.edu dataSize, addressSize, "0", False, False, False) 6984601Sgblack@eecs.umich.edu self.className = "Lea" 6994601Sgblack@eecs.umich.edu self.mnemonic = "lea" 7004601Sgblack@eecs.umich.edu 7014601Sgblack@eecs.umich.edu microopClasses["lea"] = LeaOp 7025178Sgblack@eecs.umich.edu 7035178Sgblack@eecs.umich.edu 7045359Sgblack@eecs.umich.edu iop = InstObjParams("tia", "Tia", 'X86ISA::LdStOp', 70511329Salexandru.dutu@amd.com { "code": "xc->demapPage(EA, 0);", 70611329Salexandru.dutu@amd.com "ea_code": calculateEA, 70711329Salexandru.dutu@amd.com "memDataSize": "dataSize" }) 7085359Sgblack@eecs.umich.edu header_output += MicroLeaDeclare.subst(iop) 7095359Sgblack@eecs.umich.edu decoder_output += MicroLdStOpConstructor.subst(iop) 7105359Sgblack@eecs.umich.edu exec_output += MicroLeaExecute.subst(iop) 7115359Sgblack@eecs.umich.edu 7125359Sgblack@eecs.umich.edu class TiaOp(LdStOp): 7135359Sgblack@eecs.umich.edu def __init__(self, segment, addr, disp = 0, 7145912Sgblack@eecs.umich.edu dataSize="env.dataSize", 7155912Sgblack@eecs.umich.edu addressSize="env.addressSize"): 7166345Sgblack@eecs.umich.edu super(TiaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment, 7178103Sgblack@eecs.umich.edu addr, disp, dataSize, addressSize, "0", False, False, 7188103Sgblack@eecs.umich.edu False) 7195359Sgblack@eecs.umich.edu self.className = "Tia" 7205359Sgblack@eecs.umich.edu self.mnemonic = "tia" 7215359Sgblack@eecs.umich.edu 7225359Sgblack@eecs.umich.edu microopClasses["tia"] = TiaOp 7235359Sgblack@eecs.umich.edu 7245178Sgblack@eecs.umich.edu class CdaOp(LdStOp): 7255178Sgblack@eecs.umich.edu def __init__(self, segment, addr, disp = 0, 7265912Sgblack@eecs.umich.edu dataSize="env.dataSize", 7275912Sgblack@eecs.umich.edu addressSize="env.addressSize", atCPL0=False): 7286345Sgblack@eecs.umich.edu super(CdaOp, self).__init__("InstRegIndex(NUM_INTREGS)", segment, 7296624Sgblack@eecs.umich.edu addr, disp, dataSize, addressSize, "Request::NO_ACCESS", 7308103Sgblack@eecs.umich.edu atCPL0, False, False) 7315178Sgblack@eecs.umich.edu self.className = "Cda" 7325178Sgblack@eecs.umich.edu self.mnemonic = "cda" 7335178Sgblack@eecs.umich.edu 7345178Sgblack@eecs.umich.edu microopClasses["cda"] = CdaOp 7354587Sgblack@eecs.umich.edu}}; 7364587Sgblack@eecs.umich.edu 737