control_registers.py revision 6055:40bdbc32e3db
17753SWilliam.Wang@arm.com# Copyright (c) 2009 The Regents of The University of Michigan 27753SWilliam.Wang@arm.com# All rights reserved. 37753SWilliam.Wang@arm.com# 47753SWilliam.Wang@arm.com# Redistribution and use in source and binary forms, with or without 57753SWilliam.Wang@arm.com# modification, are permitted provided that the following conditions are 67753SWilliam.Wang@arm.com# met: redistributions of source code must retain the above copyright 77753SWilliam.Wang@arm.com# notice, this list of conditions and the following disclaimer; 87753SWilliam.Wang@arm.com# redistributions in binary form must reproduce the above copyright 97753SWilliam.Wang@arm.com# notice, this list of conditions and the following disclaimer in the 107753SWilliam.Wang@arm.com# documentation and/or other materials provided with the distribution; 117753SWilliam.Wang@arm.com# neither the name of the copyright holders nor the names of its 127753SWilliam.Wang@arm.com# contributors may be used to endorse or promote products derived from 137753SWilliam.Wang@arm.com# this software without specific prior written permission. 147753SWilliam.Wang@arm.com# 157753SWilliam.Wang@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 167753SWilliam.Wang@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 177753SWilliam.Wang@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 187753SWilliam.Wang@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 197753SWilliam.Wang@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 207753SWilliam.Wang@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 217753SWilliam.Wang@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 227753SWilliam.Wang@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 237753SWilliam.Wang@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 247753SWilliam.Wang@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 257753SWilliam.Wang@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 267753SWilliam.Wang@arm.com# 277753SWilliam.Wang@arm.com# Authors: Gabe Black 287753SWilliam.Wang@arm.com 297753SWilliam.Wang@arm.commicrocode = ''' 307753SWilliam.Wang@arm.comdef macroop CLTS { 317753SWilliam.Wang@arm.com rdcr t1, 0, dataSize=8 327753SWilliam.Wang@arm.com andi t1, t1, 0xF7, dataSize=1 337753SWilliam.Wang@arm.com wrcr 0, t1, dataSize=8 347753SWilliam.Wang@arm.com}; 357753SWilliam.Wang@arm.com 367753SWilliam.Wang@arm.comdef macroop LMSW_R { 377753SWilliam.Wang@arm.com rdcr t1, 0, dataSize=8 387753SWilliam.Wang@arm.com # This logic sets MP, EM, and TS to whatever is in the operand. It will 397753SWilliam.Wang@arm.com # set PE but not clear it. 407753SWilliam.Wang@arm.com limm t2, "~ULL(0xe)", dataSize=8 417753SWilliam.Wang@arm.com and t1, t1, t2, dataSize=8 427753SWilliam.Wang@arm.com andi t2, reg, 0xf, dataSize=8 437753SWilliam.Wang@arm.com or t1, t1, t2, dataSize=8 447753SWilliam.Wang@arm.com wrcr 0, t1, dataSize=8 457753SWilliam.Wang@arm.com}; 467753SWilliam.Wang@arm.com 477753SWilliam.Wang@arm.comdef macroop LMSW_M { 487753SWilliam.Wang@arm.com ld t3, seg, sib, disp, dataSize=2 497753SWilliam.Wang@arm.com rdcr t1, 0, dataSize=8 507753SWilliam.Wang@arm.com # This logic sets MP, EM, and TS to whatever is in the operand. It will 517753SWilliam.Wang@arm.com # set PE but not clear it. 527753SWilliam.Wang@arm.com limm t2, "~ULL(0xe)", dataSize=8 537753SWilliam.Wang@arm.com and t1, t1, t2, dataSize=8 547753SWilliam.Wang@arm.com andi t2, t3, 0xf, dataSize=8 557753SWilliam.Wang@arm.com or t1, t1, t2, dataSize=8 567753SWilliam.Wang@arm.com wrcr 0, t1, dataSize=8 577753SWilliam.Wang@arm.com}; 587753SWilliam.Wang@arm.com 597753SWilliam.Wang@arm.comdef macroop LMSW_P { 607753SWilliam.Wang@arm.com rdip t7, dataSize=asz 617753SWilliam.Wang@arm.com ld t3, seg, riprel, disp, dataSize=2 627753SWilliam.Wang@arm.com rdcr t1, 0, dataSize=8 637753SWilliam.Wang@arm.com # This logic sets MP, EM, and TS to whatever is in the operand. It will 647753SWilliam.Wang@arm.com # set PE but not clear it. 657753SWilliam.Wang@arm.com limm t2, "~ULL(0xe)", dataSize=8 667753SWilliam.Wang@arm.com and t1, t1, t2, dataSize=8 677753SWilliam.Wang@arm.com andi t2, t3, 0xf, dataSize=8 687753SWilliam.Wang@arm.com or t1, t1, t2, dataSize=8 697753SWilliam.Wang@arm.com wrcr 0, t1, dataSize=8 707753SWilliam.Wang@arm.com}; 717753SWilliam.Wang@arm.com 727753SWilliam.Wang@arm.comdef macroop SMSW_R { 737753SWilliam.Wang@arm.com rdcr reg, 0 747753SWilliam.Wang@arm.com}; 757753SWilliam.Wang@arm.com 767753SWilliam.Wang@arm.comdef macroop SMSW_M { 777753SWilliam.Wang@arm.com rdcr t1, 0 787753SWilliam.Wang@arm.com st t1, seg, sib, disp, dataSize=2 797753SWilliam.Wang@arm.com}; 807753SWilliam.Wang@arm.com 817753SWilliam.Wang@arm.comdef macroop SMSW_P { 827753SWilliam.Wang@arm.com rdcr t1, 0 837753SWilliam.Wang@arm.com rdip t7, dataSize=asz 847753SWilliam.Wang@arm.com st t1, seg, riprel, disp, dataSize=2 857753SWilliam.Wang@arm.com}; 867753SWilliam.Wang@arm.com''' 877753SWilliam.Wang@arm.com