xref: /gem5/src/arch/x86/isa/insts/system/control_registers.py

# Copyright (c) 2009 The Regents of The University of Michigan
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#
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# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# Authors: Gabe Black

microcode = '''
def macroop CLTS {
    rdcr t1, regIdx(0), dataSize=8
    andi t1, t1, 0xF7, dataSize=1
    wrcr regIdx(0), t1, dataSize=8
};

def macroop LMSW_R {
    rdcr t1, regIdx(0), dataSize=8
    # This logic sets MP, EM, and TS to whatever is in the operand. It will
    # set PE but not clear it.
    limm t2, "~ULL(0xe)", dataSize=8
    and t1, t1, t2, dataSize=8
    andi t2, reg, 0xf, dataSize=8
    or t1, t1, t2, dataSize=8
    wrcr regIdx(0), t1, dataSize=8
};

def macroop LMSW_M {
    ld t3, seg, sib, disp, dataSize=2
    rdcr t1, regIdx(0), dataSize=8
    # This logic sets MP, EM, and TS to whatever is in the operand. It will
    # set PE but not clear it.
    limm t2, "~ULL(0xe)", dataSize=8
    and t1, t1, t2, dataSize=8
    andi t2, t3, 0xf, dataSize=8
    or t1, t1, t2, dataSize=8
    wrcr regIdx(0), t1, dataSize=8
};

def macroop LMSW_P {
    rdip t7, dataSize=asz
    ld t3, seg, riprel, disp, dataSize=2
    rdcr t1, regIdx(0), dataSize=8
    # This logic sets MP, EM, and TS to whatever is in the operand. It will
    # set PE but not clear it.
    limm t2, "~ULL(0xe)", dataSize=8
    and t1, t1, t2, dataSize=8
    andi t2, t3, 0xf, dataSize=8
    or t1, t1, t2, dataSize=8
    wrcr regIdx(0), t1, dataSize=8
};

def macroop SMSW_R {
    rdcr reg, regIdx(0)
};

def macroop SMSW_M {
    rdcr t1, regIdx(0)
    st t1, seg, sib, disp, dataSize=2
};

def macroop SMSW_P {
    rdcr t1, regIdx(0)
    rdip t7, dataSize=asz
    st t1, seg, riprel, disp, dataSize=2
};
'''