romutil.py revision 6057:882f1b921de7
19020Sgblack@eecs.umich.edu# Copyright (c) 2008 The Regents of The University of Michigan 29020Sgblack@eecs.umich.edu# All rights reserved. 39020Sgblack@eecs.umich.edu# 49020Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 59020Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 69020Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 79020Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 89020Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 99020Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 109020Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 119020Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 129020Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 139020Sgblack@eecs.umich.edu# this software without specific prior written permission. 149020Sgblack@eecs.umich.edu# 159020Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 169020Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 179020Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 189020Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 199020Sgblack@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 209020Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 219020Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 229020Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 239020Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 249020Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 259020Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 269020Sgblack@eecs.umich.edu# 279020Sgblack@eecs.umich.edu# Authors: Gabe Black 289020Sgblack@eecs.umich.edu 299020Sgblack@eecs.umich.eduintCodeTemplate = ''' 309020Sgblack@eecs.umich.edudef rom 319020Sgblack@eecs.umich.edu{ 329020Sgblack@eecs.umich.edu # This vectors the CPU into an interrupt handler in long mode. 339020Sgblack@eecs.umich.edu # On entry, t1 is set to the vector of the interrupt and t7 is the current 349024Sgblack@eecs.umich.edu # ip. We need that because rdip returns the next ip. 359023Sgblack@eecs.umich.edu extern %(startLabel)s: 369022Sgblack@eecs.umich.edu 379024Sgblack@eecs.umich.edu # 389023Sgblack@eecs.umich.edu # Get the 64 bit interrupt or trap gate descriptor from the IDT 399023Sgblack@eecs.umich.edu # 409023Sgblack@eecs.umich.edu 419020Sgblack@eecs.umich.edu # Load the gate descriptor from the IDT 429020Sgblack@eecs.umich.edu slli t4, t1, 4, dataSize=8 439020Sgblack@eecs.umich.edu ld t2, idtr, [1, t0, t4], 8, dataSize=8, addressSize=8, atCPL0=True 449020Sgblack@eecs.umich.edu ld t4, idtr, [1, t0, t4], dataSize=8, addressSize=8, atCPL0=True 459022Sgblack@eecs.umich.edu 469022Sgblack@eecs.umich.edu # Make sure the descriptor is a legal gate. 479022Sgblack@eecs.umich.edu chks t1, t4, %(gateCheckType)s 489023Sgblack@eecs.umich.edu 499023Sgblack@eecs.umich.edu # 509023Sgblack@eecs.umich.edu # Get the target CS descriptor using the selector in the gate 519023Sgblack@eecs.umich.edu # descriptor. 529023Sgblack@eecs.umich.edu # 539023Sgblack@eecs.umich.edu srli t10, t4, 16, dataSize=8 549023Sgblack@eecs.umich.edu andi t5, t10, 0xF8, dataSize=8 559023Sgblack@eecs.umich.edu andi t0, t10, 0x4, flags=(EZF,), dataSize=2 569023Sgblack@eecs.umich.edu br rom_local_label("%(startLabel)s_globalDescriptor"), flags=(CEZF,) 579023Sgblack@eecs.umich.edu ld t3, tsl, [1, t0, t5], dataSize=8, addressSize=8, atCPL0=True 589023Sgblack@eecs.umich.edu br rom_local_label("%(startLabel)s_processDescriptor") 599023Sgblack@eecs.umich.edu%(startLabel)s_globalDescriptor: 609023Sgblack@eecs.umich.edu ld t3, tsg, [1, t0, t5], dataSize=8, addressSize=8, atCPL0=True 619023Sgblack@eecs.umich.edu%(startLabel)s_processDescriptor: 629023Sgblack@eecs.umich.edu chks t10, t3, IntCSCheck, dataSize=8 639023Sgblack@eecs.umich.edu wrdl hs, t3, t10, dataSize=8 649023Sgblack@eecs.umich.edu 659023Sgblack@eecs.umich.edu # Stick the target offset in t9. 669023Sgblack@eecs.umich.edu wrdh t9, t4, t2, dataSize=8 679023Sgblack@eecs.umich.edu 689023Sgblack@eecs.umich.edu 699023Sgblack@eecs.umich.edu # 709023Sgblack@eecs.umich.edu # Figure out where the stack should be 719023Sgblack@eecs.umich.edu # 729023Sgblack@eecs.umich.edu 739023Sgblack@eecs.umich.edu # Record what we might set the stack selector to. 749023Sgblack@eecs.umich.edu rdsel t11, ss 759023Sgblack@eecs.umich.edu 769023Sgblack@eecs.umich.edu # Check if we're changing privelege level. At this point we can assume 779023Sgblack@eecs.umich.edu # we're going to a DPL that's less than or equal to the CPL. 789023Sgblack@eecs.umich.edu rdattr t10, hs, dataSize=8 799023Sgblack@eecs.umich.edu srli t10, t10, 3, dataSize=8 809023Sgblack@eecs.umich.edu andi t10, t10, 3, dataSize=8 819023Sgblack@eecs.umich.edu rdattr t5, cs, dataSize=8 829023Sgblack@eecs.umich.edu srli t5, t5, 3, dataSize=8 839023Sgblack@eecs.umich.edu andi t5, t5, 0x3, dataSize=8 849023Sgblack@eecs.umich.edu sub t0, t5, t10, flags=(EZF,), dataSize=8 859023Sgblack@eecs.umich.edu # We're going to change priviledge, so zero out the stack selector. We 869023Sgblack@eecs.umich.edu # need to let the IST have priority so we don't branch yet. 879023Sgblack@eecs.umich.edu mov t11, t0, t0, flags=(nCEZF,) 889023Sgblack@eecs.umich.edu 899023Sgblack@eecs.umich.edu # Check the IST field of the gate descriptor 909023Sgblack@eecs.umich.edu srli t12, t4, 32, dataSize=8 919023Sgblack@eecs.umich.edu andi t12, t12, 0x7, dataSize=8 929023Sgblack@eecs.umich.edu subi t0, t12, 1, flags=(ECF,), dataSize=8 939023Sgblack@eecs.umich.edu br rom_local_label("%(startLabel)s_istStackSwitch"), flags=(nCECF,) 949023Sgblack@eecs.umich.edu br rom_local_label("%(startLabel)s_cplStackSwitch"), flags=(nCEZF,) 959023Sgblack@eecs.umich.edu 969023Sgblack@eecs.umich.edu # If we're here, it's because the stack isn't being switched. 979023Sgblack@eecs.umich.edu # Set t6 to the new aligned rsp. 989023Sgblack@eecs.umich.edu mov t6, t6, rsp, dataSize=8 999023Sgblack@eecs.umich.edu br rom_local_label("%(startLabel)s_stackSwitched") 1009023Sgblack@eecs.umich.edu 1019023Sgblack@eecs.umich.edu%(startLabel)s_istStackSwitch: 1029023Sgblack@eecs.umich.edu ld t6, tr, [8, t12, t0], 0x1c, dataSize=8, addressSize=8, atCPL0=True 1039023Sgblack@eecs.umich.edu br rom_local_label("%(startLabel)s_stackSwitched") 1049023Sgblack@eecs.umich.edu 1059023Sgblack@eecs.umich.edu%(startLabel)s_cplStackSwitch: 1069023Sgblack@eecs.umich.edu # Get the new rsp from the TSS 1079023Sgblack@eecs.umich.edu ld t6, tr, [8, t10, t0], 4, dataSize=8, addressSize=8, atCPL0=True 1089023Sgblack@eecs.umich.edu 1099023Sgblack@eecs.umich.edu%(startLabel)s_stackSwitched: 1109023Sgblack@eecs.umich.edu 1119022Sgblack@eecs.umich.edu andi t6, t6, 0xF0, dataSize=1 1129024Sgblack@eecs.umich.edu subi t6, t6, 40 + %(errorCodeSize)d, dataSize=8 1139022Sgblack@eecs.umich.edu 1149022Sgblack@eecs.umich.edu ## 1159022Sgblack@eecs.umich.edu ## Point of no return. 1169022Sgblack@eecs.umich.edu ## We're now going to irrevocably modify visible state. 1179022Sgblack@eecs.umich.edu ## Anything bad that's going to happen should have happened by now or will 1189022Sgblack@eecs.umich.edu ## happen right now. 1199022Sgblack@eecs.umich.edu ## 1209022Sgblack@eecs.umich.edu wrip t0, t9, dataSize=8 1219022Sgblack@eecs.umich.edu 1229022Sgblack@eecs.umich.edu # 1239022Sgblack@eecs.umich.edu # Set up the target code segment. Do this now so we have the right 1249022Sgblack@eecs.umich.edu # permissions when setting up the stack frame. 1259023Sgblack@eecs.umich.edu # 1269023Sgblack@eecs.umich.edu srli t5, t4, 16, dataSize=8 1279023Sgblack@eecs.umich.edu andi t5, t5, 0xFF, dataSize=8 1289023Sgblack@eecs.umich.edu wrdl cs, t3, t5, dataSize=8 1299023Sgblack@eecs.umich.edu # Tuck away the old CS for use below 1309023Sgblack@eecs.umich.edu limm t10, 0, dataSize=8 1319023Sgblack@eecs.umich.edu rdsel t10, cs, dataSize=2 1329023Sgblack@eecs.umich.edu wrsel cs, t5, dataSize=2 1339023Sgblack@eecs.umich.edu 1349022Sgblack@eecs.umich.edu # Check that we can access everything we need to on the stack 1359020Sgblack@eecs.umich.edu ldst t0, hs, [1, t0, t6], dataSize=8, addressSize=8 1369020Sgblack@eecs.umich.edu ldst t0, hs, [1, t0, t6], \ 1379020Sgblack@eecs.umich.edu 32 + %(errorCodeSize)d, dataSize=8, addressSize=8 1389020Sgblack@eecs.umich.edu 139 140 # 141 # Build up the interrupt stack frame 142 # 143 144 145 # Write out the contents of memory 146 %(errorCodeCode)s 147 st t7, hs, [1, t0, t6], %(errorCodeSize)d, dataSize=8, addressSize=8 148 st t10, hs, [1, t0, t6], 8 + %(errorCodeSize)d, dataSize=8, addressSize=8 149 rflags t10, dataSize=8 150 st t10, hs, [1, t0, t6], 16 + %(errorCodeSize)d, dataSize=8, addressSize=8 151 st rsp, hs, [1, t0, t6], 24 + %(errorCodeSize)d, dataSize=8, addressSize=8 152 rdsel t5, ss, dataSize=2 153 st t5, hs, [1, t0, t6], 32 + %(errorCodeSize)d, dataSize=8, addressSize=8 154 155 # Set the stack segment 156 mov rsp, rsp, t6, dataSize=8 157 wrsel ss, t11, dataSize=2 158 159 # 160 # Adjust rflags which is still in t10 from above 161 # 162 163 # Set IF to the lowest bit of the original gate type. 164 # The type field of the original gate starts at bit 40. 165 166 # Set the TF, NT, and RF bits. We'll flip them at the end. 167 limm t6, (1 << 8) | (1 << 14) | (1 << 16) 168 or t10, t10, t6 169 srli t5, t4, 40, dataSize=8 170 srli t7, t10, 9, dataSize=8 171 xor t5, t7, t5, dataSize=8 172 andi t5, t5, 1, dataSize=8 173 slli t5, t5, 9, dataSize=8 174 or t6, t5, t6, dataSize=8 175 176 # Put the results into rflags 177 wrflags t6, t10 178 179 eret 180}; 181''' 182 183microcode = \ 184intCodeTemplate % {\ 185 "startLabel" : "longModeInterrupt", 186 "gateCheckType" : "IntGateCheck", 187 "errorCodeSize" : 0, 188 "errorCodeCode" : "" 189} + \ 190intCodeTemplate % {\ 191 "startLabel" : "longModeSoftInterrupt", 192 "gateCheckType" : "SoftIntGateCheck", 193 "errorCodeSize" : 0, 194 "errorCodeCode" : "" 195} + \ 196intCodeTemplate % {\ 197 "startLabel" : "longModeInterruptWithError", 198 "gateCheckType" : "IntGateCheck", 199 "errorCodeSize" : 8, 200 "errorCodeCode" : ''' 201 st t15, hs, [1, t0, t6], dataSize=8, addressSize=8 202 ''' 203} + \ 204''' 205def rom 206{ 207 # This vectors the CPU into an interrupt handler in legacy mode. 208 extern legacyModeInterrupt: 209 panic "Legacy mode interrupts not implemented (in microcode)" 210 eret 211}; 212 213def rom 214{ 215 extern initIntHalt: 216 rflags t1 217 limm t2, "~IFBit" 218 and t1, t1, t2 219 wrflags t1, t0 220 halt 221 eret 222}; 223''' 224