romutil.py revision 5853
12SN/A# Copyright (c) 2008 The Regents of The University of Michigan 21762SN/A# All rights reserved. 32SN/A# 42SN/A# Redistribution and use in source and binary forms, with or without 52SN/A# modification, are permitted provided that the following conditions are 62SN/A# met: redistributions of source code must retain the above copyright 72SN/A# notice, this list of conditions and the following disclaimer; 82SN/A# redistributions in binary form must reproduce the above copyright 92SN/A# notice, this list of conditions and the following disclaimer in the 102SN/A# documentation and/or other materials provided with the distribution; 112SN/A# neither the name of the copyright holders nor the names of its 122SN/A# contributors may be used to endorse or promote products derived from 132SN/A# this software without specific prior written permission. 142SN/A# 152SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262SN/A# 272665Ssaidi@eecs.umich.edu# Authors: Gabe Black 282665Ssaidi@eecs.umich.edu 292SN/Amicrocode = ''' 302SN/Adef rom 312439SN/A{ 322984Sgblack@eecs.umich.edu # This vectors the CPU into an interrupt handler in long mode. 33146SN/A # On entry, t1 is set to the vector of the interrupt and t7 is the current 34146SN/A # ip. We need that because rdip returns the next ip. 35146SN/A extern longModeInterrupt: 36146SN/A 37146SN/A # 38146SN/A # Get the 64 bit interrupt or trap gate descriptor from the IDT 391717SN/A # 40146SN/A 411717SN/A # Load the gate descriptor from the IDT 42146SN/A slli t4, t1, 4, dataSize=8 431977SN/A ld t2, idtr, [1, t0, t4], 8, dataSize=8, addressSize=8 442623SN/A ld t4, idtr, [1, t0, t4], dataSize=8, addressSize=8 452683Sktlim@umich.edu 461717SN/A # Make sure the descriptor is a legal gate. 47146SN/A chks t1, t4, IntGateCheck 482683Sktlim@umich.edu 493348Sbinkertn@umich.edu # 502683Sktlim@umich.edu # Get the target CS descriptor using the selector in the gate 512036SN/A # descriptor. 52146SN/A # 5356SN/A srli t10, t4, 16, dataSize=8 5456SN/A andi t5, t10, 0xF8, dataSize=8 5556SN/A andi t0, t10, 0x4, flags=(EZF,), dataSize=2 56695SN/A br rom_local_label("globalDescriptor"), flags=(CEZF,) 572901Ssaidi@eecs.umich.edu ld t3, tsl, [1, t0, t5], dataSize=8, addressSize=8 582SN/A br rom_local_label("processDescriptor") 591858SN/AglobalDescriptor: 603565Sgblack@eecs.umich.edu ld t3, tsg, [1, t0, t5], dataSize=8, addressSize=8 613565Sgblack@eecs.umich.eduprocessDescriptor: 622171SN/A chks t10, t3, IntCSCheck, dataSize=8 632170SN/A wrdl hs, t3, t10, dataSize=8 643562Sgblack@eecs.umich.edu 65146SN/A # Stick the target offset in t9. 662462SN/A wrdh t9, t4, t2, dataSize=8 67146SN/A 682SN/A 692SN/A # 702449SN/A # Figure out where the stack should be 711355SN/A # 722623SN/A 734182Sgblack@eecs.umich.edu # Record what we might set the stack selector to. 74224SN/A rdsel t11, ss 751858SN/A 762683Sktlim@umich.edu # Check if we're changing privelege level. At this point we can assume 772420SN/A # we're going to a DPL that's less than or equal to the CPL. 782683Sktlim@umich.edu rdattr t10, hs, dataSize=8 793402Sktlim@umich.edu srli t10, t10, 3, dataSize=8 802420SN/A andi t10, t10, 3, dataSize=8 812SN/A rdattr t5, cs, dataSize=8 824400Srdreslin@umich.edu srli t5, t5, 3, dataSize=8 832672Sktlim@umich.edu sub t5, t5, t10, dataSize=8 842683Sktlim@umich.edu andi t0, t5, 0x3, flags=(EZF,), dataSize=8 852SN/A # We're going to change priviledge, so zero out the stack selector. We 862SN/A # need to let the IST have priority so we don't branch yet. 87334SN/A wrsel t11, t0, flags=(nCEZF,) 88140SN/A 89334SN/A # Check the IST field of the gate descriptor 902SN/A srli t10, t4, 32, dataSize=8 912SN/A andi t10, t10, 0x7, dataSize=8 922SN/A subi t0, t10, 1, flags=(ECF,), dataSize=8 932680Sktlim@umich.edu br rom_local_label("istStackSwitch"), flags=(nCECF,) 942SN/A br rom_local_label("cplStackSwitch"), flags=(nCEZF,) 952SN/A 962623SN/A # If we're here, it's because the stack isn't being switched. 972SN/A # Set t6 to the new rsp. 982SN/A subi t6, rsp, 40, dataSize=8 992SN/A 100180SN/A # Align the stack 1012623SN/A andi t6, t6, 0xF0, dataSize=1 102393SN/A 103393SN/A # Check that we can access everything we need to on the stack 104393SN/A ldst t0, hs, [1, t0, t6], dataSize=8, addressSize=8 105393SN/A ldst t0, hs, [1, t0, t6], 32, dataSize=8, addressSize=8 106384SN/A br rom_local_label("stackSwitched") 107384SN/A 108393SN/AistStackSwitch: 1092623SN/A panic "IST based stack switching isn't implemented" 110393SN/A br rom_local_label("stackSwitched") 111393SN/A 112393SN/AcplStackSwitch: 113393SN/A panic "CPL change initiated stack switching isn't implemented" 114384SN/A 115189SN/AstackSwitched: 116189SN/A 1172623SN/A 1182SN/A ## 119729SN/A ## Point of no return. 120334SN/A ## We're now going to irrevocably modify visible state. 1212SN/A ## Anything bad that's going to happen should have happened by now or will 1222SN/A ## happen right now. 1232SN/A ## 1242SN/A wrip t0, t9, dataSize=8 1252SN/A 1262SN/A 1272SN/A # 1282SN/A # Build up the interrupt stack frame 1292SN/A # 1302SN/A 1312SN/A 1322SN/A # Write out the contents of memory 1331001SN/A st t7, hs, [1, t0, t6], dataSize=8 1341001SN/A limm t5, 0, dataSize=8 1351001SN/A rdsel t5, cs, dataSize=2 1361001SN/A st t5, hs, [1, t0, t6], 8, dataSize=8 1371001SN/A rflags t10, dataSize=8 1382SN/A st t10, hs, [1, t0, t6], 16, dataSize=8 1392SN/A st rsp, hs, [1, t0, t6], 24, dataSize=8 1402SN/A rdsel t5, ss, dataSize=2 1412SN/A st t5, hs, [1, t0, t6], 32, dataSize=8 1422SN/A 1432SN/A # Set the stack segment 1442SN/A mov rsp, rsp, t6, dataSize=8 1452SN/A wrsel ss, t11, dataSize=2 1462SN/A 1472SN/A # 1482SN/A # Set up the target code segment 1492SN/A # 1502SN/A srli t5, t4, 16, dataSize=8 1512SN/A andi t5, t5, 0xFF, dataSize=8 1522SN/A wrdl cs, t3, t5, dataSize=8 1532SN/A wrsel cs, t5, dataSize=2 1542SN/A 1552390SN/A # 1562390SN/A # Adjust rflags which is still in t10 from above 1572390SN/A # 1582390SN/A 1592390SN/A # Set IF to the lowest bit of the original gate type. 1602390SN/A # The type field of the original gate starts at bit 40. 1612390SN/A 1622390SN/A # Set the TF, NT, and RF bits. We'll flip them at the end. 1632390SN/A limm t6, (1 << 8) | (1 << 14) | (1 << 16) 1642390SN/A or t10, t10, t6 1652390SN/A srli t5, t4, 40, dataSize=8 1662390SN/A srli t7, t10, 9, dataSize=8 167385SN/A xor t5, t7, t5, dataSize=8 1682SN/A andi t5, t5, 1, dataSize=8 1692SN/A slli t5, t5, 9, dataSize=8 1702SN/A or t6, t5, t6, dataSize=8 1712623SN/A 172334SN/A # Put the results into rflags 1732361SN/A wrflags t6, t10 1742623SN/A 175334SN/A eret 176334SN/A}; 177334SN/A 1782623SN/Adef rom 1792SN/A{ 180921SN/A # This vectors the CPU into an interrupt handler in legacy mode. 1812915Sktlim@umich.edu extern legacyModeInterrupt: 1822915Sktlim@umich.edu panic "Legacy mode interrupts not implemented (in microcode)" 1832683Sktlim@umich.edu eret 1842SN/A}; 1852SN/A''' 1862SN/A