romutil.py revision 5680:39ae093fb4eb 
1# Copyright (c) 2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Gabe Black
28
29microcode = '''
30def rom
31{
32    # This vectors the CPU into an interrupt handler in long mode.
33    # On entry, t1 is set to the vector of the interrupt and t7 is the current
34    # ip. We need that because rdip returns the next ip.
35    extern longModeInterrupt:
36
37    #
38    # Get the 64 bit interrupt or trap gate descriptor from the IDT
39    #
40
41    # Load the gate descriptor from the IDT
42    slli t4, t1, 4, dataSize=8
43    ld t2, idtr, [1, t0, t4], 8, dataSize=8, addressSize=8
44    ld t4, idtr, [1, t0, t4], dataSize=8, addressSize=8
45
46    # Check permissions
47    chks t1, t4, IntGateCheck
48
49    mov t1, t1, t4, dataSize=8
50
51    # Check that it's the right type
52    srli t4, t1, 40, dataSize=8
53    andi t4, t4, 0xe, dataSize=8
54    xori t4, t4, 0xe, flags=(EZF,), dataSize=8
55    fault "new GeneralProtection(0)", flags=(nCEZF,)
56
57
58    #
59    # Get the target CS descriptor using the selector in the gate
60    # descriptor.
61    #
62    srli t4, t1, 16, dataSize=8
63    andi t5, t4, 0xF8, dataSize=8
64    andi t0, t4, 0x4, flags=(EZF,), dataSize=2
65    br rom_local_label("globalDescriptor"), flags=(CEZF,)
66    ld t3, tsl, [1, t0, t5], dataSize=8, addressSize=8
67    br rom_local_label("processDescriptor")
68globalDescriptor:
69    ld t3, tsg, [1, t0, t5], dataSize=8, addressSize=8
70processDescriptor:
71    chks t4, t3, IntCSCheck, dataSize=8
72    wrdl hs, t3, t4, dataSize=8
73
74    # Check that the target offset is in canonical form
75    wrdh t4, t1, t2, dataSize=8
76    srli t4, t4, 47, dataSize=8
77    addi t4, t4, 1, dataSize=8
78    srli t4, t4, 1, dataSize=8
79    or t4, t4, t4, flags=(EZF,), dataSize=2
80    fault "new GeneralProtection(0)", flags=(nCEZF,)
81
82
83    #
84    # Figure out where the stack should be
85    #
86
87    # Record what we might set the stack selector to.
88    rdsel t6, ss
89    wrsel hs, t6
90
91    # Check if we're changing privelege level. At this point we can assume
92    # we're going to a DPL that's less than or equal to the CPL.
93    rdattr t4, hs, dataSize=8
94    srli t4, t4, 3, dataSize=8
95    andi t4, t4, 3, dataSize=8
96    rdattr t5, cs, dataSize=8
97    srli t5, t5, 3, dataSize=8
98    sub t5, t5, t4, dataSize=8
99    andi t0, t5, 0x3, flags=(EZF,), dataSize=8
100    # We're going to change priviledge, so zero out the stack selector. We
101    # need to let the IST have priority so we don't branch yet.
102    limm t4, 0
103    wrsel hs, t4, flags=(nCEZF,)
104
105    # Check the IST field of the gate descriptor
106    srli t4, t1, 32, dataSize=8
107    andi t4, t4, 0x7, dataSize=8
108    subi t0, t4, 1, flags=(ECF,), dataSize=8
109    br rom_local_label("istStackSwitch"), flags=(nCECF,)
110    br rom_local_label("cplStackSwitch"), flags=(nCEZF,)
111
112    # If we're here, it's because the stack isn't being switched.
113    # Set t6 to the new rsp.
114    subi t6, rsp, 40, dataSize=8
115
116    # Align the stack
117    andi t6, t6, 0xF0, dataSize=1
118
119    # Check that we can access everything we need to on the stack
120    ldst t0, hs, [1, t0, t6], dataSize=8, addressSize=8
121    ldst t0, hs, [1, t0, t6], 32, dataSize=8, addressSize=8
122    br rom_local_label("stackSwitched")
123
124istStackSwitch:
125    panic "IST based stack switching isn't implemented"
126    br rom_local_label("stackSwitched")
127
128cplStackSwitch:
129    panic "CPL change initiated stack switching isn't implemented"
130
131stackSwitched:
132
133
134    ##
135    ## Point of no return.
136    ## We're now going to irrevocably modify visible state.
137    ## Anything bad that's going to happen should have happened by now.
138    ##
139
140
141    #
142    # Build up the interrupt stack frame
143    #
144
145    # Write out the contents of memory
146    st t7, hs, [1, t0, t6], dataSize=8
147    limm t5, 0, dataSize=8
148    rdsel t5, cs, dataSize=2
149    st t5, hs, [1, t0, t6], 8, dataSize=8
150    rflags t4, dataSize=8
151    st t4, hs, [1, t0, t6], 16, dataSize=8
152    st rsp, hs, [1, t0, t6], 24, dataSize=8
153    rdsel t5, ss, dataSize=2
154    st t5, hs, [1, t0, t6], 32, dataSize=8
155
156    # Set the stack segment
157    mov rsp, rsp, t6, dataSize=8
158    rdsel t7, hs, dataSize=2
159    wrsel ss, t7, dataSize=2
160
161    #
162    # Set up the target code segment
163    #
164    srli t5, t1, 16, dataSize=8
165    andi t5, t5, 0xFF, dataSize=8
166    wrdl cs, t3, t5, dataSize=8
167    wrsel cs, t5, dataSize=2
168    wrdh t7, t1, t2, dataSize=8
169    wrip t0, t7, dataSize=8
170
171    #
172    # Adjust rflags which is still in t4 from above
173    #
174
175    # Set IF to the lowest bit of the original gate type.
176    # The type field of the original gate starts at bit 40.
177
178    # Set the TF, NT, and RF bits. We'll flip them at the end.
179    limm t6, (1 << 8) | (1 << 14) | (1 << 16)
180    or t4, t4, t6
181    srli t5, t1, 40, dataSize=8
182    srli t7, t4, 9, dataSize=8
183    xor t5, t7, t5, dataSize=8
184    andi t5, t5, 1, dataSize=8
185    slli t5, t5, 9, dataSize=8
186    or t6, t5, t6, dataSize=8
187
188    # Put the results into rflags
189    wrflags t6, t4
190
191    eret
192};
193
194def rom
195{
196    # This vectors the CPU into an interrupt handler in legacy mode.
197    extern legacyModeInterrupt:
198    panic "Legacy mode interrupts not implemented (in microcode)"
199    eret
200};
201'''
202