xref: /gem5/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py

# Copyright (c) 2007 The Hewlett-Packard Development Company
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#
# Redistribution and use of this software in source and binary forms,
# with or without modification, are permitted provided that the
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# use which is NOT directed to receiving any direct monetary
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# Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.  Redistributions
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# Authors: Gabe Black

microcode = '''
def macroop SAL_R_I
{
    slli reg, reg, imm, flags=(CF,OF,SF,ZF,PF)
};

def macroop SAL_M_I
{
    ldst t1, seg, sib, disp
    slli t1, t1, imm, flags=(CF,OF,SF,ZF,PF)
    st t1, seg, sib, disp
};

def macroop SAL_P_I
{
    rdip t7
    ldst t1, seg, riprel, disp
    slli t1, t1, imm, flags=(CF,OF,SF,ZF,PF)
    st t1, seg, riprel, disp
};

def macroop SAL_1_R
{
    slli reg, reg, 1, flags=(CF,OF,SF,ZF,PF)
};

def macroop SAL_1_M
{
    ldst t1, seg, sib, disp
    slli t1, t1, 1, flags=(CF,OF,SF,ZF,PF)
    st t1, seg, sib, disp
};

def macroop SAL_1_P
{
    rdip t7
    ldst t1, seg, riprel, disp
    slli t1, t1, 1, flags=(CF,OF,SF,ZF,PF)
    st t1, seg, riprel, disp
};

def macroop SAL_R_R
{
    sll reg, reg, regm, flags=(CF,OF,SF,ZF,PF)
};

def macroop SAL_M_R
{
    ldst t1, seg, sib, disp
    sll t1, t1, reg, flags=(CF,OF,SF,ZF,PF)
    st t1, seg, sib, disp
};

def macroop SAL_P_R
{
    rdip t7
    ldst t1, seg, riprel, disp
    sll t1, t1, reg, flags=(CF,OF,SF,ZF,PF)
    st t1, seg, riprel, disp
};

def macroop SHLD_R_R
{
    mdbi regm, 0
    sld reg, reg, rcx, flags=(CF,OF,SF,ZF,PF)
};

def macroop SHLD_M_R
{
    ldst t1, seg, sib, disp
    mdbi reg, 0
    sld t1, t1, rcx, flags=(CF,OF,SF,ZF,PF)
    st t1, seg, sib, disp
};

def macroop SHLD_P_R
{
    rdip t7
    ldst t1, seg, riprel, disp
    mdbi reg, 0
    sld t1, t1, rcx, flags=(CF,OF,SF,ZF,PF)
    st t1, seg, riprel, disp
};

def macroop SHLD_R_R_I
{
    mdbi regm, 0
    sldi reg, reg, imm, flags=(CF,OF,SF,ZF,PF)
};

def macroop SHLD_M_R_I
{
    ldst t1, seg, sib, disp
    mdbi reg, 0
    sldi t1, t1, imm, flags=(CF,OF,SF,ZF,PF)
    st t1, seg, sib, disp
};

def macroop SHLD_P_R_I
{
    rdip t7
    ldst t1, seg, riprel, disp
    mdbi reg, 0
    sldi t1, t1, imm, flags=(CF,OF,SF,ZF,PF)
    st t1, seg, riprel, disp
};

def macroop SHR_R_I
{
    srli reg, reg, imm, flags=(CF,OF,SF,ZF,PF)
};

def macroop SHR_M_I
{
    ldst t1, seg, sib, disp
    srli t1, t1, imm, flags=(CF,OF,SF,ZF,PF)
    st t1, seg, sib, disp
};

def macroop SHR_P_I
{
    rdip t7
    ldst t1, seg, riprel, disp
    srli t1, t1, imm, flags=(CF,OF,SF,ZF,PF)
    st t1, seg, riprel, disp
};

def macroop SHR_1_R
{
    srli reg, reg, 1, flags=(CF,OF,SF,ZF,PF)
};

def macroop SHR_1_M
{
    ldst t1, seg, sib, disp
    srli t1, t1, 1, flags=(CF,OF,SF,ZF,PF)
    st t1, seg, sib, disp
};

def macroop SHR_1_P
{
    rdip t7
    ldst t1, seg, riprel, disp
    srli t1, t1, 1, flags=(CF,OF,SF,ZF,PF)
    st t1, seg, riprel, disp
};

def macroop SHR_R_R
{
    srl reg, reg, regm, flags=(CF,OF,SF,ZF,PF)
};

def macroop SHR_M_R
{
    ldst t1, seg, sib, disp
    srl t1, t1, reg, flags=(CF,OF,SF,ZF,PF)
    st t1, seg, sib, disp
};

def macroop SHR_P_R
{
    rdip t7
    ldst t1, seg, riprel, disp
    srl t1, t1, reg, flags=(CF,OF,SF,ZF,PF)
    st t1, seg, riprel, disp
};

# SHRD will not set OF correctly when the shift count is 1.
def macroop SHRD_R_R_I
{
    srli t1, reg, imm, flags=(CF,)
    rori t2, regm, imm
    srli t3, regm, imm
    xor t2, t2, t3
    or reg, t1, t2
};

# SHRD will not set OF correctly when the shift count is 1.
def macroop SHRD_M_R_I
{
    ldst t1, seg, sib, disp
    srli t1, t1, imm, flags=(CF,)
    rori t2, reg, imm
    srli t3, reg, imm
    xor t2, t2, t3
    or t1, t1, t2
    st t1, seg, sib, disp
};

# SHRD will not set OF correctly when the shift count is 1.
def macroop SHRD_P_R_I
{
    rdip t7
    ldst t1, seg, riprel, disp
    srli t1, t1, imm, flags=(CF,)
    rori t2, reg, imm
    srli t3, reg, imm
    xor t2, t2, t3
    or t1, t1, t2
    st t1, seg, riprel, disp
};

def macroop SAR_R_I
{
    srai reg, reg, imm, flags=(CF,OF,SF,ZF,PF)
};

def macroop SAR_M_I
{
    ldst t1, seg, sib, disp
    srai t1, t1, imm, flags=(CF,OF,SF,ZF,PF)
    st t1, seg, sib, disp
};

def macroop SAR_P_I
{
    rdip t7
    ldst t1, seg, riprel, disp
    srai t1, t1, imm, flags=(CF,OF,SF,ZF,PF)
    st t1, seg, riprel, disp
};

def macroop SAR_1_R
{
    srai reg, reg, 1, flags=(CF,OF,SF,ZF,PF)
};

def macroop SAR_1_M
{
    ldst t1, seg, sib, disp
    srai t1, t1, 1, flags=(CF,OF,SF,ZF,PF)
    st t1, seg, sib, disp
};

def macroop SAR_1_P
{
    rdip t7
    ldst t1, seg, riprel, disp
    srai t1, t1, 1, flags=(CF,OF,SF,ZF,PF)
    st t1, seg, riprel, disp
};

def macroop SAR_R_R
{
    sra reg, reg, regm, flags=(CF,OF,SF,ZF,PF)
};

def macroop SAR_M_R
{
    ldst t1, seg, sib, disp
    sra t1, t1, reg, flags=(CF,OF,SF,ZF,PF)
    st t1, seg, sib, disp
};

def macroop SAR_P_R
{
    rdip t7
    ldst t1, seg, riprel, disp
    sra t1, t1, reg, flags=(CF,OF,SF,ZF,PF)
    st t1, seg, riprel, disp
};
'''