xref: /gem5/src/arch/x86/isa/insts/general_purpose/compare_and_test/bit_test.py

# Copyright (c) 2007 The Hewlett-Packard Development Company
# All rights reserved.
#
# Redistribution and use of this software in source and binary forms,
# with or without modification, are permitted provided that the
# following conditions are met:
#
# The software must be used only for Non-Commercial Use which means any
# use which is NOT directed to receiving any direct monetary
# compensation for, or commercial advantage from such use.  Illustrative
# examples of non-commercial use are academic research, personal study,
# teaching, education and corporate research & development.
# Illustrative examples of commercial use are distributing products for
# commercial advantage and providing services using the software for
# commercial advantage.
#
# If you wish to use this software or functionality therein that may be
# covered by patents for commercial use, please contact:
#     Director of Intellectual Property Licensing
#     Office of Strategy and Technology
#     Hewlett-Packard Company
#     1501 Page Mill Road
#     Palo Alto, California  94304
#
# Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.  Redistributions
# in binary form must reproduce the above copyright notice, this list of
# conditions and the following disclaimer in the documentation and/or
# other materials provided with the distribution.  Neither the name of
# the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.  No right of
# sublicense is granted herewith.  Derivatives of the software and
# output created using the software may be prepared, but only for
# Non-Commercial Uses.  Derivatives of the software may be shared with
# others provided: (i) the others agree to abide by the list of
# conditions herein which includes the Non-Commercial Use restrictions;
# and (ii) such Derivatives of the software include the above copyright
# notice to acknowledge the contribution from this software where
# applicable, this list of conditions and the disclaimer below.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Gabe Black

microcode = '''
def macroop BT_R_I {
    sexti t0, reg, imm, flags=(CF,)
};

def macroop BT_M_I {
    limm t1, imm, dataSize=asz
    # This fudges just a tiny bit, but it's reasonable to expect the
    # microcode generation logic to have the log of the various sizes
    # floating around as well.
    srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)", \
            dataSize=asz
    add t2, t2, base, dataSize=asz
    ld t1, seg, [scale, index, t2], disp
    sexti t0, t1, imm, flags=(CF,)
};

def macroop BT_P_I {
    rdip t7
    limm t1, imm, dataSize=asz
    srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)", \
            dataSize=asz
    ld t1, seg, [1, t2, t7]
    sexti t0, t1, imm, flags=(CF,)
};

def macroop BT_R_R {
    sext t0, reg, regm, flags=(CF,)
};

def macroop BT_M_R {
    srai t2, reg, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)", \
            dataSize=asz
    add t2, t2, base, dataSize=asz
    ld t1, seg, [scale, index, t2], disp
    sext t0, t1, reg, flags=(CF,)
};

def macroop BT_P_R {
    rdip t7
    srai t2, reg, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)", \
            dataSize=asz
    ld t1, seg, [1, t2, t7]
    sext t0, t1, reg, flags=(CF,)
};

def macroop BTC_R_I {
    sexti t0, reg, imm, flags=(CF,)
    limm t1, 1
    roli t1, t1, imm
    xor reg, reg, t1
};

def macroop BTC_M_I {
    limm t1, imm, dataSize=asz
    # This fudges just a tiny bit, but it's reasonable to expect the
    # microcode generation logic to have the log of the various sizes
    # floating around as well.
    srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)", \
            dataSize=asz
    add t2, t2, base, dataSize=asz
    limm t3, 1
    roli t3, t3, imm
    ldst t1, seg, [scale, index, t2], disp
    sexti t0, t1, imm, flags=(CF,)
    xor t1, t1, t3
    st t1, seg, [scale, index, t2], disp
};

def macroop BTC_P_I {
    rdip t7, dataSize=asz
    limm t1, imm, dataSize=asz
    srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)", \
            dataSize=asz
    limm t3, 1
    roli t3, t3, imm
    ldst t1, seg, [1, t2, t7]
    sexti t0, t1, imm, flags=(CF,)
    xor t1, t1, t3
    st t1, seg, [1, t2, t7], disp
};

def macroop BTC_R_R {
    sext t0, reg, regm, flags=(CF,)
    limm t1, 1
    rol t1, t1, regm
    xor reg, reg, t1
};

def macroop BTC_M_R {
    srai t2, reg, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)", \
            dataSize=asz
    add t2, t2, base, dataSize=asz
    limm t3, 1
    rol t3, t3, reg
    ldst t1, seg, [scale, index, t2], disp
    sext t0, t1, reg, flags=(CF,)
    xor t1, t1, t3
    st t1, seg, [scale, index, t2], disp
};

def macroop BTC_P_R {
    rdip t7, dataSize=asz
    srai t2, reg, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)", \
            dataSize=asz
    limm t3, 1
    rol t3, t3, reg
    ldst t1, seg, [1, t2, t7]
    sext t0, t1, reg, flags=(CF,)
    xor t1, t1, t3
    st t1, seg, [1, t2, t7], disp
};

def macroop BTR_R_I {
    sexti t0, reg, imm, flags=(CF,)
    limm t1, "(uint64_t(-(2ULL)))"
    roli t1, t1, imm
    and reg, reg, t1
};

def macroop BTR_M_I {
    limm t1, imm, dataSize=asz
    # This fudges just a tiny bit, but it's reasonable to expect the
    # microcode generation logic to have the log of the various sizes
    # floating around as well.
    srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)", \
            dataSize=asz
    add t2, t2, base, dataSize=asz
    limm t3, "(uint64_t(-(2ULL)))"
    roli t3, t3, imm
    ldst t1, seg, [scale, index, t2], disp
    sexti t0, t1, imm, flags=(CF,)
    and t1, t1, t3
    st t1, seg, [scale, index, t2], disp
};

def macroop BTR_P_I {
    rdip t7, dataSize=asz
    limm t1, imm, dataSize=asz
    srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)", \
            dataSize=asz
    limm t3, "(uint64_t(-(2ULL)))"
    roli t3, t3, imm
    ldst t1, seg, [1, t2, t7]
    sexti t0, t1, imm, flags=(CF,)
    and t1, t1, t3
    st t1, seg, [1, t2, t7], disp
};

def macroop BTR_R_R {
    sext t0, reg, regm, flags=(CF,)
    limm t1, "(uint64_t(-(2ULL)))"
    rol t1, t1, regm
    and reg, reg, t1
};

def macroop BTR_M_R {
    srai t2, reg, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)", \
            dataSize=asz
    add t2, t2, base, dataSize=asz
    limm t3, "(uint64_t(-(2ULL)))"
    rol t3, t3, reg
    ldst t1, seg, [scale, index, t2], disp
    sext t0, t1, reg, flags=(CF,)
    and t1, t1, t3
    st t1, seg, [scale, index, t2], disp
};

def macroop BTR_P_R {
    rdip t7, dataSize=asz
    srai t2, reg, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)", \
            dataSize=asz
    limm t3, "(uint64_t(-(2ULL)))"
    rol t3, t3, reg
    ldst t1, seg, [1, t2, t7]
    sext t0, t1, reg, flags=(CF,)
    and t1, t1, t3
    st t1, seg, [1, t2, t7], disp
};

def macroop BTS_R_I {
    sexti t0, reg, imm, flags=(CF,)
    limm t1, 1
    roli t1, t1, imm
    or reg, reg, t1
};

def macroop BTS_M_I {
    limm t1, imm, dataSize=asz
    # This fudges just a tiny bit, but it's reasonable to expect the
    # microcode generation logic to have the log of the various sizes
    # floating around as well.
    srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)", \
            dataSize=asz
    add t2, t2, base, dataSize=asz
    limm t3, 1
    roli t3, t3, imm
    ldst t1, seg, [scale, index, t2], disp
    sexti t0, t1, imm, flags=(CF,)
    or t1, t1, t3
    st t1, seg, [scale, index, t2], disp
};

def macroop BTS_P_I {
    rdip t7, dataSize=asz
    limm t1, imm, dataSize=asz
    srai t2, t1, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)", \
            dataSize=asz
    limm t3, 1
    roli t3, t3, imm
    ldst t1, seg, [1, t2, t7]
    sexti t0, t1, imm, flags=(CF,)
    or t1, t1, t3
    st t1, seg, [1, t2, t7], disp
};

def macroop BTS_R_R {
    sext t0, reg, regm, flags=(CF,)
    limm t1, 1
    rol t1, t1, regm
    or reg, reg, t1
};

def macroop BTS_M_R {
    srai t2, reg, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)", \
            dataSize=asz
    add t2, t2, base, dataSize=asz
    limm t3, 1
    rol t3, t3, reg
    ldst t1, seg, [scale, index, t2], disp
    sext t0, t1, reg, flags=(CF,)
    or t1, t1, t3
    st t1, seg, [scale, index, t2], disp
};

def macroop BTS_P_R {
    rdip t7, dataSize=asz
    srai t2, reg, "(env.dataSize == 8) ? 3 : ((env.dataSize == 4) ? 2 : 1)", \
            dataSize=asz
    limm t3, 1
    rol t3, t3, reg
    ldst t1, seg, [1, t2, t7]
    sext t0, t1, reg, flags=(CF,)
    or t1, t1, t3
    st t1, seg, [1, t2, t7], disp
};
'''