add_and_subtract.py revision 7087:fb8d5786ff30 
1# Copyright (c) 2007 The Hewlett-Packard Development Company
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Gabe Black
37
38microcode = '''
39def macroop ADD_R_R
40{
41    add reg, reg, regm, flags=(OF,SF,ZF,AF,PF,CF)
42};
43
44def macroop ADD_R_I
45{
46    limm t1, imm
47    add reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
48};
49
50def macroop ADD_M_I
51{
52    limm t2, imm
53    ldst t1, seg, sib, disp
54    add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
55    st t1, seg, sib, disp
56};
57
58def macroop ADD_P_I
59{
60    rdip t7
61    limm t2, imm
62    ldst t1, seg, riprel, disp
63    add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
64    st t1, seg, riprel, disp
65};
66
67def macroop ADD_LOCKED_M_I
68{
69    limm t2, imm
70    ldstl t1, seg, sib, disp
71    add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
72    stul t1, seg, sib, disp
73};
74
75def macroop ADD_LOCKED_P_I
76{
77    rdip t7
78    limm t2, imm
79    ldstl t1, seg, riprel, disp
80    add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
81    stul t1, seg, riprel, disp
82};
83
84def macroop ADD_M_R
85{
86    ldst t1, seg, sib, disp
87    add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
88    st t1, seg, sib, disp
89};
90
91def macroop ADD_P_R
92{
93    rdip t7
94    ldst t1, seg, riprel, disp
95    add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
96    st t1, seg, riprel, disp
97};
98
99def macroop ADD_LOCKED_M_R
100{
101    ldstl t1, seg, sib, disp
102    add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
103    stul t1, seg, sib, disp
104};
105
106def macroop ADD_LOCKED_P_R
107{
108    rdip t7
109    ldstl t1, seg, riprel, disp
110    add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
111    stul t1, seg, riprel, disp
112};
113
114def macroop ADD_R_M
115{
116    ld t1, seg, sib, disp
117    add reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
118};
119
120def macroop ADD_R_P
121{
122    rdip t7
123    ld t1, seg, riprel, disp
124    add reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
125};
126
127def macroop SUB_R_R
128{
129    sub reg, reg, regm, flags=(OF,SF,ZF,AF,PF,CF)
130};
131
132def macroop SUB_R_I
133{
134    limm t1, imm
135    sub reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
136};
137
138def macroop SUB_R_M
139{
140    ld t1, seg, sib, disp
141    sub reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
142};
143
144def macroop SUB_R_P
145{
146    rdip t7
147    ld t1, seg, riprel, disp
148    sub reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
149};
150
151def macroop SUB_M_I
152{
153    limm t2, imm
154    ldst t1, seg, sib, disp
155    sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
156    st t1, seg, sib, disp
157};
158
159def macroop SUB_P_I
160{
161    rdip t7
162    limm t2, imm
163    ldst t1, seg, riprel, disp
164    sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
165    st t1, seg, riprel, disp
166};
167
168def macroop SUB_LOCKED_M_I
169{
170    limm t2, imm
171    ldstl t1, seg, sib, disp
172    sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
173    stul t1, seg, sib, disp
174};
175
176def macroop SUB_LOCKED_P_I
177{
178    rdip t7
179    limm t2, imm
180    ldstl t1, seg, riprel, disp
181    sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
182    stul t1, seg, riprel, disp
183};
184
185def macroop SUB_M_R
186{
187    ldst t1, seg, sib, disp
188    sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
189    st t1, seg, sib, disp
190};
191
192def macroop SUB_P_R
193{
194    rdip t7
195    ldst t1, seg, riprel, disp
196    sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
197    st t1, seg, riprel, disp
198};
199
200def macroop SUB_LOCKED_M_R
201{
202    ldstl t1, seg, sib, disp
203    sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
204    stul t1, seg, sib, disp
205};
206
207def macroop SUB_LOCKED_P_R
208{
209    rdip t7
210    ldstl t1, seg, riprel, disp
211    sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
212    stul t1, seg, riprel, disp
213};
214
215def macroop ADC_R_R
216{
217    adc reg, reg, regm, flags=(OF,SF,ZF,AF,PF,CF)
218};
219
220def macroop ADC_R_I
221{
222    limm t1, imm
223    adc reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
224};
225
226def macroop ADC_M_I
227{
228    limm t2, imm
229    ldst t1, seg, sib, disp
230    adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
231    st t1, seg, sib, disp
232};
233
234def macroop ADC_P_I
235{
236    rdip t7
237    limm t2, imm
238    ldst t1, seg, riprel, disp
239    adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
240    st t1, seg, riprel, disp
241};
242
243def macroop ADC_LOCKED_M_I
244{
245    limm t2, imm
246    ldstl t1, seg, sib, disp
247    adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
248    stul t1, seg, sib, disp
249};
250
251def macroop ADC_LOCKED_P_I
252{
253    rdip t7
254    limm t2, imm
255    ldstl t1, seg, riprel, disp
256    adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
257    stul t1, seg, riprel, disp
258};
259
260def macroop ADC_M_R
261{
262    ldst t1, seg, sib, disp
263    adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
264    st t1, seg, sib, disp
265};
266
267def macroop ADC_P_R
268{
269    rdip t7
270    ldst t1, seg, riprel, disp
271    adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
272    st t1, seg, riprel, disp
273};
274
275def macroop ADC_LOCKED_M_R
276{
277    ldstl t1, seg, sib, disp
278    adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
279    stul t1, seg, sib, disp
280};
281
282def macroop ADC_LOCKED_P_R
283{
284    rdip t7
285    ldstl t1, seg, riprel, disp
286    adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
287    stul t1, seg, riprel, disp
288};
289
290def macroop ADC_R_M
291{
292    ld t1, seg, sib, disp
293    adc reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
294};
295
296def macroop ADC_R_P
297{
298    rdip t7
299    ld t1, seg, riprel, disp
300    adc reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
301};
302
303def macroop SBB_R_R
304{
305    sbb reg, reg, regm, flags=(OF,SF,ZF,AF,PF,CF)
306};
307
308def macroop SBB_R_I
309{
310    limm t1, imm
311    sbb reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
312};
313
314def macroop SBB_R_M
315{
316    ld t1, seg, sib, disp
317    sbb reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
318};
319
320def macroop SBB_R_P
321{
322    rdip t7
323    ld t1, seg, riprel, disp
324    sbb reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
325};
326
327def macroop SBB_M_I
328{
329    limm t2, imm
330    ldst t1, seg, sib, disp
331    sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
332    st t1, seg, sib, disp
333};
334
335def macroop SBB_P_I
336{
337    rdip t7
338    limm t2, imm
339    ldst t1, seg, riprel, disp
340    sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
341    st t1, seg, riprel, disp
342};
343
344def macroop SBB_LOCKED_M_I
345{
346    limm t2, imm
347    ldstl t1, seg, sib, disp
348    sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
349    stul t1, seg, sib, disp
350};
351
352def macroop SBB_LOCKED_P_I
353{
354    rdip t7
355    limm t2, imm
356    ldstl t1, seg, riprel, disp
357    sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
358    stul t1, seg, riprel, disp
359};
360
361def macroop SBB_M_R
362{
363    ldst t1, seg, sib, disp
364    sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
365    st t1, seg, sib, disp
366};
367
368def macroop SBB_P_R
369{
370    rdip t7
371    ldst t1, seg, riprel, disp
372    sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
373    st t1, seg, riprel, disp
374};
375
376def macroop SBB_LOCKED_M_R
377{
378    ldstl t1, seg, sib, disp
379    sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
380    stul t1, seg, sib, disp
381};
382
383def macroop SBB_LOCKED_P_R
384{
385    rdip t7
386    ldstl t1, seg, riprel, disp
387    sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
388    stul t1, seg, riprel, disp
389};
390
391def macroop NEG_R
392{
393    sub reg, t0, reg, flags=(CF,OF,SF,ZF,AF,PF)
394};
395
396def macroop NEG_M
397{
398    ldst t1, seg, sib, disp
399    sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
400    st t1, seg, sib, disp
401};
402
403def macroop NEG_P
404{
405    rdip t7
406    ldst t1, seg, riprel, disp
407    sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
408    st t1, seg, riprel, disp
409};
410
411def macroop NEG_LOCKED_M
412{
413    ldstl t1, seg, sib, disp
414    sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
415    stul t1, seg, sib, disp
416};
417
418def macroop NEG_LOCKED_P
419{
420    rdip t7
421    ldstl t1, seg, riprel, disp
422    sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
423    stul t1, seg, riprel, disp
424};
425'''
426