xref: /gem5/src/arch/x86/isa/insts/general_purpose/arithmetic/add_and_subtract.py

# Copyright (c) 2007 The Hewlett-Packard Development Company
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#
# Redistribution and use of this software in source and binary forms,
# with or without modification, are permitted provided that the
# following conditions are met:
#
# The software must be used only for Non-Commercial Use which means any
# use which is NOT directed to receiving any direct monetary
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# If you wish to use this software or functionality therein that may be
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# Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.  Redistributions
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# Authors: Gabe Black

microcode = '''
def macroop ADD_R_R
{
    add reg, reg, regm, flags=(OF,SF,ZF,AF,PF,CF)
};

def macroop ADD_R_I
{
    limm t1, imm
    add reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};

def macroop ADD_M_I
{
    limm t2, imm
    ldst t1, seg, sib, disp
    add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
    st t1, seg, sib, disp
};

def macroop ADD_P_I
{
    rdip t7
    limm t2, imm
    ldst t1, seg, riprel, disp
    add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
    st t1, seg, riprel, disp
};

def macroop ADD_LOCKED_M_I
{
    limm t2, imm
    ldstl t1, seg, sib, disp
    add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
    stul t1, seg, sib, disp
};

def macroop ADD_LOCKED_P_I
{
    rdip t7
    limm t2, imm
    ldstl t1, seg, riprel, disp
    add t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
    stul t1, seg, riprel, disp
};

def macroop ADD_M_R
{
    ldst t1, seg, sib, disp
    add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
    st t1, seg, sib, disp
};

def macroop ADD_P_R
{
    rdip t7
    ldst t1, seg, riprel, disp
    add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
    st t1, seg, riprel, disp
};

def macroop ADD_LOCKED_M_R
{
    ldstl t1, seg, sib, disp
    add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
    stul t1, seg, sib, disp
};

def macroop ADD_LOCKED_P_R
{
    rdip t7
    ldstl t1, seg, riprel, disp
    add t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
    stul t1, seg, riprel, disp
};

def macroop ADD_R_M
{
    ld t1, seg, sib, disp
    add reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};

def macroop ADD_R_P
{
    rdip t7
    ld t1, seg, riprel, disp
    add reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};

def macroop SUB_R_R
{
    sub reg, reg, regm, flags=(OF,SF,ZF,AF,PF,CF)
};

def macroop SUB_R_I
{
    limm t1, imm
    sub reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};

def macroop SUB_R_M
{
    ld t1, seg, sib, disp
    sub reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};

def macroop SUB_R_P
{
    rdip t7
    ld t1, seg, riprel, disp
    sub reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};

def macroop SUB_M_I
{
    limm t2, imm
    ldst t1, seg, sib, disp
    sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
    st t1, seg, sib, disp
};

def macroop SUB_P_I
{
    rdip t7
    limm t2, imm
    ldst t1, seg, riprel, disp
    sub t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
    st t1, seg, riprel, disp
};

def macroop SUB_M_R
{
    ldst t1, seg, sib, disp
    sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
    st t1, seg, sib, disp
};

def macroop SUB_P_R
{
    rdip t7
    ldst t1, seg, riprel, disp
    sub t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
    st t1, seg, riprel, disp
};

def macroop ADC_R_R
{
    adc reg, reg, regm, flags=(OF,SF,ZF,AF,PF,CF)
};

def macroop ADC_R_I
{
    limm t1, imm
    adc reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};

def macroop ADC_M_I
{
    limm t2, imm
    ldst t1, seg, sib, disp
    adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
    st t1, seg, sib, disp
};

def macroop ADC_P_I
{
    rdip t7
    limm t2, imm
    ldst t1, seg, riprel, disp
    adc t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
    st t1, seg, riprel, disp
};

def macroop ADC_M_R
{
    ldst t1, seg, sib, disp
    adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
    st t1, seg, sib, disp
};

def macroop ADC_P_R
{
    rdip t7
    ldst t1, seg, riprel, disp
    adc t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
    st t1, seg, riprel, disp
};

def macroop ADC_R_M
{
    ld t1, seg, sib, disp
    adc reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};

def macroop ADC_R_P
{
    rdip t7
    ld t1, seg, riprel, disp
    adc reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};

def macroop SBB_R_R
{
    sbb reg, reg, regm, flags=(OF,SF,ZF,AF,PF,CF)
};

def macroop SBB_R_I
{
    limm t1, imm
    sbb reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};

def macroop SBB_R_M
{
    ld t1, seg, sib, disp
    sbb reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};

def macroop SBB_R_P
{
    rdip t7
    ld t1, seg, riprel, disp
    sbb reg, reg, t1, flags=(OF,SF,ZF,AF,PF,CF)
};

def macroop SBB_M_I
{
    limm t2, imm
    ldst t1, seg, sib, disp
    sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
    st t1, seg, sib, disp
};

def macroop SBB_P_I
{
    rdip t7
    limm t2, imm
    ldst t1, seg, riprel, disp
    sbb t1, t1, t2, flags=(OF,SF,ZF,AF,PF,CF)
    st t1, seg, riprel, disp
};

def macroop SBB_M_R
{
    ldst t1, seg, sib, disp
    sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
    st t1, seg, sib, disp
};

def macroop SBB_P_R
{
    rdip t7
    ldst t1, seg, riprel, disp
    sbb t1, t1, reg, flags=(OF,SF,ZF,AF,PF,CF)
    st t1, seg, riprel, disp
};

def macroop NEG_R
{
    sub reg, t0, reg, flags=(CF,OF,SF,ZF,AF,PF)
};

def macroop NEG_M
{
    ldst t1, seg, sib, disp
    sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
    st t1, seg, sib, disp
};

def macroop NEG_P
{
    rdip t7
    ldst t1, seg, riprel, disp
    sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
    st t1, seg, riprel, disp
};
'''