isa.cc revision 9376:270c9a75e91f
15627Sgblack@eecs.umich.edu/* 25627Sgblack@eecs.umich.edu * Copyright (c) 2009 The Regents of The University of Michigan 35627Sgblack@eecs.umich.edu * All rights reserved. 45627Sgblack@eecs.umich.edu * 55627Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 65627Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 75627Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 85627Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 95627Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 105627Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 115627Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 125627Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 135627Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 145627Sgblack@eecs.umich.edu * this software without specific prior written permission. 155627Sgblack@eecs.umich.edu * 165627Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175627Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185627Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195627Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205627Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215627Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225627Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235627Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245627Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255627Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265627Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275627Sgblack@eecs.umich.edu * 285627Sgblack@eecs.umich.edu * Authors: Gabe Black 295627Sgblack@eecs.umich.edu */ 305627Sgblack@eecs.umich.edu 315627Sgblack@eecs.umich.edu#include "arch/x86/decoder.hh" 325627Sgblack@eecs.umich.edu#include "arch/x86/isa.hh" 335627Sgblack@eecs.umich.edu#include "arch/x86/tlb.hh" 345627Sgblack@eecs.umich.edu#include "cpu/base.hh" 355627Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 365627Sgblack@eecs.umich.edu#include "sim/serialize.hh" 375627Sgblack@eecs.umich.edu 385627Sgblack@eecs.umich.edunamespace X86ISA 395627Sgblack@eecs.umich.edu{ 405627Sgblack@eecs.umich.edu 415627Sgblack@eecs.umich.eduvoid 425627Sgblack@eecs.umich.eduISA::updateHandyM5Reg(Efer efer, CR0 cr0, 435627Sgblack@eecs.umich.edu SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags, 445627Sgblack@eecs.umich.edu ThreadContext *tc) 455627Sgblack@eecs.umich.edu{ 465627Sgblack@eecs.umich.edu HandyM5Reg m5reg = 0; 475627Sgblack@eecs.umich.edu if (efer.lma) { 485627Sgblack@eecs.umich.edu m5reg.mode = LongMode; 495627Sgblack@eecs.umich.edu if (csAttr.longMode) 505627Sgblack@eecs.umich.edu m5reg.submode = SixtyFourBitMode; 515627Sgblack@eecs.umich.edu else 525627Sgblack@eecs.umich.edu m5reg.submode = CompatabilityMode; 535627Sgblack@eecs.umich.edu } else { 545627Sgblack@eecs.umich.edu m5reg.mode = LegacyMode; 555627Sgblack@eecs.umich.edu if (cr0.pe) { 565627Sgblack@eecs.umich.edu if (rflags.vm) 575627Sgblack@eecs.umich.edu m5reg.submode = Virtual8086Mode; 585627Sgblack@eecs.umich.edu else 595627Sgblack@eecs.umich.edu m5reg.submode = ProtectedMode; 605627Sgblack@eecs.umich.edu } else { 616214Snate@binkert.org m5reg.submode = RealMode; 625627Sgblack@eecs.umich.edu } 635627Sgblack@eecs.umich.edu } 645627Sgblack@eecs.umich.edu m5reg.cpl = csAttr.dpl; 655627Sgblack@eecs.umich.edu m5reg.paging = cr0.pg; 665627Sgblack@eecs.umich.edu m5reg.prot = cr0.pe; 675627Sgblack@eecs.umich.edu 685627Sgblack@eecs.umich.edu // Compute the default and alternate operand size. 695627Sgblack@eecs.umich.edu if (m5reg.submode == SixtyFourBitMode || csAttr.defaultSize) { 705627Sgblack@eecs.umich.edu m5reg.defOp = 2; 715627Sgblack@eecs.umich.edu m5reg.altOp = 1; 725627Sgblack@eecs.umich.edu } else { 735627Sgblack@eecs.umich.edu m5reg.defOp = 1; 745627Sgblack@eecs.umich.edu m5reg.altOp = 2; 755627Sgblack@eecs.umich.edu } 765627Sgblack@eecs.umich.edu 775627Sgblack@eecs.umich.edu // Compute the default and alternate address size. 785627Sgblack@eecs.umich.edu if (m5reg.submode == SixtyFourBitMode) { 795627Sgblack@eecs.umich.edu m5reg.defAddr = 3; 805627Sgblack@eecs.umich.edu m5reg.altAddr = 2; 815627Sgblack@eecs.umich.edu } else if (csAttr.defaultSize) { 825627Sgblack@eecs.umich.edu m5reg.defAddr = 2; 835627Sgblack@eecs.umich.edu m5reg.altAddr = 1; 845627Sgblack@eecs.umich.edu } else { 855627Sgblack@eecs.umich.edu m5reg.defAddr = 1; 865627Sgblack@eecs.umich.edu m5reg.altAddr = 2; 875627Sgblack@eecs.umich.edu } 885627Sgblack@eecs.umich.edu 895627Sgblack@eecs.umich.edu // Compute the stack size 905627Sgblack@eecs.umich.edu if (m5reg.submode == SixtyFourBitMode) { 915627Sgblack@eecs.umich.edu m5reg.stack = 3; 925627Sgblack@eecs.umich.edu } else if (ssAttr.defaultSize) { 935627Sgblack@eecs.umich.edu m5reg.stack = 2; 945627Sgblack@eecs.umich.edu } else { 955627Sgblack@eecs.umich.edu m5reg.stack = 1; 965627Sgblack@eecs.umich.edu } 975627Sgblack@eecs.umich.edu 985627Sgblack@eecs.umich.edu regVal[MISCREG_M5_REG] = m5reg; 995627Sgblack@eecs.umich.edu if (tc) 1005627Sgblack@eecs.umich.edu tc->getDecoderPtr()->setM5Reg(m5reg); 1015627Sgblack@eecs.umich.edu} 1025627Sgblack@eecs.umich.edu 1035627Sgblack@eecs.umich.eduvoid 1045627Sgblack@eecs.umich.eduISA::clear() 1055627Sgblack@eecs.umich.edu{ 1065627Sgblack@eecs.umich.edu // Blank everything. 0 might not be an appropriate value for some things, 1075627Sgblack@eecs.umich.edu // but it is for most. 1085627Sgblack@eecs.umich.edu memset(regVal, 0, NumMiscRegs * sizeof(MiscReg)); 1095627Sgblack@eecs.umich.edu regVal[MISCREG_DR6] = (mask(8) << 4) | (mask(16) << 16); 1105627Sgblack@eecs.umich.edu regVal[MISCREG_DR7] = 1 << 10; 1115627Sgblack@eecs.umich.edu} 1125627Sgblack@eecs.umich.edu 1135627Sgblack@eecs.umich.eduMiscReg 1145627Sgblack@eecs.umich.eduISA::readMiscRegNoEffect(int miscReg) 1155627Sgblack@eecs.umich.edu{ 1165627Sgblack@eecs.umich.edu // Make sure we're not dealing with an illegal control register. 1175627Sgblack@eecs.umich.edu // Instructions should filter out these indexes, and nothing else should 1185627Sgblack@eecs.umich.edu // attempt to read them directly. 1195627Sgblack@eecs.umich.edu assert( miscReg != MISCREG_CR1 && 1205627Sgblack@eecs.umich.edu !(miscReg > MISCREG_CR4 && 1215627Sgblack@eecs.umich.edu miscReg < MISCREG_CR8) && 1225627Sgblack@eecs.umich.edu !(miscReg > MISCREG_CR8 && 1235627Sgblack@eecs.umich.edu miscReg <= MISCREG_CR15)); 1245627Sgblack@eecs.umich.edu 1255627Sgblack@eecs.umich.edu return regVal[miscReg]; 1265627Sgblack@eecs.umich.edu} 1275627Sgblack@eecs.umich.edu 1285627Sgblack@eecs.umich.eduMiscReg 1295627Sgblack@eecs.umich.eduISA::readMiscReg(int miscReg, ThreadContext * tc) 1305627Sgblack@eecs.umich.edu{ 1315627Sgblack@eecs.umich.edu if (miscReg == MISCREG_TSC) { 1325627Sgblack@eecs.umich.edu return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle(); 1335627Sgblack@eecs.umich.edu } 1345627Sgblack@eecs.umich.edu 1355627Sgblack@eecs.umich.edu if (miscReg == MISCREG_FSW) { 1365627Sgblack@eecs.umich.edu MiscReg fsw = regVal[MISCREG_FSW]; 1375627Sgblack@eecs.umich.edu MiscReg top = regVal[MISCREG_X87_TOP]; 1385627Sgblack@eecs.umich.edu return (fsw & (~(7ULL << 11))) + (top << 11); 1395627Sgblack@eecs.umich.edu } 1405627Sgblack@eecs.umich.edu 1415627Sgblack@eecs.umich.edu return readMiscRegNoEffect(miscReg); 1425627Sgblack@eecs.umich.edu} 1435627Sgblack@eecs.umich.edu 1445627Sgblack@eecs.umich.eduvoid 1455627Sgblack@eecs.umich.eduISA::setMiscRegNoEffect(int miscReg, MiscReg val) 1465627Sgblack@eecs.umich.edu{ 1475627Sgblack@eecs.umich.edu // Make sure we're not dealing with an illegal control register. 148 // Instructions should filter out these indexes, and nothing else should 149 // attempt to write to them directly. 150 assert( miscReg != MISCREG_CR1 && 151 !(miscReg > MISCREG_CR4 && 152 miscReg < MISCREG_CR8) && 153 !(miscReg > MISCREG_CR8 && 154 miscReg <= MISCREG_CR15)); 155 regVal[miscReg] = val; 156} 157 158void 159ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) 160{ 161 MiscReg newVal = val; 162 switch(miscReg) 163 { 164 case MISCREG_CR0: 165 { 166 CR0 toggled = regVal[miscReg] ^ val; 167 CR0 newCR0 = val; 168 Efer efer = regVal[MISCREG_EFER]; 169 if (toggled.pg && efer.lme) { 170 if (newCR0.pg) { 171 //Turning on long mode 172 efer.lma = 1; 173 regVal[MISCREG_EFER] = efer; 174 } else { 175 //Turning off long mode 176 efer.lma = 0; 177 regVal[MISCREG_EFER] = efer; 178 } 179 } 180 if (toggled.pg) { 181 tc->getITBPtr()->invalidateAll(); 182 tc->getDTBPtr()->invalidateAll(); 183 } 184 //This must always be 1. 185 newCR0.et = 1; 186 newVal = newCR0; 187 updateHandyM5Reg(regVal[MISCREG_EFER], 188 newCR0, 189 regVal[MISCREG_CS_ATTR], 190 regVal[MISCREG_SS_ATTR], 191 regVal[MISCREG_RFLAGS], 192 tc); 193 } 194 break; 195 case MISCREG_CR2: 196 break; 197 case MISCREG_CR3: 198 tc->getITBPtr()->invalidateNonGlobal(); 199 tc->getDTBPtr()->invalidateNonGlobal(); 200 break; 201 case MISCREG_CR4: 202 { 203 CR4 toggled = regVal[miscReg] ^ val; 204 if (toggled.pae || toggled.pse || toggled.pge) { 205 tc->getITBPtr()->invalidateAll(); 206 tc->getDTBPtr()->invalidateAll(); 207 } 208 } 209 break; 210 case MISCREG_CR8: 211 break; 212 case MISCREG_CS_ATTR: 213 { 214 SegAttr toggled = regVal[miscReg] ^ val; 215 SegAttr newCSAttr = val; 216 if (toggled.longMode) { 217 if (newCSAttr.longMode) { 218 regVal[MISCREG_ES_EFF_BASE] = 0; 219 regVal[MISCREG_CS_EFF_BASE] = 0; 220 regVal[MISCREG_SS_EFF_BASE] = 0; 221 regVal[MISCREG_DS_EFF_BASE] = 0; 222 } else { 223 regVal[MISCREG_ES_EFF_BASE] = regVal[MISCREG_ES_BASE]; 224 regVal[MISCREG_CS_EFF_BASE] = regVal[MISCREG_CS_BASE]; 225 regVal[MISCREG_SS_EFF_BASE] = regVal[MISCREG_SS_BASE]; 226 regVal[MISCREG_DS_EFF_BASE] = regVal[MISCREG_DS_BASE]; 227 } 228 } 229 updateHandyM5Reg(regVal[MISCREG_EFER], 230 regVal[MISCREG_CR0], 231 newCSAttr, 232 regVal[MISCREG_SS_ATTR], 233 regVal[MISCREG_RFLAGS], 234 tc); 235 } 236 break; 237 case MISCREG_SS_ATTR: 238 updateHandyM5Reg(regVal[MISCREG_EFER], 239 regVal[MISCREG_CR0], 240 regVal[MISCREG_CS_ATTR], 241 val, 242 regVal[MISCREG_RFLAGS], 243 tc); 244 break; 245 // These segments always actually use their bases, or in other words 246 // their effective bases must stay equal to their actual bases. 247 case MISCREG_FS_BASE: 248 case MISCREG_GS_BASE: 249 case MISCREG_HS_BASE: 250 case MISCREG_TSL_BASE: 251 case MISCREG_TSG_BASE: 252 case MISCREG_TR_BASE: 253 case MISCREG_IDTR_BASE: 254 regVal[MISCREG_SEG_EFF_BASE(miscReg - MISCREG_SEG_BASE_BASE)] = val; 255 break; 256 // These segments ignore their bases in 64 bit mode. 257 // their effective bases must stay equal to their actual bases. 258 case MISCREG_ES_BASE: 259 case MISCREG_CS_BASE: 260 case MISCREG_SS_BASE: 261 case MISCREG_DS_BASE: 262 { 263 Efer efer = regVal[MISCREG_EFER]; 264 SegAttr csAttr = regVal[MISCREG_CS_ATTR]; 265 if (!efer.lma || !csAttr.longMode) // Check for non 64 bit mode. 266 regVal[MISCREG_SEG_EFF_BASE(miscReg - 267 MISCREG_SEG_BASE_BASE)] = val; 268 } 269 break; 270 case MISCREG_TSC: 271 regVal[MISCREG_TSC] = val - tc->getCpuPtr()->curCycle(); 272 return; 273 case MISCREG_DR0: 274 case MISCREG_DR1: 275 case MISCREG_DR2: 276 case MISCREG_DR3: 277 /* These should eventually set up breakpoints. */ 278 break; 279 case MISCREG_DR4: 280 miscReg = MISCREG_DR6; 281 /* Fall through to have the same effects as DR6. */ 282 case MISCREG_DR6: 283 { 284 DR6 dr6 = regVal[MISCREG_DR6]; 285 DR6 newDR6 = val; 286 dr6.b0 = newDR6.b0; 287 dr6.b1 = newDR6.b1; 288 dr6.b2 = newDR6.b2; 289 dr6.b3 = newDR6.b3; 290 dr6.bd = newDR6.bd; 291 dr6.bs = newDR6.bs; 292 dr6.bt = newDR6.bt; 293 newVal = dr6; 294 } 295 break; 296 case MISCREG_DR5: 297 miscReg = MISCREG_DR7; 298 /* Fall through to have the same effects as DR7. */ 299 case MISCREG_DR7: 300 { 301 DR7 dr7 = regVal[MISCREG_DR7]; 302 DR7 newDR7 = val; 303 dr7.l0 = newDR7.l0; 304 dr7.g0 = newDR7.g0; 305 if (dr7.l0 || dr7.g0) { 306 panic("Debug register breakpoints not implemented.\n"); 307 } else { 308 /* Disable breakpoint 0. */ 309 } 310 dr7.l1 = newDR7.l1; 311 dr7.g1 = newDR7.g1; 312 if (dr7.l1 || dr7.g1) { 313 panic("Debug register breakpoints not implemented.\n"); 314 } else { 315 /* Disable breakpoint 1. */ 316 } 317 dr7.l2 = newDR7.l2; 318 dr7.g2 = newDR7.g2; 319 if (dr7.l2 || dr7.g2) { 320 panic("Debug register breakpoints not implemented.\n"); 321 } else { 322 /* Disable breakpoint 2. */ 323 } 324 dr7.l3 = newDR7.l3; 325 dr7.g3 = newDR7.g3; 326 if (dr7.l3 || dr7.g3) { 327 panic("Debug register breakpoints not implemented.\n"); 328 } else { 329 /* Disable breakpoint 3. */ 330 } 331 dr7.gd = newDR7.gd; 332 dr7.rw0 = newDR7.rw0; 333 dr7.len0 = newDR7.len0; 334 dr7.rw1 = newDR7.rw1; 335 dr7.len1 = newDR7.len1; 336 dr7.rw2 = newDR7.rw2; 337 dr7.len2 = newDR7.len2; 338 dr7.rw3 = newDR7.rw3; 339 dr7.len3 = newDR7.len3; 340 } 341 break; 342 case MISCREG_M5_REG: 343 // Writing anything to the m5reg with side effects makes it update 344 // based on the current values of the relevant registers. The actual 345 // value written is discarded. 346 updateHandyM5Reg(regVal[MISCREG_EFER], 347 regVal[MISCREG_CR0], 348 regVal[MISCREG_CS_ATTR], 349 regVal[MISCREG_SS_ATTR], 350 regVal[MISCREG_RFLAGS], 351 tc); 352 return; 353 default: 354 break; 355 } 356 setMiscRegNoEffect(miscReg, newVal); 357} 358 359void 360ISA::serialize(EventManager *em, std::ostream & os) 361{ 362 SERIALIZE_ARRAY(regVal, NumMiscRegs); 363} 364 365void 366ISA::unserialize(EventManager *em, Checkpoint * cp, 367 const std::string & section) 368{ 369 UNSERIALIZE_ARRAY(regVal, NumMiscRegs); 370 updateHandyM5Reg(regVal[MISCREG_EFER], 371 regVal[MISCREG_CR0], 372 regVal[MISCREG_CS_ATTR], 373 regVal[MISCREG_SS_ATTR], 374 regVal[MISCREG_RFLAGS], 375 NULL); 376} 377 378} 379