isa.cc revision 9372
1/* 2 * Copyright (c) 2009 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#include "arch/x86/isa.hh" 32#include "arch/x86/tlb.hh" 33#include "cpu/base.hh" 34#include "cpu/thread_context.hh" 35#include "sim/serialize.hh" 36 37namespace X86ISA 38{ 39 40void 41ISA::updateHandyM5Reg(Efer efer, CR0 cr0, 42 SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags) 43{ 44 HandyM5Reg m5reg = 0; 45 if (efer.lma) { 46 m5reg.mode = LongMode; 47 if (csAttr.longMode) 48 m5reg.submode = SixtyFourBitMode; 49 else 50 m5reg.submode = CompatabilityMode; 51 } else { 52 m5reg.mode = LegacyMode; 53 if (cr0.pe) { 54 if (rflags.vm) 55 m5reg.submode = Virtual8086Mode; 56 else 57 m5reg.submode = ProtectedMode; 58 } else { 59 m5reg.submode = RealMode; 60 } 61 } 62 m5reg.cpl = csAttr.dpl; 63 m5reg.paging = cr0.pg; 64 m5reg.prot = cr0.pe; 65 66 // Compute the default and alternate operand size. 67 if (m5reg.submode == SixtyFourBitMode || csAttr.defaultSize) { 68 m5reg.defOp = 2; 69 m5reg.altOp = 1; 70 } else { 71 m5reg.defOp = 1; 72 m5reg.altOp = 2; 73 } 74 75 // Compute the default and alternate address size. 76 if (m5reg.submode == SixtyFourBitMode) { 77 m5reg.defAddr = 3; 78 m5reg.altAddr = 2; 79 } else if (csAttr.defaultSize) { 80 m5reg.defAddr = 2; 81 m5reg.altAddr = 1; 82 } else { 83 m5reg.defAddr = 1; 84 m5reg.altAddr = 2; 85 } 86 87 // Compute the stack size 88 if (m5reg.submode == SixtyFourBitMode) { 89 m5reg.stack = 3; 90 } else if (ssAttr.defaultSize) { 91 m5reg.stack = 2; 92 } else { 93 m5reg.stack = 1; 94 } 95 96 regVal[MISCREG_M5_REG] = m5reg; 97} 98 99void 100ISA::clear() 101{ 102 // Blank everything. 0 might not be an appropriate value for some things, 103 // but it is for most. 104 memset(regVal, 0, NumMiscRegs * sizeof(MiscReg)); 105 regVal[MISCREG_DR6] = (mask(8) << 4) | (mask(16) << 16); 106 regVal[MISCREG_DR7] = 1 << 10; 107} 108 109MiscReg 110ISA::readMiscRegNoEffect(int miscReg) 111{ 112 // Make sure we're not dealing with an illegal control register. 113 // Instructions should filter out these indexes, and nothing else should 114 // attempt to read them directly. 115 assert( miscReg != MISCREG_CR1 && 116 !(miscReg > MISCREG_CR4 && 117 miscReg < MISCREG_CR8) && 118 !(miscReg > MISCREG_CR8 && 119 miscReg <= MISCREG_CR15)); 120 121 return regVal[miscReg]; 122} 123 124MiscReg 125ISA::readMiscReg(int miscReg, ThreadContext * tc) 126{ 127 if (miscReg == MISCREG_TSC) { 128 return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle(); 129 } 130 131 if (miscReg == MISCREG_FSW) { 132 MiscReg fsw = regVal[MISCREG_FSW]; 133 MiscReg top = regVal[MISCREG_X87_TOP]; 134 return (fsw & (~(7ULL << 11))) + (top << 11); 135 } 136 137 return readMiscRegNoEffect(miscReg); 138} 139 140void 141ISA::setMiscRegNoEffect(int miscReg, MiscReg val) 142{ 143 // Make sure we're not dealing with an illegal control register. 144 // Instructions should filter out these indexes, and nothing else should 145 // attempt to write to them directly. 146 assert( miscReg != MISCREG_CR1 && 147 !(miscReg > MISCREG_CR4 && 148 miscReg < MISCREG_CR8) && 149 !(miscReg > MISCREG_CR8 && 150 miscReg <= MISCREG_CR15)); 151 regVal[miscReg] = val; 152} 153 154void 155ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) 156{ 157 MiscReg newVal = val; 158 switch(miscReg) 159 { 160 case MISCREG_CR0: 161 { 162 CR0 toggled = regVal[miscReg] ^ val; 163 CR0 newCR0 = val; 164 Efer efer = regVal[MISCREG_EFER]; 165 if (toggled.pg && efer.lme) { 166 if (newCR0.pg) { 167 //Turning on long mode 168 efer.lma = 1; 169 regVal[MISCREG_EFER] = efer; 170 } else { 171 //Turning off long mode 172 efer.lma = 0; 173 regVal[MISCREG_EFER] = efer; 174 } 175 } 176 if (toggled.pg) { 177 tc->getITBPtr()->invalidateAll(); 178 tc->getDTBPtr()->invalidateAll(); 179 } 180 //This must always be 1. 181 newCR0.et = 1; 182 newVal = newCR0; 183 updateHandyM5Reg(regVal[MISCREG_EFER], 184 newCR0, 185 regVal[MISCREG_CS_ATTR], 186 regVal[MISCREG_SS_ATTR], 187 regVal[MISCREG_RFLAGS]); 188 } 189 break; 190 case MISCREG_CR2: 191 break; 192 case MISCREG_CR3: 193 tc->getITBPtr()->invalidateNonGlobal(); 194 tc->getDTBPtr()->invalidateNonGlobal(); 195 break; 196 case MISCREG_CR4: 197 { 198 CR4 toggled = regVal[miscReg] ^ val; 199 if (toggled.pae || toggled.pse || toggled.pge) { 200 tc->getITBPtr()->invalidateAll(); 201 tc->getDTBPtr()->invalidateAll(); 202 } 203 } 204 break; 205 case MISCREG_CR8: 206 break; 207 case MISCREG_CS_ATTR: 208 { 209 SegAttr toggled = regVal[miscReg] ^ val; 210 SegAttr newCSAttr = val; 211 if (toggled.longMode) { 212 if (newCSAttr.longMode) { 213 regVal[MISCREG_ES_EFF_BASE] = 0; 214 regVal[MISCREG_CS_EFF_BASE] = 0; 215 regVal[MISCREG_SS_EFF_BASE] = 0; 216 regVal[MISCREG_DS_EFF_BASE] = 0; 217 } else { 218 regVal[MISCREG_ES_EFF_BASE] = regVal[MISCREG_ES_BASE]; 219 regVal[MISCREG_CS_EFF_BASE] = regVal[MISCREG_CS_BASE]; 220 regVal[MISCREG_SS_EFF_BASE] = regVal[MISCREG_SS_BASE]; 221 regVal[MISCREG_DS_EFF_BASE] = regVal[MISCREG_DS_BASE]; 222 } 223 } 224 updateHandyM5Reg(regVal[MISCREG_EFER], 225 regVal[MISCREG_CR0], 226 newCSAttr, 227 regVal[MISCREG_SS_ATTR], 228 regVal[MISCREG_RFLAGS]); 229 } 230 break; 231 case MISCREG_SS_ATTR: 232 updateHandyM5Reg(regVal[MISCREG_EFER], 233 regVal[MISCREG_CR0], 234 regVal[MISCREG_CS_ATTR], 235 val, 236 regVal[MISCREG_RFLAGS]); 237 break; 238 // These segments always actually use their bases, or in other words 239 // their effective bases must stay equal to their actual bases. 240 case MISCREG_FS_BASE: 241 case MISCREG_GS_BASE: 242 case MISCREG_HS_BASE: 243 case MISCREG_TSL_BASE: 244 case MISCREG_TSG_BASE: 245 case MISCREG_TR_BASE: 246 case MISCREG_IDTR_BASE: 247 regVal[MISCREG_SEG_EFF_BASE(miscReg - MISCREG_SEG_BASE_BASE)] = val; 248 break; 249 // These segments ignore their bases in 64 bit mode. 250 // their effective bases must stay equal to their actual bases. 251 case MISCREG_ES_BASE: 252 case MISCREG_CS_BASE: 253 case MISCREG_SS_BASE: 254 case MISCREG_DS_BASE: 255 { 256 Efer efer = regVal[MISCREG_EFER]; 257 SegAttr csAttr = regVal[MISCREG_CS_ATTR]; 258 if (!efer.lma || !csAttr.longMode) // Check for non 64 bit mode. 259 regVal[MISCREG_SEG_EFF_BASE(miscReg - 260 MISCREG_SEG_BASE_BASE)] = val; 261 } 262 break; 263 case MISCREG_TSC: 264 regVal[MISCREG_TSC] = val - tc->getCpuPtr()->curCycle(); 265 return; 266 case MISCREG_DR0: 267 case MISCREG_DR1: 268 case MISCREG_DR2: 269 case MISCREG_DR3: 270 /* These should eventually set up breakpoints. */ 271 break; 272 case MISCREG_DR4: 273 miscReg = MISCREG_DR6; 274 /* Fall through to have the same effects as DR6. */ 275 case MISCREG_DR6: 276 { 277 DR6 dr6 = regVal[MISCREG_DR6]; 278 DR6 newDR6 = val; 279 dr6.b0 = newDR6.b0; 280 dr6.b1 = newDR6.b1; 281 dr6.b2 = newDR6.b2; 282 dr6.b3 = newDR6.b3; 283 dr6.bd = newDR6.bd; 284 dr6.bs = newDR6.bs; 285 dr6.bt = newDR6.bt; 286 newVal = dr6; 287 } 288 break; 289 case MISCREG_DR5: 290 miscReg = MISCREG_DR7; 291 /* Fall through to have the same effects as DR7. */ 292 case MISCREG_DR7: 293 { 294 DR7 dr7 = regVal[MISCREG_DR7]; 295 DR7 newDR7 = val; 296 dr7.l0 = newDR7.l0; 297 dr7.g0 = newDR7.g0; 298 if (dr7.l0 || dr7.g0) { 299 panic("Debug register breakpoints not implemented.\n"); 300 } else { 301 /* Disable breakpoint 0. */ 302 } 303 dr7.l1 = newDR7.l1; 304 dr7.g1 = newDR7.g1; 305 if (dr7.l1 || dr7.g1) { 306 panic("Debug register breakpoints not implemented.\n"); 307 } else { 308 /* Disable breakpoint 1. */ 309 } 310 dr7.l2 = newDR7.l2; 311 dr7.g2 = newDR7.g2; 312 if (dr7.l2 || dr7.g2) { 313 panic("Debug register breakpoints not implemented.\n"); 314 } else { 315 /* Disable breakpoint 2. */ 316 } 317 dr7.l3 = newDR7.l3; 318 dr7.g3 = newDR7.g3; 319 if (dr7.l3 || dr7.g3) { 320 panic("Debug register breakpoints not implemented.\n"); 321 } else { 322 /* Disable breakpoint 3. */ 323 } 324 dr7.gd = newDR7.gd; 325 dr7.rw0 = newDR7.rw0; 326 dr7.len0 = newDR7.len0; 327 dr7.rw1 = newDR7.rw1; 328 dr7.len1 = newDR7.len1; 329 dr7.rw2 = newDR7.rw2; 330 dr7.len2 = newDR7.len2; 331 dr7.rw3 = newDR7.rw3; 332 dr7.len3 = newDR7.len3; 333 } 334 break; 335 case MISCREG_M5_REG: 336 // Writing anything to the m5reg with side effects makes it update 337 // based on the current values of the relevant registers. The actual 338 // value written is discarded. 339 updateHandyM5Reg(regVal[MISCREG_EFER], 340 regVal[MISCREG_CR0], 341 regVal[MISCREG_CS_ATTR], 342 regVal[MISCREG_SS_ATTR], 343 regVal[MISCREG_RFLAGS]); 344 return; 345 default: 346 break; 347 } 348 setMiscRegNoEffect(miscReg, newVal); 349} 350 351void 352ISA::serialize(EventManager *em, std::ostream & os) 353{ 354 SERIALIZE_ARRAY(regVal, NumMiscRegs); 355} 356 357void 358ISA::unserialize(EventManager *em, Checkpoint * cp, 359 const std::string & section) 360{ 361 UNSERIALIZE_ARRAY(regVal, NumMiscRegs); 362 updateHandyM5Reg(regVal[MISCREG_EFER], 363 regVal[MISCREG_CR0], 364 regVal[MISCREG_CS_ATTR], 365 regVal[MISCREG_SS_ATTR], 366 regVal[MISCREG_RFLAGS]); 367} 368 369} 370