isa.cc revision 8147
13170Sstever@eecs.umich.edu/* 25254Sksewell@umich.edu * Copyright (c) 2009 The Regents of The University of Michigan 35254Sksewell@umich.edu * All rights reserved. 43170Sstever@eecs.umich.edu * 55254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 65254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 75254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 85254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 95254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 105254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 115254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 125254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 135254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 145254Sksewell@umich.edu * this software without specific prior written permission. 153170Sstever@eecs.umich.edu * 165254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185254Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195254Sksewell@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205254Sksewell@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215254Sksewell@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225254Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235254Sksewell@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245254Sksewell@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255254Sksewell@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265254Sksewell@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273170Sstever@eecs.umich.edu * 285254Sksewell@umich.edu * Authors: Gabe Black 293170Sstever@eecs.umich.edu */ 303170Sstever@eecs.umich.edu 313170Sstever@eecs.umich.edu#include "arch/x86/isa.hh" 323170Sstever@eecs.umich.edu#include "arch/x86/tlb.hh" 333170Sstever@eecs.umich.edu#include "cpu/base.hh" 343170Sstever@eecs.umich.edu#include "cpu/thread_context.hh" 353170Sstever@eecs.umich.edu#include "sim/serialize.hh" 363170Sstever@eecs.umich.edu 373170Sstever@eecs.umich.edunamespace X86ISA 383170Sstever@eecs.umich.edu{ 393170Sstever@eecs.umich.edu 406329Sgblack@eecs.umich.eduvoid 414661Sksewell@umich.eduISA::updateHandyM5Reg(Efer efer, CR0 cr0, 424661Sksewell@umich.edu SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags) 433170Sstever@eecs.umich.edu{ 443170Sstever@eecs.umich.edu HandyM5Reg m5reg = 0; 453170Sstever@eecs.umich.edu if (efer.lma) { 463170Sstever@eecs.umich.edu m5reg.mode = LongMode; 473170Sstever@eecs.umich.edu if (csAttr.longMode) 486378Sgblack@eecs.umich.edu m5reg.submode = SixtyFourBitMode; 493170Sstever@eecs.umich.edu else 503170Sstever@eecs.umich.edu m5reg.submode = CompatabilityMode; 513170Sstever@eecs.umich.edu } else { 523170Sstever@eecs.umich.edu m5reg.mode = LegacyMode; 536383Sgblack@eecs.umich.edu if (cr0.pe) { 546425Sksewell@umich.edu if (rflags.vm) 556378Sgblack@eecs.umich.edu m5reg.submode = Virtual8086Mode; 566378Sgblack@eecs.umich.edu else 575715Shsul@eecs.umich.edu m5reg.submode = ProtectedMode; 583170Sstever@eecs.umich.edu } else { 593170Sstever@eecs.umich.edu m5reg.submode = RealMode; 603170Sstever@eecs.umich.edu } 613170Sstever@eecs.umich.edu } 623170Sstever@eecs.umich.edu m5reg.cpl = csAttr.dpl; 633170Sstever@eecs.umich.edu m5reg.paging = cr0.pg; 644661Sksewell@umich.edu m5reg.prot = cr0.pe; 654661Sksewell@umich.edu 664661Sksewell@umich.edu // Compute the default and alternate operand size. 674661Sksewell@umich.edu if (m5reg.submode == SixtyFourBitMode || csAttr.defaultSize) { 684661Sksewell@umich.edu m5reg.defOp = 2; 694661Sksewell@umich.edu m5reg.altOp = 1; 706383Sgblack@eecs.umich.edu } else { 716383Sgblack@eecs.umich.edu m5reg.defOp = 1; 724661Sksewell@umich.edu m5reg.altOp = 2; 734661Sksewell@umich.edu } 744661Sksewell@umich.edu 754661Sksewell@umich.edu // Compute the default and alternate address size. 764661Sksewell@umich.edu if (m5reg.submode == SixtyFourBitMode) { 776383Sgblack@eecs.umich.edu m5reg.defAddr = 3; 784661Sksewell@umich.edu m5reg.altAddr = 2; 794661Sksewell@umich.edu } else if (csAttr.defaultSize) { 804661Sksewell@umich.edu m5reg.defAddr = 2; 814661Sksewell@umich.edu m5reg.altAddr = 1; 824661Sksewell@umich.edu } else { 834661Sksewell@umich.edu m5reg.defAddr = 1; 844661Sksewell@umich.edu m5reg.altAddr = 2; 854661Sksewell@umich.edu } 866425Sksewell@umich.edu 875714Shsul@eecs.umich.edu // Compute the stack size 884661Sksewell@umich.edu if (m5reg.submode == SixtyFourBitMode) { 895714Shsul@eecs.umich.edu m5reg.stack = 3; 904661Sksewell@umich.edu } else if (ssAttr.defaultSize) { 914661Sksewell@umich.edu m5reg.stack = 2; 924661Sksewell@umich.edu } else { 936378Sgblack@eecs.umich.edu m5reg.stack = 1; 946378Sgblack@eecs.umich.edu } 955715Shsul@eecs.umich.edu 964661Sksewell@umich.edu regVal[MISCREG_M5_REG] = m5reg; 976378Sgblack@eecs.umich.edu} 986378Sgblack@eecs.umich.edu 995715Shsul@eecs.umich.eduvoid 1004661Sksewell@umich.eduISA::clear() 1014661Sksewell@umich.edu{ 1024661Sksewell@umich.edu // Blank everything. 0 might not be an appropriate value for some things, 1034661Sksewell@umich.edu // but it is for most. 1044661Sksewell@umich.edu memset(regVal, 0, NumMiscRegs * sizeof(MiscReg)); 1054661Sksewell@umich.edu regVal[MISCREG_DR6] = (mask(8) << 4) | (mask(16) << 16); 1063170Sstever@eecs.umich.edu regVal[MISCREG_DR7] = 1 << 10; 1073170Sstever@eecs.umich.edu} 1083170Sstever@eecs.umich.edu 1093170Sstever@eecs.umich.eduMiscReg 1103170Sstever@eecs.umich.eduISA::readMiscRegNoEffect(int miscReg) 1113170Sstever@eecs.umich.edu{ 112 // Make sure we're not dealing with an illegal control register. 113 // Instructions should filter out these indexes, and nothing else should 114 // attempt to read them directly. 115 assert( miscReg != MISCREG_CR1 && 116 !(miscReg > MISCREG_CR4 && 117 miscReg < MISCREG_CR8) && 118 !(miscReg > MISCREG_CR8 && 119 miscReg <= MISCREG_CR15)); 120 121 return regVal[miscReg]; 122} 123 124MiscReg 125ISA::readMiscReg(int miscReg, ThreadContext * tc) 126{ 127 if (miscReg == MISCREG_TSC) { 128 return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle(); 129 } 130 return readMiscRegNoEffect(miscReg); 131} 132 133void 134ISA::setMiscRegNoEffect(int miscReg, MiscReg val) 135{ 136 // Make sure we're not dealing with an illegal control register. 137 // Instructions should filter out these indexes, and nothing else should 138 // attempt to write to them directly. 139 assert( miscReg != MISCREG_CR1 && 140 !(miscReg > MISCREG_CR4 && 141 miscReg < MISCREG_CR8) && 142 !(miscReg > MISCREG_CR8 && 143 miscReg <= MISCREG_CR15)); 144 regVal[miscReg] = val; 145} 146 147void 148ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) 149{ 150 MiscReg newVal = val; 151 switch(miscReg) 152 { 153 case MISCREG_CR0: 154 { 155 CR0 toggled = regVal[miscReg] ^ val; 156 CR0 newCR0 = val; 157 Efer efer = regVal[MISCREG_EFER]; 158 if (toggled.pg && efer.lme) { 159 if (newCR0.pg) { 160 //Turning on long mode 161 efer.lma = 1; 162 regVal[MISCREG_EFER] = efer; 163 } else { 164 //Turning off long mode 165 efer.lma = 0; 166 regVal[MISCREG_EFER] = efer; 167 } 168 } 169 if (toggled.pg) { 170 tc->getITBPtr()->invalidateAll(); 171 tc->getDTBPtr()->invalidateAll(); 172 } 173 //This must always be 1. 174 newCR0.et = 1; 175 newVal = newCR0; 176 updateHandyM5Reg(regVal[MISCREG_EFER], 177 newCR0, 178 regVal[MISCREG_CS_ATTR], 179 regVal[MISCREG_SS_ATTR], 180 regVal[MISCREG_RFLAGS]); 181 } 182 break; 183 case MISCREG_CR2: 184 break; 185 case MISCREG_CR3: 186 tc->getITBPtr()->invalidateNonGlobal(); 187 tc->getDTBPtr()->invalidateNonGlobal(); 188 break; 189 case MISCREG_CR4: 190 { 191 CR4 toggled = regVal[miscReg] ^ val; 192 if (toggled.pae || toggled.pse || toggled.pge) { 193 tc->getITBPtr()->invalidateAll(); 194 tc->getDTBPtr()->invalidateAll(); 195 } 196 } 197 break; 198 case MISCREG_CR8: 199 break; 200 case MISCREG_CS_ATTR: 201 { 202 SegAttr toggled = regVal[miscReg] ^ val; 203 SegAttr newCSAttr = val; 204 if (toggled.longMode) { 205 if (newCSAttr.longMode) { 206 regVal[MISCREG_ES_EFF_BASE] = 0; 207 regVal[MISCREG_CS_EFF_BASE] = 0; 208 regVal[MISCREG_SS_EFF_BASE] = 0; 209 regVal[MISCREG_DS_EFF_BASE] = 0; 210 } else { 211 regVal[MISCREG_ES_EFF_BASE] = regVal[MISCREG_ES_BASE]; 212 regVal[MISCREG_CS_EFF_BASE] = regVal[MISCREG_CS_BASE]; 213 regVal[MISCREG_SS_EFF_BASE] = regVal[MISCREG_SS_BASE]; 214 regVal[MISCREG_DS_EFF_BASE] = regVal[MISCREG_DS_BASE]; 215 } 216 } 217 updateHandyM5Reg(regVal[MISCREG_EFER], 218 regVal[MISCREG_CR0], 219 newCSAttr, 220 regVal[MISCREG_SS_ATTR], 221 regVal[MISCREG_RFLAGS]); 222 } 223 break; 224 case MISCREG_SS_ATTR: 225 updateHandyM5Reg(regVal[MISCREG_EFER], 226 regVal[MISCREG_CR0], 227 regVal[MISCREG_CS_ATTR], 228 val, 229 regVal[MISCREG_RFLAGS]); 230 break; 231 // These segments always actually use their bases, or in other words 232 // their effective bases must stay equal to their actual bases. 233 case MISCREG_FS_BASE: 234 case MISCREG_GS_BASE: 235 case MISCREG_HS_BASE: 236 case MISCREG_TSL_BASE: 237 case MISCREG_TSG_BASE: 238 case MISCREG_TR_BASE: 239 case MISCREG_IDTR_BASE: 240 regVal[MISCREG_SEG_EFF_BASE(miscReg - MISCREG_SEG_BASE_BASE)] = val; 241 break; 242 // These segments ignore their bases in 64 bit mode. 243 // their effective bases must stay equal to their actual bases. 244 case MISCREG_ES_BASE: 245 case MISCREG_CS_BASE: 246 case MISCREG_SS_BASE: 247 case MISCREG_DS_BASE: 248 { 249 Efer efer = regVal[MISCREG_EFER]; 250 SegAttr csAttr = regVal[MISCREG_CS_ATTR]; 251 if (!efer.lma || !csAttr.longMode) // Check for non 64 bit mode. 252 regVal[MISCREG_SEG_EFF_BASE(miscReg - 253 MISCREG_SEG_BASE_BASE)] = val; 254 } 255 break; 256 case MISCREG_TSC: 257 regVal[MISCREG_TSC] = val - tc->getCpuPtr()->curCycle(); 258 return; 259 case MISCREG_DR0: 260 case MISCREG_DR1: 261 case MISCREG_DR2: 262 case MISCREG_DR3: 263 /* These should eventually set up breakpoints. */ 264 break; 265 case MISCREG_DR4: 266 miscReg = MISCREG_DR6; 267 /* Fall through to have the same effects as DR6. */ 268 case MISCREG_DR6: 269 { 270 DR6 dr6 = regVal[MISCREG_DR6]; 271 DR6 newDR6 = val; 272 dr6.b0 = newDR6.b0; 273 dr6.b1 = newDR6.b1; 274 dr6.b2 = newDR6.b2; 275 dr6.b3 = newDR6.b3; 276 dr6.bd = newDR6.bd; 277 dr6.bs = newDR6.bs; 278 dr6.bt = newDR6.bt; 279 newVal = dr6; 280 } 281 break; 282 case MISCREG_DR5: 283 miscReg = MISCREG_DR7; 284 /* Fall through to have the same effects as DR7. */ 285 case MISCREG_DR7: 286 { 287 DR7 dr7 = regVal[MISCREG_DR7]; 288 DR7 newDR7 = val; 289 dr7.l0 = newDR7.l0; 290 dr7.g0 = newDR7.g0; 291 if (dr7.l0 || dr7.g0) { 292 panic("Debug register breakpoints not implemented.\n"); 293 } else { 294 /* Disable breakpoint 0. */ 295 } 296 dr7.l1 = newDR7.l1; 297 dr7.g1 = newDR7.g1; 298 if (dr7.l1 || dr7.g1) { 299 panic("Debug register breakpoints not implemented.\n"); 300 } else { 301 /* Disable breakpoint 1. */ 302 } 303 dr7.l2 = newDR7.l2; 304 dr7.g2 = newDR7.g2; 305 if (dr7.l2 || dr7.g2) { 306 panic("Debug register breakpoints not implemented.\n"); 307 } else { 308 /* Disable breakpoint 2. */ 309 } 310 dr7.l3 = newDR7.l3; 311 dr7.g3 = newDR7.g3; 312 if (dr7.l3 || dr7.g3) { 313 panic("Debug register breakpoints not implemented.\n"); 314 } else { 315 /* Disable breakpoint 3. */ 316 } 317 dr7.gd = newDR7.gd; 318 dr7.rw0 = newDR7.rw0; 319 dr7.len0 = newDR7.len0; 320 dr7.rw1 = newDR7.rw1; 321 dr7.len1 = newDR7.len1; 322 dr7.rw2 = newDR7.rw2; 323 dr7.len2 = newDR7.len2; 324 dr7.rw3 = newDR7.rw3; 325 dr7.len3 = newDR7.len3; 326 } 327 break; 328 case MISCREG_M5_REG: 329 // Writing anything to the m5reg with side effects makes it update 330 // based on the current values of the relevant registers. The actual 331 // value written is discarded. 332 updateHandyM5Reg(regVal[MISCREG_EFER], 333 regVal[MISCREG_CR0], 334 regVal[MISCREG_CS_ATTR], 335 regVal[MISCREG_SS_ATTR], 336 regVal[MISCREG_RFLAGS]); 337 return; 338 default: 339 break; 340 } 341 setMiscRegNoEffect(miscReg, newVal); 342} 343 344void 345ISA::serialize(EventManager *em, std::ostream & os) 346{ 347 SERIALIZE_ARRAY(regVal, NumMiscRegs); 348} 349 350void 351ISA::unserialize(EventManager *em, Checkpoint * cp, 352 const std::string & section) 353{ 354 UNSERIALIZE_ARRAY(regVal, NumMiscRegs); 355 updateHandyM5Reg(regVal[MISCREG_EFER], 356 regVal[MISCREG_CR0], 357 regVal[MISCREG_CS_ATTR], 358 regVal[MISCREG_SS_ATTR], 359 regVal[MISCREG_RFLAGS]); 360} 361 362} 363