xref: /gem5/src/arch/x86/isa.cc

/*
 * Copyright (c) 2009 The Regents of The University of Michigan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * Authors: Gabe Black
 */

#include "arch/x86/isa.hh"
#include "arch/x86/floatregs.hh"
#include "cpu/thread_context.hh"

namespace X86ISA
{

void
ISA::clear()
{
    miscRegFile.clear();
}

MiscReg
ISA::readMiscRegNoEffect(int miscReg)
{
    return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg);
}

MiscReg
ISA::readMiscReg(int miscReg, ThreadContext *tc)
{
    return miscRegFile.readReg((MiscRegIndex)miscReg, tc);
}

void
ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
{
    miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val);
}

void
ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
{
    miscRegFile.setReg((MiscRegIndex)miscReg, val, tc);
}

int
ISA::flattenIntIndex(int reg)
{
    //If we need to fold over the index to match byte semantics, do that.
    //Otherwise, just strip off any extra bits and pass it through.
    if (reg & (1 << 6))
        return (reg & (~(1 << 6) - 0x4));
    else
        return (reg & ~(1 << 6));
}

int
ISA::flattenFloatIndex(int reg)
{
    if (reg >= NUM_FLOATREGS) {
        int top = miscRegFile.readRegNoEffect(MISCREG_X87_TOP);
        reg = FLOATREG_STACK(reg - NUM_FLOATREGS, top);
    }
    return reg;
}

void
ISA::serialize(EventManager *em, std::ostream &os)
{
    miscRegFile.serialize(os);
}

void
ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string &section)
{
    miscRegFile.unserialize(cp, section);
}

}