isa.cc revision 12392
114039Sstacze01@arm.com/* 214039Sstacze01@arm.com * Copyright (c) 2009 The Regents of The University of Michigan 314039Sstacze01@arm.com * All rights reserved. 414039Sstacze01@arm.com * 514039Sstacze01@arm.com * Redistribution and use in source and binary forms, with or without 614039Sstacze01@arm.com * modification, are permitted provided that the following conditions are 714039Sstacze01@arm.com * met: redistributions of source code must retain the above copyright 814039Sstacze01@arm.com * notice, this list of conditions and the following disclaimer; 914039Sstacze01@arm.com * redistributions in binary form must reproduce the above copyright 1014039Sstacze01@arm.com * notice, this list of conditions and the following disclaimer in the 1114039Sstacze01@arm.com * documentation and/or other materials provided with the distribution; 1214039Sstacze01@arm.com * neither the name of the copyright holders nor the names of its 1314039Sstacze01@arm.com * contributors may be used to endorse or promote products derived from 1414039Sstacze01@arm.com * this software without specific prior written permission. 1514039Sstacze01@arm.com * 1614039Sstacze01@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1714039Sstacze01@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1814039Sstacze01@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1914039Sstacze01@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2014039Sstacze01@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2114039Sstacze01@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2214039Sstacze01@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2314039Sstacze01@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2414039Sstacze01@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2514039Sstacze01@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2614039Sstacze01@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2714039Sstacze01@arm.com * 2814039Sstacze01@arm.com * Authors: Gabe Black 2914039Sstacze01@arm.com */ 3014039Sstacze01@arm.com 3114039Sstacze01@arm.com#include "arch/x86/isa.hh" 3214039Sstacze01@arm.com 3314039Sstacze01@arm.com#include "arch/x86/decoder.hh" 3414039Sstacze01@arm.com#include "arch/x86/tlb.hh" 3514039Sstacze01@arm.com#include "cpu/base.hh" 3614039Sstacze01@arm.com#include "cpu/thread_context.hh" 3714039Sstacze01@arm.com#include "params/X86ISA.hh" 3814039Sstacze01@arm.com#include "sim/serialize.hh" 3914039Sstacze01@arm.com 4014039Sstacze01@arm.comnamespace X86ISA 4114039Sstacze01@arm.com{ 4214039Sstacze01@arm.com 4314039Sstacze01@arm.comvoid 4414039Sstacze01@arm.comISA::updateHandyM5Reg(Efer efer, CR0 cr0, 4514039Sstacze01@arm.com SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags, 4614039Sstacze01@arm.com ThreadContext *tc) 4714039Sstacze01@arm.com{ 4814039Sstacze01@arm.com HandyM5Reg m5reg = 0; 4914039Sstacze01@arm.com if (efer.lma) { 5014039Sstacze01@arm.com m5reg.mode = LongMode; 5114039Sstacze01@arm.com if (csAttr.longMode) 5214039Sstacze01@arm.com m5reg.submode = SixtyFourBitMode; 5314039Sstacze01@arm.com else 5414039Sstacze01@arm.com m5reg.submode = CompatabilityMode; 5514039Sstacze01@arm.com } else { 5614039Sstacze01@arm.com m5reg.mode = LegacyMode; 5714039Sstacze01@arm.com if (cr0.pe) { 5814039Sstacze01@arm.com if (rflags.vm) 5914039Sstacze01@arm.com m5reg.submode = Virtual8086Mode; 6014039Sstacze01@arm.com else 6114039Sstacze01@arm.com m5reg.submode = ProtectedMode; 6214039Sstacze01@arm.com } else { 6314039Sstacze01@arm.com m5reg.submode = RealMode; 6414039Sstacze01@arm.com } 6514039Sstacze01@arm.com } 6614039Sstacze01@arm.com m5reg.cpl = csAttr.dpl; 6714039Sstacze01@arm.com m5reg.paging = cr0.pg; 6814039Sstacze01@arm.com m5reg.prot = cr0.pe; 6914039Sstacze01@arm.com 7014086Sgiacomo.travaglini@arm.com // Compute the default and alternate operand size. 7114039Sstacze01@arm.com if (m5reg.submode == SixtyFourBitMode || csAttr.defaultSize) { 7214039Sstacze01@arm.com m5reg.defOp = 2; 7314039Sstacze01@arm.com m5reg.altOp = 1; 7414039Sstacze01@arm.com } else { 7514039Sstacze01@arm.com m5reg.defOp = 1; 7614039Sstacze01@arm.com m5reg.altOp = 2; 7714039Sstacze01@arm.com } 7814039Sstacze01@arm.com 7914039Sstacze01@arm.com // Compute the default and alternate address size. 8014039Sstacze01@arm.com if (m5reg.submode == SixtyFourBitMode) { 8114039Sstacze01@arm.com m5reg.defAddr = 3; 8214039Sstacze01@arm.com m5reg.altAddr = 2; 8314039Sstacze01@arm.com } else if (csAttr.defaultSize) { 8414039Sstacze01@arm.com m5reg.defAddr = 2; 8514039Sstacze01@arm.com m5reg.altAddr = 1; 8614039Sstacze01@arm.com } else { 8714039Sstacze01@arm.com m5reg.defAddr = 1; 8814039Sstacze01@arm.com m5reg.altAddr = 2; 8914039Sstacze01@arm.com } 9014039Sstacze01@arm.com 9114039Sstacze01@arm.com // Compute the stack size 9214039Sstacze01@arm.com if (m5reg.submode == SixtyFourBitMode) { 9314039Sstacze01@arm.com m5reg.stack = 3; 9414039Sstacze01@arm.com } else if (ssAttr.defaultSize) { 9514039Sstacze01@arm.com m5reg.stack = 2; 9614039Sstacze01@arm.com } else { 9714039Sstacze01@arm.com m5reg.stack = 1; 9814039Sstacze01@arm.com } 9914039Sstacze01@arm.com 10014039Sstacze01@arm.com regVal[MISCREG_M5_REG] = m5reg; 10114039Sstacze01@arm.com if (tc) 10214039Sstacze01@arm.com tc->getDecoderPtr()->setM5Reg(m5reg); 10314039Sstacze01@arm.com} 10414039Sstacze01@arm.com 10514039Sstacze01@arm.comvoid 10614039Sstacze01@arm.comISA::clear() 10714039Sstacze01@arm.com{ 10814039Sstacze01@arm.com // Blank everything. 0 might not be an appropriate value for some things, 10914039Sstacze01@arm.com // but it is for most. 11014039Sstacze01@arm.com memset(regVal, 0, NumMiscRegs * sizeof(MiscReg)); 11114039Sstacze01@arm.com regVal[MISCREG_DR6] = (mask(8) << 4) | (mask(16) << 16); 11214039Sstacze01@arm.com regVal[MISCREG_DR7] = 1 << 10; 11314039Sstacze01@arm.com} 11414039Sstacze01@arm.com 11514039Sstacze01@arm.comISA::ISA(Params *p) 11614039Sstacze01@arm.com : SimObject(p) 11714039Sstacze01@arm.com{ 11814039Sstacze01@arm.com clear(); 11914039Sstacze01@arm.com} 12014039Sstacze01@arm.com 12114039Sstacze01@arm.comconst X86ISAParams * 12214039Sstacze01@arm.comISA::params() const 12314039Sstacze01@arm.com{ 12414039Sstacze01@arm.com return dynamic_cast<const Params *>(_params); 12514039Sstacze01@arm.com} 12614039Sstacze01@arm.com 12714039Sstacze01@arm.comMiscReg 12814039Sstacze01@arm.comISA::readMiscRegNoEffect(int miscReg) const 12914039Sstacze01@arm.com{ 13014039Sstacze01@arm.com // Make sure we're not dealing with an illegal control register. 13114039Sstacze01@arm.com // Instructions should filter out these indexes, and nothing else should 13214039Sstacze01@arm.com // attempt to read them directly. 13314039Sstacze01@arm.com assert(isValidMiscReg(miscReg)); 13414039Sstacze01@arm.com 13514039Sstacze01@arm.com return regVal[miscReg]; 13614039Sstacze01@arm.com} 13714039Sstacze01@arm.com 13814039Sstacze01@arm.comMiscReg 13914039Sstacze01@arm.comISA::readMiscReg(int miscReg, ThreadContext * tc) 14014039Sstacze01@arm.com{ 14114039Sstacze01@arm.com if (miscReg == MISCREG_TSC) { 14214039Sstacze01@arm.com return regVal[MISCREG_TSC] + tc->getCpuPtr()->curCycle(); 14314039Sstacze01@arm.com } 14414039Sstacze01@arm.com 14514039Sstacze01@arm.com if (miscReg == MISCREG_FSW) { 14614039Sstacze01@arm.com MiscReg fsw = regVal[MISCREG_FSW]; 14714039Sstacze01@arm.com MiscReg top = regVal[MISCREG_X87_TOP]; 14814039Sstacze01@arm.com return insertBits(fsw, 11, 13, top); 14914039Sstacze01@arm.com } 15014039Sstacze01@arm.com 15114039Sstacze01@arm.com return readMiscRegNoEffect(miscReg); 15214039Sstacze01@arm.com} 15314039Sstacze01@arm.com 15414039Sstacze01@arm.comvoid 15514039Sstacze01@arm.comISA::setMiscRegNoEffect(int miscReg, MiscReg val) 15614039Sstacze01@arm.com{ 15714039Sstacze01@arm.com // Make sure we're not dealing with an illegal control register. 15814039Sstacze01@arm.com // Instructions should filter out these indexes, and nothing else should 15914039Sstacze01@arm.com // attempt to write to them directly. 16014039Sstacze01@arm.com assert(isValidMiscReg(miscReg)); 16114039Sstacze01@arm.com 16214039Sstacze01@arm.com HandyM5Reg m5Reg = regVal[MISCREG_M5_REG]; 16314039Sstacze01@arm.com int reg_width = 64; 16414039Sstacze01@arm.com switch (miscReg) { 16514039Sstacze01@arm.com case MISCREG_X87_TOP: 16614039Sstacze01@arm.com reg_width = 3; 16714039Sstacze01@arm.com break; 16814039Sstacze01@arm.com case MISCREG_FTW: 16914039Sstacze01@arm.com reg_width = 8; 17014039Sstacze01@arm.com break; 17114039Sstacze01@arm.com case MISCREG_FSW: 17214039Sstacze01@arm.com case MISCREG_FCW: 17314039Sstacze01@arm.com case MISCREG_FOP: 17414039Sstacze01@arm.com reg_width = 16; 17514039Sstacze01@arm.com break; 17614039Sstacze01@arm.com case MISCREG_MXCSR: 17714039Sstacze01@arm.com reg_width = 32; 17814039Sstacze01@arm.com break; 17914039Sstacze01@arm.com case MISCREG_FISEG: 18014039Sstacze01@arm.com case MISCREG_FOSEG: 18114039Sstacze01@arm.com if (m5Reg.submode != SixtyFourBitMode) 18214039Sstacze01@arm.com reg_width = 16; 18314039Sstacze01@arm.com break; 18414039Sstacze01@arm.com case MISCREG_FIOFF: 18514039Sstacze01@arm.com case MISCREG_FOOFF: 18614039Sstacze01@arm.com if (m5Reg.submode != SixtyFourBitMode) 18714039Sstacze01@arm.com reg_width = 32; 18814039Sstacze01@arm.com break; 18914039Sstacze01@arm.com default: 19014039Sstacze01@arm.com break; 19114039Sstacze01@arm.com } 19214039Sstacze01@arm.com 19314039Sstacze01@arm.com regVal[miscReg] = val & mask(reg_width); 19414039Sstacze01@arm.com} 19514039Sstacze01@arm.com 19614039Sstacze01@arm.comvoid 19714039Sstacze01@arm.comISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc) 19814039Sstacze01@arm.com{ 19914039Sstacze01@arm.com MiscReg newVal = val; 20014039Sstacze01@arm.com switch(miscReg) 20114039Sstacze01@arm.com { 20214039Sstacze01@arm.com case MISCREG_CR0: 20314039Sstacze01@arm.com { 20414039Sstacze01@arm.com CR0 toggled = regVal[miscReg] ^ val; 20514039Sstacze01@arm.com CR0 newCR0 = val; 20614039Sstacze01@arm.com Efer efer = regVal[MISCREG_EFER]; 20714039Sstacze01@arm.com if (toggled.pg && efer.lme) { 20814039Sstacze01@arm.com if (newCR0.pg) { 20914039Sstacze01@arm.com //Turning on long mode 21014039Sstacze01@arm.com efer.lma = 1; 21114039Sstacze01@arm.com regVal[MISCREG_EFER] = efer; 21214039Sstacze01@arm.com } else { 21314039Sstacze01@arm.com //Turning off long mode 21414039Sstacze01@arm.com efer.lma = 0; 21514039Sstacze01@arm.com regVal[MISCREG_EFER] = efer; 21614039Sstacze01@arm.com } 21714039Sstacze01@arm.com } 21814039Sstacze01@arm.com if (toggled.pg) { 21914039Sstacze01@arm.com tc->getITBPtr()->flushAll(); 22014039Sstacze01@arm.com tc->getDTBPtr()->flushAll(); 22114039Sstacze01@arm.com } 22214039Sstacze01@arm.com //This must always be 1. 22314039Sstacze01@arm.com newCR0.et = 1; 22414039Sstacze01@arm.com newVal = newCR0; 22514039Sstacze01@arm.com updateHandyM5Reg(regVal[MISCREG_EFER], 22614039Sstacze01@arm.com newCR0, 22714039Sstacze01@arm.com regVal[MISCREG_CS_ATTR], 22814039Sstacze01@arm.com regVal[MISCREG_SS_ATTR], 22914039Sstacze01@arm.com regVal[MISCREG_RFLAGS], 23014039Sstacze01@arm.com tc); 23114039Sstacze01@arm.com } 23214039Sstacze01@arm.com break; 23314039Sstacze01@arm.com case MISCREG_CR2: 23414039Sstacze01@arm.com break; 23514039Sstacze01@arm.com case MISCREG_CR3: 23614039Sstacze01@arm.com tc->getITBPtr()->flushNonGlobal(); 23714039Sstacze01@arm.com tc->getDTBPtr()->flushNonGlobal(); 23814039Sstacze01@arm.com break; 23914039Sstacze01@arm.com case MISCREG_CR4: 24014039Sstacze01@arm.com { 24114039Sstacze01@arm.com CR4 toggled = regVal[miscReg] ^ val; 24214039Sstacze01@arm.com if (toggled.pae || toggled.pse || toggled.pge) { 24314039Sstacze01@arm.com tc->getITBPtr()->flushAll(); 24414039Sstacze01@arm.com tc->getDTBPtr()->flushAll(); 24514039Sstacze01@arm.com } 24614039Sstacze01@arm.com } 24714039Sstacze01@arm.com break; 24814039Sstacze01@arm.com case MISCREG_CR8: 24914039Sstacze01@arm.com break; 25014039Sstacze01@arm.com case MISCREG_CS_ATTR: 25114039Sstacze01@arm.com { 25214039Sstacze01@arm.com SegAttr toggled = regVal[miscReg] ^ val; 25314039Sstacze01@arm.com SegAttr newCSAttr = val; 25414039Sstacze01@arm.com if (toggled.longMode) { 25514039Sstacze01@arm.com if (newCSAttr.longMode) { 25614039Sstacze01@arm.com regVal[MISCREG_ES_EFF_BASE] = 0; 25714039Sstacze01@arm.com regVal[MISCREG_CS_EFF_BASE] = 0; 25814039Sstacze01@arm.com regVal[MISCREG_SS_EFF_BASE] = 0; 25914039Sstacze01@arm.com regVal[MISCREG_DS_EFF_BASE] = 0; 26014039Sstacze01@arm.com } else { 26114039Sstacze01@arm.com regVal[MISCREG_ES_EFF_BASE] = regVal[MISCREG_ES_BASE]; 26214039Sstacze01@arm.com regVal[MISCREG_CS_EFF_BASE] = regVal[MISCREG_CS_BASE]; 26314039Sstacze01@arm.com regVal[MISCREG_SS_EFF_BASE] = regVal[MISCREG_SS_BASE]; 26414039Sstacze01@arm.com regVal[MISCREG_DS_EFF_BASE] = regVal[MISCREG_DS_BASE]; 26514039Sstacze01@arm.com } 26614039Sstacze01@arm.com } 26714039Sstacze01@arm.com updateHandyM5Reg(regVal[MISCREG_EFER], 26814039Sstacze01@arm.com regVal[MISCREG_CR0], 26914039Sstacze01@arm.com newCSAttr, 27014039Sstacze01@arm.com regVal[MISCREG_SS_ATTR], 27114039Sstacze01@arm.com regVal[MISCREG_RFLAGS], 27214039Sstacze01@arm.com tc); 27314039Sstacze01@arm.com } 27414039Sstacze01@arm.com break; 27514039Sstacze01@arm.com case MISCREG_SS_ATTR: 27614039Sstacze01@arm.com updateHandyM5Reg(regVal[MISCREG_EFER], 27714039Sstacze01@arm.com regVal[MISCREG_CR0], 27814039Sstacze01@arm.com regVal[MISCREG_CS_ATTR], 27914039Sstacze01@arm.com val, 28014039Sstacze01@arm.com regVal[MISCREG_RFLAGS], 28114039Sstacze01@arm.com tc); 28214039Sstacze01@arm.com break; 28314039Sstacze01@arm.com // These segments always actually use their bases, or in other words 28414039Sstacze01@arm.com // their effective bases must stay equal to their actual bases. 28514039Sstacze01@arm.com case MISCREG_FS_BASE: 28614039Sstacze01@arm.com case MISCREG_GS_BASE: 28714039Sstacze01@arm.com case MISCREG_HS_BASE: 28814039Sstacze01@arm.com case MISCREG_TSL_BASE: 28914039Sstacze01@arm.com case MISCREG_TSG_BASE: 29014039Sstacze01@arm.com case MISCREG_TR_BASE: 29114039Sstacze01@arm.com case MISCREG_IDTR_BASE: 29214039Sstacze01@arm.com regVal[MISCREG_SEG_EFF_BASE(miscReg - MISCREG_SEG_BASE_BASE)] = val; 29314039Sstacze01@arm.com break; 29414039Sstacze01@arm.com // These segments ignore their bases in 64 bit mode. 29514039Sstacze01@arm.com // their effective bases must stay equal to their actual bases. 29614039Sstacze01@arm.com case MISCREG_ES_BASE: 29714039Sstacze01@arm.com case MISCREG_CS_BASE: 29814039Sstacze01@arm.com case MISCREG_SS_BASE: 29914039Sstacze01@arm.com case MISCREG_DS_BASE: 30014039Sstacze01@arm.com { 30114039Sstacze01@arm.com Efer efer = regVal[MISCREG_EFER]; 30214039Sstacze01@arm.com SegAttr csAttr = regVal[MISCREG_CS_ATTR]; 30314039Sstacze01@arm.com if (!efer.lma || !csAttr.longMode) // Check for non 64 bit mode. 30414039Sstacze01@arm.com regVal[MISCREG_SEG_EFF_BASE(miscReg - 30514039Sstacze01@arm.com MISCREG_SEG_BASE_BASE)] = val; 30614039Sstacze01@arm.com } 30714039Sstacze01@arm.com break; 30814039Sstacze01@arm.com case MISCREG_TSC: 30914039Sstacze01@arm.com regVal[MISCREG_TSC] = val - tc->getCpuPtr()->curCycle(); 31014039Sstacze01@arm.com return; 31114039Sstacze01@arm.com case MISCREG_DR0: 31214039Sstacze01@arm.com case MISCREG_DR1: 31314039Sstacze01@arm.com case MISCREG_DR2: 31414102Sgiacomo.travaglini@arm.com case MISCREG_DR3: 31514102Sgiacomo.travaglini@arm.com /* These should eventually set up breakpoints. */ 31614102Sgiacomo.travaglini@arm.com break; 31714102Sgiacomo.travaglini@arm.com case MISCREG_DR4: 31814102Sgiacomo.travaglini@arm.com miscReg = MISCREG_DR6; 31914102Sgiacomo.travaglini@arm.com M5_FALLTHROUGH; 32014102Sgiacomo.travaglini@arm.com case MISCREG_DR6: 32114102Sgiacomo.travaglini@arm.com { 32214102Sgiacomo.travaglini@arm.com DR6 dr6 = regVal[MISCREG_DR6]; 32314039Sstacze01@arm.com DR6 newDR6 = val; 32414116Sgiacomo.travaglini@arm.com dr6.b0 = newDR6.b0; 32514116Sgiacomo.travaglini@arm.com dr6.b1 = newDR6.b1; 32614116Sgiacomo.travaglini@arm.com dr6.b2 = newDR6.b2; 32714116Sgiacomo.travaglini@arm.com dr6.b3 = newDR6.b3; 32814116Sgiacomo.travaglini@arm.com dr6.bd = newDR6.bd; 32914116Sgiacomo.travaglini@arm.com dr6.bs = newDR6.bs; 33014116Sgiacomo.travaglini@arm.com dr6.bt = newDR6.bt; 33114116Sgiacomo.travaglini@arm.com newVal = dr6; 33214116Sgiacomo.travaglini@arm.com } 33314116Sgiacomo.travaglini@arm.com break; 33414116Sgiacomo.travaglini@arm.com case MISCREG_DR5: 33514116Sgiacomo.travaglini@arm.com miscReg = MISCREG_DR7; 33614116Sgiacomo.travaglini@arm.com M5_FALLTHROUGH; 33714116Sgiacomo.travaglini@arm.com case MISCREG_DR7: 33814116Sgiacomo.travaglini@arm.com { 33914116Sgiacomo.travaglini@arm.com DR7 dr7 = regVal[MISCREG_DR7]; 34014116Sgiacomo.travaglini@arm.com DR7 newDR7 = val; 34114116Sgiacomo.travaglini@arm.com dr7.l0 = newDR7.l0; 34214116Sgiacomo.travaglini@arm.com dr7.g0 = newDR7.g0; 34314116Sgiacomo.travaglini@arm.com if (dr7.l0 || dr7.g0) { 34414116Sgiacomo.travaglini@arm.com panic("Debug register breakpoints not implemented.\n"); 34514116Sgiacomo.travaglini@arm.com } else { 34614116Sgiacomo.travaglini@arm.com /* Disable breakpoint 0. */ 34714116Sgiacomo.travaglini@arm.com } 34814039Sstacze01@arm.com dr7.l1 = newDR7.l1; 34914039Sstacze01@arm.com dr7.g1 = newDR7.g1; 35014039Sstacze01@arm.com if (dr7.l1 || dr7.g1) { 35114039Sstacze01@arm.com panic("Debug register breakpoints not implemented.\n"); 35214116Sgiacomo.travaglini@arm.com } else { 35314116Sgiacomo.travaglini@arm.com /* Disable breakpoint 1. */ 35414116Sgiacomo.travaglini@arm.com } 35514116Sgiacomo.travaglini@arm.com dr7.l2 = newDR7.l2; 35614116Sgiacomo.travaglini@arm.com dr7.g2 = newDR7.g2; 35714116Sgiacomo.travaglini@arm.com if (dr7.l2 || dr7.g2) { 35814116Sgiacomo.travaglini@arm.com panic("Debug register breakpoints not implemented.\n"); 35914116Sgiacomo.travaglini@arm.com } else { 36014116Sgiacomo.travaglini@arm.com /* Disable breakpoint 2. */ 36114116Sgiacomo.travaglini@arm.com } 36214116Sgiacomo.travaglini@arm.com dr7.l3 = newDR7.l3; 36314116Sgiacomo.travaglini@arm.com dr7.g3 = newDR7.g3; 36414116Sgiacomo.travaglini@arm.com if (dr7.l3 || dr7.g3) { 36514116Sgiacomo.travaglini@arm.com panic("Debug register breakpoints not implemented.\n"); 36614116Sgiacomo.travaglini@arm.com } else { 36714116Sgiacomo.travaglini@arm.com /* Disable breakpoint 3. */ 36814116Sgiacomo.travaglini@arm.com } 36914116Sgiacomo.travaglini@arm.com dr7.gd = newDR7.gd; 37014116Sgiacomo.travaglini@arm.com dr7.rw0 = newDR7.rw0; 37114116Sgiacomo.travaglini@arm.com dr7.len0 = newDR7.len0; 37214116Sgiacomo.travaglini@arm.com dr7.rw1 = newDR7.rw1; 37314116Sgiacomo.travaglini@arm.com dr7.len1 = newDR7.len1; 37414116Sgiacomo.travaglini@arm.com dr7.rw2 = newDR7.rw2; 37514116Sgiacomo.travaglini@arm.com dr7.len2 = newDR7.len2; 37614039Sstacze01@arm.com dr7.rw3 = newDR7.rw3; 37714039Sstacze01@arm.com dr7.len3 = newDR7.len3; 37814039Sstacze01@arm.com } 37914039Sstacze01@arm.com break; 38014039Sstacze01@arm.com case MISCREG_M5_REG: 38114039Sstacze01@arm.com // Writing anything to the m5reg with side effects makes it update 38214039Sstacze01@arm.com // based on the current values of the relevant registers. The actual 38314039Sstacze01@arm.com // value written is discarded. 38414039Sstacze01@arm.com updateHandyM5Reg(regVal[MISCREG_EFER], 38514039Sstacze01@arm.com regVal[MISCREG_CR0], 38614039Sstacze01@arm.com regVal[MISCREG_CS_ATTR], 38714039Sstacze01@arm.com regVal[MISCREG_SS_ATTR], 38814039Sstacze01@arm.com regVal[MISCREG_RFLAGS], 38914039Sstacze01@arm.com tc); 39014039Sstacze01@arm.com return; 39114039Sstacze01@arm.com default: 39214039Sstacze01@arm.com break; 39314039Sstacze01@arm.com } 39414039Sstacze01@arm.com setMiscRegNoEffect(miscReg, newVal); 39514039Sstacze01@arm.com} 39614039Sstacze01@arm.com 39714039Sstacze01@arm.comvoid 39814039Sstacze01@arm.comISA::serialize(CheckpointOut &cp) const 39914039Sstacze01@arm.com{ 40014039Sstacze01@arm.com SERIALIZE_ARRAY(regVal, NumMiscRegs); 40114039Sstacze01@arm.com} 402 403void 404ISA::unserialize(CheckpointIn &cp) 405{ 406 UNSERIALIZE_ARRAY(regVal, NumMiscRegs); 407 updateHandyM5Reg(regVal[MISCREG_EFER], 408 regVal[MISCREG_CR0], 409 regVal[MISCREG_CS_ATTR], 410 regVal[MISCREG_SS_ATTR], 411 regVal[MISCREG_RFLAGS], 412 NULL); 413} 414 415void 416ISA::startup(ThreadContext *tc) 417{ 418 tc->getDecoderPtr()->setM5Reg(regVal[MISCREG_M5_REG]); 419} 420 421} 422 423X86ISA::ISA * 424X86ISAParams::create() 425{ 426 return new X86ISA::ISA(this); 427} 428