interrupts.hh revision 8746 
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#ifndef __ARCH_X86_INTERRUPTS_HH__
41#define __ARCH_X86_INTERRUPTS_HH__
42
43#include "arch/x86/regs/apic.hh"
44#include "arch/x86/faults.hh"
45#include "arch/x86/intmessage.hh"
46#include "base/bitfield.hh"
47#include "config/full_system.hh"
48#include "cpu/thread_context.hh"
49#include "dev/x86/intdev.hh"
50#include "dev/io_device.hh"
51#include "params/X86LocalApic.hh"
52#include "sim/eventq.hh"
53
54class ThreadContext;
55class BaseCPU;
56
57namespace X86ISA {
58
59class Interrupts : public BasicPioDevice, IntDev
60{
61  protected:
62    // Storage for the APIC registers
63    uint32_t regs[NUM_APIC_REGS];
64
65    BitUnion32(LVTEntry)
66        Bitfield<7, 0> vector;
67        Bitfield<10, 8> deliveryMode;
68        Bitfield<12> status;
69        Bitfield<13> polarity;
70        Bitfield<14> remoteIRR;
71        Bitfield<15> trigger;
72        Bitfield<16> masked;
73        Bitfield<17> periodic;
74    EndBitUnion(LVTEntry)
75
76    /*
77     * Timing related stuff.
78     */
79    Tick latency;
80    Tick clock;
81
82    class ApicTimerEvent : public Event
83    {
84      private:
85        Interrupts *localApic;
86      public:
87        ApicTimerEvent(Interrupts *_localApic) :
88            Event(), localApic(_localApic)
89        {}
90
91        void process()
92        {
93            assert(localApic);
94            if (localApic->triggerTimerInterrupt()) {
95                localApic->setReg(APIC_INITIAL_COUNT,
96                        localApic->readReg(APIC_INITIAL_COUNT));
97            }
98        }
99    };
100
101    ApicTimerEvent apicTimerEvent;
102
103    /*
104     * A set of variables to keep track of interrupts that don't go through
105     * the IRR.
106     */
107    bool pendingSmi;
108    uint8_t smiVector;
109    bool pendingNmi;
110    uint8_t nmiVector;
111    bool pendingExtInt;
112    uint8_t extIntVector;
113    bool pendingInit;
114    uint8_t initVector;
115    bool pendingStartup;
116    uint8_t startupVector;
117    bool startedUp;
118
119    // This is a quick check whether any of the above (except ExtInt) are set.
120    bool pendingUnmaskableInt;
121
122    // A count of how many IPIs are in flight.
123    int pendingIPIs;
124
125    /*
126     * IRR and ISR maintenance.
127     */
128    uint8_t IRRV;
129    uint8_t ISRV;
130
131    int
132    findRegArrayMSB(ApicRegIndex base)
133    {
134        int offset = 7;
135        do {
136            if (regs[base + offset] != 0) {
137                return offset * 32 + findMsbSet(regs[base + offset]);
138            }
139        } while (offset--);
140        return 0;
141    }
142
143    void
144    updateIRRV()
145    {
146        IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE);
147    }
148
149    void
150    updateISRV()
151    {
152        ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE);
153    }
154
155    void
156    setRegArrayBit(ApicRegIndex base, uint8_t vector)
157    {
158        regs[base + (vector / 32)] |= (1 << (vector % 32));
159    }
160
161    void
162    clearRegArrayBit(ApicRegIndex base, uint8_t vector)
163    {
164        regs[base + (vector / 32)] &= ~(1 << (vector % 32));
165    }
166
167    bool
168    getRegArrayBit(ApicRegIndex base, uint8_t vector)
169    {
170        return bits(regs[base + (vector / 32)], vector % 5);
171    }
172
173    void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
174
175    BaseCPU *cpu;
176
177    int initialApicId;
178
179  public:
180
181    int getInitialApicId() { return initialApicId; }
182
183    /*
184     * Params stuff.
185     */
186    typedef X86LocalApicParams Params;
187
188    void setCPU(BaseCPU * newCPU);
189
190    void
191    setClock(Tick newClock)
192    {
193        clock = newClock;
194    }
195
196    const Params *
197    params() const
198    {
199        return dynamic_cast<const Params *>(_params);
200    }
201
202    /*
203     * Initialize this object by registering it with the IO APIC.
204     */
205    void init();
206
207    /*
208     * Functions to interact with the interrupt port from IntDev.
209     */
210    Tick read(PacketPtr pkt);
211    Tick write(PacketPtr pkt);
212    Tick recvMessage(PacketPtr pkt);
213    Tick recvResponse(PacketPtr pkt);
214
215    bool
216    triggerTimerInterrupt()
217    {
218        LVTEntry entry = regs[APIC_LVT_TIMER];
219        if (!entry.masked)
220            requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
221        return entry.periodic;
222    }
223
224    void addressRanges(AddrRangeList &range_list);
225    void getIntAddrRange(AddrRangeList &range_list);
226
227    Port *getPort(const std::string &if_name, int idx = -1)
228    {
229        if (if_name == "int_port")
230            return intPort;
231        return BasicPioDevice::getPort(if_name, idx);
232    }
233
234    /*
235     * Functions to access and manipulate the APIC's registers.
236     */
237
238    uint32_t readReg(ApicRegIndex miscReg);
239    void setReg(ApicRegIndex reg, uint32_t val);
240    void
241    setRegNoEffect(ApicRegIndex reg, uint32_t val)
242    {
243        regs[reg] = val;
244    }
245
246    /*
247     * Constructor.
248     */
249
250    Interrupts(Params * p);
251
252    /*
253     * Functions for retrieving interrupts for the CPU to handle.
254     */
255
256    bool checkInterrupts(ThreadContext *tc) const;
257    Fault getInterrupt(ThreadContext *tc);
258    void updateIntrInfo(ThreadContext *tc);
259
260    /*
261     * Serialization.
262     */
263
264    virtual void serialize(std::ostream &os);
265    virtual void unserialize(Checkpoint *cp, const std::string &section);
266
267    /*
268     * Old functions needed for compatability but which will be phased out
269     * eventually.
270     */
271    void
272    post(int int_num, int index)
273    {
274        panic("Interrupts::post unimplemented!\n");
275    }
276
277    void
278    clear(int int_num, int index)
279    {
280        panic("Interrupts::clear unimplemented!\n");
281    }
282
283    void
284    clearAll()
285    {
286        panic("Interrupts::clearAll unimplemented!\n");
287    }
288};
289
290} // namespace X86ISA
291
292#endif // __ARCH_X86_INTERRUPTS_HH__
293