interrupts.hh revision 7902:aafb4a7384d4 
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#ifndef __ARCH_X86_INTERRUPTS_HH__
41#define __ARCH_X86_INTERRUPTS_HH__
42
43#include "arch/x86/faults.hh"
44#include "arch/x86/intmessage.hh"
45#include "arch/x86/regs/apic.hh"
46#include "base/bitfield.hh"
47#include "cpu/thread_context.hh"
48#include "dev/io_device.hh"
49#include "dev/x86/intdev.hh"
50#include "params/X86LocalApic.hh"
51#include "sim/eventq.hh"
52
53class ThreadContext;
54class BaseCPU;
55
56namespace X86ISA {
57
58class Interrupts : public BasicPioDevice, IntDev
59{
60  protected:
61    // Storage for the APIC registers
62    uint32_t regs[NUM_APIC_REGS];
63
64    BitUnion32(LVTEntry)
65        Bitfield<7, 0> vector;
66        Bitfield<10, 8> deliveryMode;
67        Bitfield<12> status;
68        Bitfield<13> polarity;
69        Bitfield<14> remoteIRR;
70        Bitfield<15> trigger;
71        Bitfield<16> masked;
72        Bitfield<17> periodic;
73    EndBitUnion(LVTEntry)
74
75    /*
76     * Timing related stuff.
77     */
78    Tick latency;
79    Tick clock;
80
81    class ApicTimerEvent : public Event
82    {
83      private:
84        Interrupts *localApic;
85      public:
86        ApicTimerEvent(Interrupts *_localApic) :
87            Event(), localApic(_localApic)
88        {}
89
90        void process()
91        {
92            assert(localApic);
93            if (localApic->triggerTimerInterrupt()) {
94                localApic->setReg(APIC_INITIAL_COUNT,
95                        localApic->readReg(APIC_INITIAL_COUNT));
96            }
97        }
98    };
99
100    ApicTimerEvent apicTimerEvent;
101
102    /*
103     * A set of variables to keep track of interrupts that don't go through
104     * the IRR.
105     */
106    bool pendingSmi;
107    uint8_t smiVector;
108    bool pendingNmi;
109    uint8_t nmiVector;
110    bool pendingExtInt;
111    uint8_t extIntVector;
112    bool pendingInit;
113    uint8_t initVector;
114    bool pendingStartup;
115    uint8_t startupVector;
116    bool startedUp;
117
118    // This is a quick check whether any of the above (except ExtInt) are set.
119    bool pendingUnmaskableInt;
120
121    // A count of how many IPIs are in flight.
122    int pendingIPIs;
123
124    /*
125     * IRR and ISR maintenance.
126     */
127    uint8_t IRRV;
128    uint8_t ISRV;
129
130    int
131    findRegArrayMSB(ApicRegIndex base)
132    {
133        int offset = 7;
134        do {
135            if (regs[base + offset] != 0) {
136                return offset * 32 + findMsbSet(regs[base + offset]);
137            }
138        } while (offset--);
139        return 0;
140    }
141
142    void
143    updateIRRV()
144    {
145        IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE);
146    }
147
148    void
149    updateISRV()
150    {
151        ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE);
152    }
153
154    void
155    setRegArrayBit(ApicRegIndex base, uint8_t vector)
156    {
157        regs[base + (vector / 32)] |= (1 << (vector % 32));
158    }
159
160    void
161    clearRegArrayBit(ApicRegIndex base, uint8_t vector)
162    {
163        regs[base + (vector / 32)] &= ~(1 << (vector % 32));
164    }
165
166    bool
167    getRegArrayBit(ApicRegIndex base, uint8_t vector)
168    {
169        return bits(regs[base + (vector / 32)], vector % 5);
170    }
171
172    void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level);
173
174    BaseCPU *cpu;
175
176    int initialApicId;
177
178  public:
179    /*
180     * Params stuff.
181     */
182    typedef X86LocalApicParams Params;
183
184    void setCPU(BaseCPU * newCPU);
185
186    void
187    setClock(Tick newClock)
188    {
189        clock = newClock;
190    }
191
192    const Params *
193    params() const
194    {
195        return dynamic_cast<const Params *>(_params);
196    }
197
198    /*
199     * Initialize this object by registering it with the IO APIC.
200     */
201    void init();
202
203    /*
204     * Functions to interact with the interrupt port from IntDev.
205     */
206    Tick read(PacketPtr pkt);
207    Tick write(PacketPtr pkt);
208    Tick recvMessage(PacketPtr pkt);
209    Tick recvResponse(PacketPtr pkt);
210
211    bool
212    triggerTimerInterrupt()
213    {
214        LVTEntry entry = regs[APIC_LVT_TIMER];
215        if (!entry.masked)
216            requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger);
217        return entry.periodic;
218    }
219
220    void addressRanges(AddrRangeList &range_list);
221    void getIntAddrRange(AddrRangeList &range_list);
222
223    Port *getPort(const std::string &if_name, int idx = -1)
224    {
225        if (if_name == "int_port")
226            return intPort;
227        return BasicPioDevice::getPort(if_name, idx);
228    }
229
230    /*
231     * Functions to access and manipulate the APIC's registers.
232     */
233
234    uint32_t readReg(ApicRegIndex miscReg);
235    void setReg(ApicRegIndex reg, uint32_t val);
236    void
237    setRegNoEffect(ApicRegIndex reg, uint32_t val)
238    {
239        regs[reg] = val;
240    }
241
242    /*
243     * Constructor.
244     */
245
246    Interrupts(Params * p);
247
248    /*
249     * Functions for retrieving interrupts for the CPU to handle.
250     */
251
252    bool checkInterrupts(ThreadContext *tc) const;
253    Fault getInterrupt(ThreadContext *tc);
254    void updateIntrInfo(ThreadContext *tc);
255
256    /*
257     * Serialization.
258     */
259
260    virtual void serialize(std::ostream &os);
261    virtual void unserialize(Checkpoint *cp, const std::string &section);
262
263    /*
264     * Old functions needed for compatability but which will be phased out
265     * eventually.
266     */
267    void
268    post(int int_num, int index)
269    {
270        panic("Interrupts::post unimplemented!\n");
271    }
272
273    void
274    clear(int int_num, int index)
275    {
276        panic("Interrupts::clear unimplemented!\n");
277    }
278
279    void
280    clearAll()
281    {
282        panic("Interrupts::clearAll unimplemented!\n");
283    }
284};
285
286} // namespace X86ISA
287
288#endif // __ARCH_X86_INTERRUPTS_HH__
289