interrupts.hh revision 6050
1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use of this software in source and binary forms, 6 * with or without modification, are permitted provided that the 7 * following conditions are met: 8 * 9 * The software must be used only for Non-Commercial Use which means any 10 * use which is NOT directed to receiving any direct monetary 11 * compensation for, or commercial advantage from such use. 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Derivatives of the software may be shared with 37 * others provided: (i) the others agree to abide by the list of 38 * conditions herein which includes the Non-Commercial Use restrictions; 39 * and (ii) such Derivatives of the software include the above copyright 40 * notice to acknowledge the contribution from this software where 41 * applicable, this list of conditions and the disclaimer below. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * 55 * Authors: Gabe Black 56 */ 57 58#ifndef __ARCH_X86_INTERRUPTS_HH__ 59#define __ARCH_X86_INTERRUPTS_HH__ 60 61#include "arch/x86/apicregs.hh" 62#include "arch/x86/faults.hh" 63#include "arch/x86/intmessage.hh" 64#include "base/bitfield.hh" 65#include "cpu/thread_context.hh" 66#include "dev/io_device.hh" 67#include "dev/x86/intdev.hh" 68#include "params/X86LocalApic.hh" 69#include "sim/eventq.hh" 70 71class ThreadContext; 72class BaseCPU; 73 74namespace X86ISA { 75 76class Interrupts : public BasicPioDevice, IntDev 77{ 78 protected: 79 // Storage for the APIC registers 80 uint32_t regs[NUM_APIC_REGS]; 81 82 BitUnion32(LVTEntry) 83 Bitfield<7, 0> vector; 84 Bitfield<10, 8> deliveryMode; 85 Bitfield<12> status; 86 Bitfield<13> polarity; 87 Bitfield<14> remoteIRR; 88 Bitfield<15> trigger; 89 Bitfield<16> masked; 90 Bitfield<17> periodic; 91 EndBitUnion(LVTEntry) 92 93 /* 94 * Timing related stuff. 95 */ 96 Tick latency; 97 Tick clock; 98 99 class ApicTimerEvent : public Event 100 { 101 private: 102 Interrupts *localApic; 103 public: 104 ApicTimerEvent(Interrupts *_localApic) : 105 Event(), localApic(_localApic) 106 {} 107 108 void process() 109 { 110 assert(localApic); 111 if (localApic->triggerTimerInterrupt()) { 112 localApic->setReg(APIC_INITIAL_COUNT, 113 localApic->readReg(APIC_INITIAL_COUNT)); 114 } 115 } 116 }; 117 118 ApicTimerEvent apicTimerEvent; 119 120 /* 121 * A set of variables to keep track of interrupts that don't go through 122 * the IRR. 123 */ 124 bool pendingSmi; 125 uint8_t smiVector; 126 bool pendingNmi; 127 uint8_t nmiVector; 128 bool pendingExtInt; 129 uint8_t extIntVector; 130 bool pendingInit; 131 uint8_t initVector; 132 bool pendingStartup; 133 uint8_t startupVector; 134 135 // This is a quick check whether any of the above (except ExtInt) are set. 136 bool pendingUnmaskableInt; 137 138 /* 139 * IRR and ISR maintenance. 140 */ 141 uint8_t IRRV; 142 uint8_t ISRV; 143 144 int 145 findRegArrayMSB(ApicRegIndex base) 146 { 147 int offset = 7; 148 do { 149 if (regs[base + offset] != 0) { 150 return offset * 32 + findMsbSet(regs[base + offset]); 151 } 152 } while (offset--); 153 return 0; 154 } 155 156 void 157 updateIRRV() 158 { 159 IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE); 160 } 161 162 void 163 updateISRV() 164 { 165 ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE); 166 } 167 168 void 169 setRegArrayBit(ApicRegIndex base, uint8_t vector) 170 { 171 regs[base + (vector % 32)] |= (1 << (vector >> 5)); 172 } 173 174 void 175 clearRegArrayBit(ApicRegIndex base, uint8_t vector) 176 { 177 regs[base + (vector % 32)] &= ~(1 << (vector >> 5)); 178 } 179 180 bool 181 getRegArrayBit(ApicRegIndex base, uint8_t vector) 182 { 183 return bits(regs[base + (vector % 32)], vector >> 5); 184 } 185 186 void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level); 187 188 BaseCPU *cpu; 189 190 public: 191 /* 192 * Params stuff. 193 */ 194 typedef X86LocalApicParams Params; 195 196 void setCPU(BaseCPU * newCPU); 197 198 void 199 setClock(Tick newClock) 200 { 201 clock = newClock; 202 } 203 204 const Params * 205 params() const 206 { 207 return dynamic_cast<const Params *>(_params); 208 } 209 210 /* 211 * Functions to interact with the interrupt port from IntDev. 212 */ 213 Tick read(PacketPtr pkt); 214 Tick write(PacketPtr pkt); 215 Tick recvMessage(PacketPtr pkt); 216 217 bool 218 triggerTimerInterrupt() 219 { 220 LVTEntry entry = regs[APIC_LVT_TIMER]; 221 if (!entry.masked) 222 requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger); 223 return entry.periodic; 224 } 225 226 void addressRanges(AddrRangeList &range_list); 227 void getIntAddrRange(AddrRangeList &range_list); 228 229 Port *getPort(const std::string &if_name, int idx = -1) 230 { 231 if (if_name == "int_port") 232 return intPort; 233 return BasicPioDevice::getPort(if_name, idx); 234 } 235 236 /* 237 * Functions to access and manipulate the APIC's registers. 238 */ 239 240 uint32_t readReg(ApicRegIndex miscReg); 241 void setReg(ApicRegIndex reg, uint32_t val); 242 void 243 setRegNoEffect(ApicRegIndex reg, uint32_t val) 244 { 245 regs[reg] = val; 246 } 247 248 /* 249 * Constructor. 250 */ 251 252 Interrupts(Params * p); 253 254 /* 255 * Functions for retrieving interrupts for the CPU to handle. 256 */ 257 258 bool checkInterrupts(ThreadContext *tc) const; 259 Fault getInterrupt(ThreadContext *tc); 260 void updateIntrInfo(ThreadContext *tc); 261 262 /* 263 * Serialization. 264 */ 265 266 void 267 serialize(std::ostream &os) 268 { 269 panic("Interrupts::serialize unimplemented!\n"); 270 } 271 272 void 273 unserialize(Checkpoint *cp, const std::string §ion) 274 { 275 panic("Interrupts::unserialize unimplemented!\n"); 276 } 277 278 /* 279 * Old functions needed for compatability but which will be phased out 280 * eventually. 281 */ 282 void 283 post(int int_num, int index) 284 { 285 panic("Interrupts::post unimplemented!\n"); 286 } 287 288 void 289 clear(int int_num, int index) 290 { 291 panic("Interrupts::clear unimplemented!\n"); 292 } 293 294 void 295 clearAll() 296 { 297 panic("Interrupts::clearAll unimplemented!\n"); 298 } 299}; 300 301} // namespace X86ISA 302 303#endif // __ARCH_X86_INTERRUPTS_HH__ 304