interrupts.hh revision 6041
1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use of this software in source and binary forms, 6 * with or without modification, are permitted provided that the 7 * following conditions are met: 8 * 9 * The software must be used only for Non-Commercial Use which means any 10 * use which is NOT directed to receiving any direct monetary 11 * compensation for, or commercial advantage from such use. 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Derivatives of the software may be shared with 37 * others provided: (i) the others agree to abide by the list of 38 * conditions herein which includes the Non-Commercial Use restrictions; 39 * and (ii) such Derivatives of the software include the above copyright 40 * notice to acknowledge the contribution from this software where 41 * applicable, this list of conditions and the disclaimer below. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * 55 * Authors: Gabe Black 56 */ 57 58#ifndef __ARCH_X86_INTERRUPTS_HH__ 59#define __ARCH_X86_INTERRUPTS_HH__ 60 61#include "arch/x86/apicregs.hh" 62#include "arch/x86/faults.hh" 63#include "arch/x86/intmessage.hh" 64#include "base/bitfield.hh" 65#include "cpu/thread_context.hh" 66#include "dev/io_device.hh" 67#include "dev/x86/intdev.hh" 68#include "params/X86LocalApic.hh" 69#include "sim/eventq.hh" 70 71class ThreadContext; 72class BaseCPU; 73 74namespace X86ISA { 75 76class Interrupts : public BasicPioDevice, IntDev 77{ 78 protected: 79 // Storage for the APIC registers 80 uint32_t regs[NUM_APIC_REGS]; 81 82 BitUnion32(LVTEntry) 83 Bitfield<7, 0> vector; 84 Bitfield<10, 8> deliveryMode; 85 Bitfield<12> status; 86 Bitfield<13> polarity; 87 Bitfield<14> remoteIRR; 88 Bitfield<15> trigger; 89 Bitfield<16> masked; 90 Bitfield<17> periodic; 91 EndBitUnion(LVTEntry) 92 93 /* 94 * Timing related stuff. 95 */ 96 Tick latency; 97 Tick clock; 98 99 class ApicTimerEvent : public Event 100 { 101 private: 102 Interrupts *localApic; 103 public: 104 ApicTimerEvent(Interrupts *_localApic) : 105 Event(), localApic(_localApic) 106 {} 107 108 void process() 109 { 110 assert(localApic); 111 if (localApic->triggerTimerInterrupt()) { 112 localApic->setReg(APIC_INITIAL_COUNT, 113 localApic->readReg(APIC_INITIAL_COUNT)); 114 } 115 } 116 }; 117 118 ApicTimerEvent apicTimerEvent; 119 120 /* 121 * A set of variables to keep track of interrupts that don't go through 122 * the IRR. 123 */ 124 bool pendingSmi; 125 uint8_t smiVector; 126 bool pendingNmi; 127 uint8_t nmiVector; 128 bool pendingExtInt; 129 uint8_t extIntVector; 130 bool pendingInit; 131 uint8_t initVector; 132 133 // This is a quick check whether any of the above (except ExtInt) are set. 134 bool pendingUnmaskableInt; 135 136 /* 137 * IRR and ISR maintenance. 138 */ 139 uint8_t IRRV; 140 uint8_t ISRV; 141 142 int 143 findRegArrayMSB(ApicRegIndex base) 144 { 145 int offset = 7; 146 do { 147 if (regs[base + offset] != 0) { 148 return offset * 32 + findMsbSet(regs[base + offset]); 149 } 150 } while (offset--); 151 return 0; 152 } 153 154 void 155 updateIRRV() 156 { 157 IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE); 158 } 159 160 void 161 updateISRV() 162 { 163 ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE); 164 } 165 166 void 167 setRegArrayBit(ApicRegIndex base, uint8_t vector) 168 { 169 regs[base + (vector % 32)] |= (1 << (vector >> 5)); 170 } 171 172 void 173 clearRegArrayBit(ApicRegIndex base, uint8_t vector) 174 { 175 regs[base + (vector % 32)] &= ~(1 << (vector >> 5)); 176 } 177 178 bool 179 getRegArrayBit(ApicRegIndex base, uint8_t vector) 180 { 181 return bits(regs[base + (vector % 32)], vector >> 5); 182 } 183 184 void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level); 185 186 BaseCPU *cpu; 187 188 public: 189 /* 190 * Params stuff. 191 */ 192 typedef X86LocalApicParams Params; 193 194 void setCPU(BaseCPU * newCPU); 195 196 void 197 setClock(Tick newClock) 198 { 199 clock = newClock; 200 } 201 202 const Params * 203 params() const 204 { 205 return dynamic_cast<const Params *>(_params); 206 } 207 208 /* 209 * Functions to interact with the interrupt port from IntDev. 210 */ 211 Tick read(PacketPtr pkt); 212 Tick write(PacketPtr pkt); 213 Tick recvMessage(PacketPtr pkt); 214 215 bool 216 triggerTimerInterrupt() 217 { 218 LVTEntry entry = regs[APIC_LVT_TIMER]; 219 if (!entry.masked) 220 requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger); 221 return entry.periodic; 222 } 223 224 void addressRanges(AddrRangeList &range_list); 225 void getIntAddrRange(AddrRangeList &range_list); 226 227 Port *getPort(const std::string &if_name, int idx = -1) 228 { 229 if (if_name == "int_port") 230 return intPort; 231 return BasicPioDevice::getPort(if_name, idx); 232 } 233 234 /* 235 * Functions to access and manipulate the APIC's registers. 236 */ 237 238 uint32_t readReg(ApicRegIndex miscReg); 239 void setReg(ApicRegIndex reg, uint32_t val); 240 void 241 setRegNoEffect(ApicRegIndex reg, uint32_t val) 242 { 243 regs[reg] = val; 244 } 245 246 /* 247 * Constructor. 248 */ 249 250 Interrupts(Params * p); 251 252 /* 253 * Functions for retrieving interrupts for the CPU to handle. 254 */ 255 256 bool checkInterrupts(ThreadContext *tc) const; 257 Fault getInterrupt(ThreadContext *tc); 258 void updateIntrInfo(ThreadContext *tc); 259 260 /* 261 * Serialization. 262 */ 263 264 void 265 serialize(std::ostream &os) 266 { 267 panic("Interrupts::serialize unimplemented!\n"); 268 } 269 270 void 271 unserialize(Checkpoint *cp, const std::string §ion) 272 { 273 panic("Interrupts::unserialize unimplemented!\n"); 274 } 275 276 /* 277 * Old functions needed for compatability but which will be phased out 278 * eventually. 279 */ 280 void 281 post(int int_num, int index) 282 { 283 panic("Interrupts::post unimplemented!\n"); 284 } 285 286 void 287 clear(int int_num, int index) 288 { 289 panic("Interrupts::clear unimplemented!\n"); 290 } 291 292 void 293 clearAll() 294 { 295 panic("Interrupts::clearAll unimplemented!\n"); 296 } 297}; 298 299} // namespace X86ISA 300 301#endif // __ARCH_X86_INTERRUPTS_HH__ 302