interrupts.hh revision 9554
16019Shines@cs.fsu.edu/* 26019Shines@cs.fsu.edu * Copyright (c) 2012 ARM Limited 37100Sgblack@eecs.umich.edu * All rights reserved 47100Sgblack@eecs.umich.edu * 57100Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67100Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77100Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87100Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97100Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107100Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117100Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127100Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137100Sgblack@eecs.umich.edu * 147100Sgblack@eecs.umich.edu * Copyright (c) 2007 The Hewlett-Packard Development Company 156019Shines@cs.fsu.edu * All rights reserved. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * The license below extends only to copyright in the software and shall 186019Shines@cs.fsu.edu * not be construed as granting a license to any other intellectual 196019Shines@cs.fsu.edu * property including but not limited to intellectual property relating 206019Shines@cs.fsu.edu * to a hardware implementation of the functionality of the software 216019Shines@cs.fsu.edu * licensed hereunder. You may use the software subject to the license 226019Shines@cs.fsu.edu * terms below provided that you ensure that this notice is replicated 236019Shines@cs.fsu.edu * unmodified and in its entirety in all distributions of the software, 246019Shines@cs.fsu.edu * modified or unmodified, in source code or in binary form. 256019Shines@cs.fsu.edu * 266019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 276019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 286019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 296019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 306019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 316019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 326019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 336019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 346019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 356019Shines@cs.fsu.edu * this software without specific prior written permission. 366019Shines@cs.fsu.edu * 376019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 386019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 396019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 406019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 416019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 426757SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 436019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 446019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 456019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 466019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 476019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 486019Shines@cs.fsu.edu * 496019Shines@cs.fsu.edu * Authors: Gabe Black 509022Sgblack@eecs.umich.edu * Andreas Hansson 516019Shines@cs.fsu.edu */ 527170Sgblack@eecs.umich.edu 536253Sgblack@eecs.umich.edu#ifndef __ARCH_X86_INTERRUPTS_HH__ 547202Sgblack@eecs.umich.edu#define __ARCH_X86_INTERRUPTS_HH__ 556253Sgblack@eecs.umich.edu 566253Sgblack@eecs.umich.edu#include "arch/x86/regs/apic.hh" 577396Sgblack@eecs.umich.edu#include "arch/x86/faults.hh" 588745Sgblack@eecs.umich.edu#include "arch/x86/intmessage.hh" 597405SAli.Saidi@ARM.com#include "base/bitfield.hh" 608782Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 618782Sgblack@eecs.umich.edu#include "dev/x86/intdev.hh" 628782Sgblack@eecs.umich.edu#include "dev/io_device.hh" 637259Sgblack@eecs.umich.edu#include "params/X86LocalApic.hh" 648757Sgblack@eecs.umich.edu#include "sim/eventq.hh" 658782Sgblack@eecs.umich.edu 668757Sgblack@eecs.umich.educlass ThreadContext; 678777Sgblack@eecs.umich.educlass BaseCPU; 688782Sgblack@eecs.umich.edu 698756Sgblack@eecs.umich.eduint divideFromConf(uint32_t conf); 706019Shines@cs.fsu.edu 716757SAli.Saidi@ARM.comnamespace X86ISA { 728757Sgblack@eecs.umich.edu 736019Shines@cs.fsu.eduApicRegIndex decodeAddr(Addr paddr); 748745Sgblack@eecs.umich.edu 759384SAndreas.Sandberg@arm.comclass Interrupts : public BasicPioDevice, IntDev 766397Sgblack@eecs.umich.edu{ 778782Sgblack@eecs.umich.edu protected: 786019Shines@cs.fsu.edu // Storage for the APIC registers 796397Sgblack@eecs.umich.edu uint32_t regs[NUM_APIC_REGS]; 808335Snate@binkert.org 819023Sgblack@eecs.umich.edu BitUnion32(LVTEntry) 829023Sgblack@eecs.umich.edu Bitfield<7, 0> vector; 838335Snate@binkert.org Bitfield<10, 8> deliveryMode; 846019Shines@cs.fsu.edu Bitfield<12> status; 856019Shines@cs.fsu.edu Bitfield<13> polarity; 866019Shines@cs.fsu.edu Bitfield<14> remoteIRR; 876019Shines@cs.fsu.edu Bitfield<15> trigger; 886019Shines@cs.fsu.edu Bitfield<16> masked; 896019Shines@cs.fsu.edu Bitfield<17> periodic; 906019Shines@cs.fsu.edu EndBitUnion(LVTEntry) 916019Shines@cs.fsu.edu 92 /* 93 * Timing related stuff. 94 */ 95 Tick latency; 96 97 class ApicTimerEvent : public Event 98 { 99 private: 100 Interrupts *localApic; 101 public: 102 ApicTimerEvent(Interrupts *_localApic) : 103 Event(), localApic(_localApic) 104 {} 105 106 void process() 107 { 108 assert(localApic); 109 if (localApic->triggerTimerInterrupt()) { 110 localApic->setReg(APIC_INITIAL_COUNT, 111 localApic->readReg(APIC_INITIAL_COUNT)); 112 } 113 } 114 }; 115 116 ApicTimerEvent apicTimerEvent; 117 118 /* 119 * A set of variables to keep track of interrupts that don't go through 120 * the IRR. 121 */ 122 bool pendingSmi; 123 uint8_t smiVector; 124 bool pendingNmi; 125 uint8_t nmiVector; 126 bool pendingExtInt; 127 uint8_t extIntVector; 128 bool pendingInit; 129 uint8_t initVector; 130 bool pendingStartup; 131 uint8_t startupVector; 132 bool startedUp; 133 134 // This is a quick check whether any of the above (except ExtInt) are set. 135 bool pendingUnmaskableInt; 136 137 // A count of how many IPIs are in flight. 138 int pendingIPIs; 139 140 /* 141 * IRR and ISR maintenance. 142 */ 143 uint8_t IRRV; 144 uint8_t ISRV; 145 146 int 147 findRegArrayMSB(ApicRegIndex base) 148 { 149 int offset = 7; 150 do { 151 if (regs[base + offset] != 0) { 152 return offset * 32 + findMsbSet(regs[base + offset]); 153 } 154 } while (offset--); 155 return 0; 156 } 157 158 void 159 updateIRRV() 160 { 161 IRRV = findRegArrayMSB(APIC_INTERRUPT_REQUEST_BASE); 162 } 163 164 void 165 updateISRV() 166 { 167 ISRV = findRegArrayMSB(APIC_IN_SERVICE_BASE); 168 } 169 170 void 171 setRegArrayBit(ApicRegIndex base, uint8_t vector) 172 { 173 regs[base + (vector / 32)] |= (1 << (vector % 32)); 174 } 175 176 void 177 clearRegArrayBit(ApicRegIndex base, uint8_t vector) 178 { 179 regs[base + (vector / 32)] &= ~(1 << (vector % 32)); 180 } 181 182 bool 183 getRegArrayBit(ApicRegIndex base, uint8_t vector) 184 { 185 return bits(regs[base + (vector / 32)], vector % 5); 186 } 187 188 void requestInterrupt(uint8_t vector, uint8_t deliveryMode, bool level); 189 190 BaseCPU *cpu; 191 192 int initialApicId; 193 194 // Port for receiving interrupts 195 IntSlavePort intSlavePort; 196 197 public: 198 199 int getInitialApicId() { return initialApicId; } 200 201 /* 202 * Params stuff. 203 */ 204 typedef X86LocalApicParams Params; 205 206 void setCPU(BaseCPU * newCPU); 207 208 const Params * 209 params() const 210 { 211 return dynamic_cast<const Params *>(_params); 212 } 213 214 /* 215 * Initialize this object by registering it with the IO APIC. 216 */ 217 void init(); 218 219 /* 220 * Functions to interact with the interrupt port from IntDev. 221 */ 222 Tick read(PacketPtr pkt); 223 Tick write(PacketPtr pkt); 224 Tick recvMessage(PacketPtr pkt); 225 Tick recvResponse(PacketPtr pkt); 226 227 bool 228 triggerTimerInterrupt() 229 { 230 LVTEntry entry = regs[APIC_LVT_TIMER]; 231 if (!entry.masked) 232 requestInterrupt(entry.vector, entry.deliveryMode, entry.trigger); 233 return entry.periodic; 234 } 235 236 AddrRangeList getAddrRanges() const; 237 AddrRangeList getIntAddrRange() const; 238 239 BaseMasterPort &getMasterPort(const std::string &if_name, 240 PortID idx = InvalidPortID) 241 { 242 if (if_name == "int_master") { 243 return intMasterPort; 244 } 245 return BasicPioDevice::getMasterPort(if_name, idx); 246 } 247 248 BaseSlavePort &getSlavePort(const std::string &if_name, 249 PortID idx = InvalidPortID) 250 { 251 if (if_name == "int_slave") { 252 return intSlavePort; 253 } 254 return BasicPioDevice::getSlavePort(if_name, idx); 255 } 256 257 /* 258 * Functions to access and manipulate the APIC's registers. 259 */ 260 261 uint32_t readReg(ApicRegIndex miscReg); 262 void setReg(ApicRegIndex reg, uint32_t val); 263 void 264 setRegNoEffect(ApicRegIndex reg, uint32_t val) 265 { 266 regs[reg] = val; 267 } 268 269 /* 270 * Constructor. 271 */ 272 273 Interrupts(Params * p); 274 275 /* 276 * Functions for retrieving interrupts for the CPU to handle. 277 */ 278 279 bool checkInterrupts(ThreadContext *tc) const; 280 Fault getInterrupt(ThreadContext *tc); 281 void updateIntrInfo(ThreadContext *tc); 282 283 /* 284 * Serialization. 285 */ 286 287 virtual void serialize(std::ostream &os); 288 virtual void unserialize(Checkpoint *cp, const std::string §ion); 289 290 /* 291 * Old functions needed for compatability but which will be phased out 292 * eventually. 293 */ 294 void 295 post(int int_num, int index) 296 { 297 panic("Interrupts::post unimplemented!\n"); 298 } 299 300 void 301 clear(int int_num, int index) 302 { 303 panic("Interrupts::clear unimplemented!\n"); 304 } 305 306 void 307 clearAll() 308 { 309 panic("Interrupts::clearAll unimplemented!\n"); 310 } 311}; 312 313} // namespace X86ISA 314 315#endif // __ARCH_X86_INTERRUPTS_HH__ 316